JPH04152731A - Digital data transmitter - Google Patents

Abstract

PURPOSE:To efficiently send a digital data by checking a bit sequence of a transmission data so as to insert a 2nd digital data or a dummy data '1' adaptively to a predetermined bit location. CONSTITUTION:A pattern check circuit 107 checks a bit sequence of a transmission data 1(102) based on a frame pulse (101) and an n-bit block timing pulse 107d, sets a pulse to multiplex a '1' data to a 1st bit of a relevant block when a '0' data of m bits or over is in existence in a bit sequence comprising two blocks, a preceding block and a relevant block and sets a pulse to multiplex a transmission data 2 in a timing of a 1st bit of the relevant block when not in existence and gives the relevant block to a multiplexer circuit 110 and a NAND gate 109. After the data is respectively multiplexed, the result is fed to a unipolar bipolar conversion circuit 111, in which the data is converted into a bipolar signal that is able to be sent for a long distance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital data transmission device that can efficiently transmit data even through a transmission path where there are restrictions on the bit sequence of transmission data.

[Prior Art] In a PCM transmission system, when digital pig pit logic "0" occurs continuously.

There is a drawback that phase jitter occurs in the timing signal when reproducing the timing signal in the PCM repeater, which causes errors in the reproduced code. For this reason, in conventional transmission systems, the above-mentioned drawbacks have been addressed by using a zero pattern suppression circuit that prevents the continuous occurrence of logic "0".

To be more specific, this suppression circuit monitors the input data pit string to the PCM terminal device word by word, and when a continuous word of ``0'' data is detected.

Forces the least weighted bit in the word to be “l”
However, if such a suppression circuit is applied to an interframe encoding device that targets a signal from which redundant bits have been removed, such as a band-compressed digital image signal, the image quality will be degraded by 2 or more. Therefore, this device is designed to solve this problem.

A forced insertion circuit is used that forcibly inserts "1" data into the transmission data at a fixed period, and prevents "0" data from occurring continuously over a predetermined value.

For example, in the United States, there is a transmission path that requires that the bit sequence to be transmitted has 3 or more 1° data in any 24-bit sequence with no more than 15 successive occurrences of 0° data. When data is transmitted using such a transmission path, "1 degree data is forcibly inserted every 8 bits."

[Problem to be solved by the invention] However, the conventional forced insertion circuit described above has the disadvantage that data transmission efficiency is significantly reduced because "1" data is forcibly inserted even in areas where "12" data insertion is unnecessary. there were.

SUMMARY OF THE INVENTION In view of these drawbacks, it is an object of the present invention to provide a digital data transmission device that can efficiently transmit digital data even if there are restrictions on the bit sequence of a transmission path.

[Means for Solving the Problems] According to the present invention, there is provided a digital data transmission device comprising a bit sequence of "O" and "1".

(1> Frame configuring means for configuring a digital data transmission frame; block configuring means for configuring a block of n (where n≧2) bit strings synchronized with this digital data transmission frame; a first multiplexing means for multiplexing the first digital data;

If there are consecutive m (m≧1) bits or more of “0” data in the bit sequence spanning the previous block and the current block, “]’ data is multiplexed to the first bit of the current block, and the consecutive m bits are and a second multiplexing means for multiplexing the second digital data onto the first bit of the block when the "O° data does not exist."

(2) Reference frame configuring means for configuring a reference frame by detecting a frame synchronization signal synchronized with the transmission frame from the multiplexed digital data received from the transmission path.

block detecting means for detecting the division of blocks in the n-bi soto array synchronized with the reference frame;

a first separating means for separating the first digital data multiplexed in the eleventh bit from the second bit of the detected block; 1) When there is '01 data of BiSoto or more, "1" is set from the first bit of the block.
° a receiving unit comprising a second multiplexing means for separating the data and separating the second digital data from the first bit of the block when there is no continuous 0° data of m or more bits; A digital data transmission device is obtained.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a digital data transmission device according to an embodiment of the present invention. In this figure, 1 is a transmission unit that creates transmission data, 2 is a transmission path that transmits the transmission data created by transmission unit 1, and 3 is a reception unit that receives transmission data transmitted to transmission path 2 and decodes the data. Department.

First, the transmitter 1 will be explained in detail.

First digital data (transmission data 1) is input to the input terminal 102, and a frame node indicating the bit sequence of the transmission data 1 is input to the input terminal 01. This frame pulse is supplied to a frame configuration circuit 106 and a pattern detection circuit 107.

The frame configuration circuit 106 is a kind of pulse generator that configures a transmission path frame based on the supplied frame pulse, and generates timing pulses for configuring a program consisting of n bits synchronized with this transmission path frame. 1
07d is sent to the turn detection circuit 107. The frame configuration circuit 106 also generates a frame synchronization signal 106C synchronized with the transmission path frame and a frame synchronization signal 106C synchronized with the transmission line frame.
and a frame pulse 106a for multiplexing 06C.

Second digital data (transmission data 2) to be described later or a block pulse 106b indicating the timing for forcibly inserting "1" data is sent to the multiplexing circuit 110.

The pattern detection circuit 107 uses a frame nox (101
) and n (however, n≧2) timing pulse 107d of bi-nodpro-tsuk as a reference, transmission data 1 (102
), and check the bit sequence of m in the bit sequence consisting of the previous block and the second block of the corresponding block.
(however, m≧1) bits or more “0” data is determined whether it is consecutive or not, and if there is consecutive m (however m≧1) and “01” data of soto or more bits, the If 1 degree data is multiplexed into 1 bit and there is no 0 data of 1m bits or more, a pulse is generated to multiplex transmission data 2 at the timing of the 1st bit of the corresponding block, and this is multiplexed. circuit 110 and NAN
Supplied to D gate 109. This pulse is transmitted data 2
This becomes a selection signal.

Note that the transmission data 1 (102) is stored in the register 108 until the determination result by the turn detection circuit 107 is output, and then led to the multiplexing circuit 110, where it is multiplexed.

Further, the transmission data 2 selection signal is transmitted to the NAND gate 109.
The signal is gated by the clock (CLK) at , and is output to the output terminal 104 as a data 2 request signal. In response to this data 2 request signal (104), the second digital signal (transmission data 2) is sequentially input from the input terminal 103 and guided to the multiplexing circuit 110.

In the multiplexing circuit 110, the frame synchronization signal 106C is generated by the frame pulse 106a, and the transmission data 1. Transmission data 2. After multiplexing the "1' data, they are supplied to the unipolar/bipolar conversion circuit 111, where they are converted into bipolar signals that can be transmitted over long distances, and sent to the transmission line 2 via the output terminal 105. .

Next, the receiving section will be explained in detail.

The multiplexed bipolar signal received from input terminal 305 is converted to a unipolar signal in bipolar-unipolar conversion circuit 308, and then sent to frame synchronization circuit 306. Pattern detection circuit 307. and register 309, respectively.

The frame synchronization circuit 306 detects a frame synchronization signal multiplexed by the transmitter from among the received multiplexed data to configure a reference frame of the multiplexed data, and
A frame pulse 306d indicating the position where the frame synchronization signal is multiplexed and a block pulse 30 indicating the division of a block consisting of n bits are sent to the pattern detection circuit 307.
6c, a frame pulse 306a indicating the bit sequence of the first digital data (received data 1) is sent to the output terminal 301, and a received data 1 selection pulse 306b is sent to the register 310, respectively.

Similar to the pattern detection circuit 107 of the transmitting section, the pattern detection circuit 307 checks the bit/- sense of the data in the received multiplexed data based on the frame pulse 306d and the block pulse 306C, and distinguishes between the previous block and the corresponding block. It is determined whether “0° data of m (however, m≧1) bits or more is consecutive in the bit sequence consisting of two blocks, and if there is no “0° data of 1m bits or more, the corresponding block is It is determined that data 2 is multiplexed in the first bit.

A data 2 selection signal is sent to the NAND gate 312.

The register 309 is a circuit that delays the received multiplexed data in order to compensate for the delay time until the determination result is output in the pattern detection circuit 307. The multiplexed data delayed here is stored as data 1 in the register 310.
Only the received data 1 is output to the output terminal 302 by the selection pulse.

Note that the data 2 selection signal is gated by a clock (CLK) through a NAND gate 3]2, guided to a register 311, selects only received data 2 from among the received data, and outputs it to an output terminal 303. It is output as a 304 datater 2 request signal.

Next, a specific example of a transmission path will be explained.

FIG. 2 shows an operation time chart when, for example, a T1 line in the United States is used.

In this example, the transmission path speed is 1.544 Mb/s.

A frame is configured in units of 193 bits, and a frame synchronization signal is inserted every 193 bits.

Further, the block length n is set to 8, and the determination value m of continuous "O" data is set to 7.

Referring to FIG. 2, frame pulse (101) or 19
This frame pulse (101
) is constructed in units of 8 bits (B1 to B24). Furthermore, valid data of the transmission data 1 is input between the second bit and the eighth bit of each block. The pattern detection circuit 1 detects the transmission data 1.
07, 307 to determine what is to be multiplexed to the first bit of each block or whether it has been multiplexed. For example, in the example of Fig. 2, the first block (B
1) and the second block (B2), there are nine consecutive "O° data," so dummy data "1" is inserted into the first bit of the second block, and on the other hand, The 24th block (B24) and the 1st block (B1
), the longest series of 0° data present in the pitton sequence is 5, so data 2 is multiplexed into the first bit of the first block.

In this way, the multiplexed transmission data (110) no longer contains 8 bits or more of consecutive "0" data.

In the operation time chart of FIG. 2, the frame length is 193 bits, and n is 8. Although the explanation has been made assuming that m is 7, the present invention is not limited to these examples.

It is also possible to carry out using the values of each pressure type. Further, the relative positional relationship between the frame pulse and the block can also be set arbitrarily.

[Effects of the Invention] As explained above, in the present invention, by checking the bit sequence of transmission data, second digital data or dummy data is inserted into a predetermined bit position.
1m is inserted adaptively, so if there is a constraint on the "0° data" that occurs continuously during the transmission data pitton sequence2.For example, if there are 15 consecutive occurrences of "01" in the bit sequence you want to transmit, Even if the condition is as follows and three or more "1's" exist in any 24-bit sequence, it is possible to efficiently transmit digital data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital data transmission device according to an embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation of the digital data transmission device of this embodiment. In the figure. U...Transmission unit, 2...Transmission path, 3...Reception unit, 10
1゜102.103.305...Input terminal, 104,
105.301,302,303...output terminal, 10
6...Frame configuration circuit, 107.307...Pattern detection circuit, 108,309...Delay circuit (register), 109,312...NAND gate, 110...
- Multiplexing circuit, 11 units... Unipolar/bipolar conversion circuit 08... Bipolar/unipolar conversion circuit 6... Frame synchronization circuit 1... Register. Figure/1

Claims (3)

[Claims] (1) A digital data transmission device consisting of a bit sequence of “0” and “1”, comprising a frame configuring means configuring a digital data transmission frame, and a frame configuring means configuring a digital data transmission frame, and ) block configuring means for configuring blocks of bit strings; first multiplexing means for multiplexing first digital data from the second bit to the nth bit of these blocks; When there is continuous "0" data of m or more bits (m≧1), "1" data is multiplexed to the first bit of the block, and when there is no continuous "0" data of m or more bits. A digital data transmission device includes a transmitting section including a second multiplexing means for multiplexing second digital data onto the first bit of the block. (2) A digital data transmission device consisting of a bit sequence of “0” and “1”, which detects a frame synchronization signal synchronized with a transmission frame from multiplexed digital data received from a transmission path to construct a reference frame. a reference frame configuring means for composing a block of n bit strings synchronized with this reference frame; a first separation means for separating data, and when there is continuous "0" data of m (however, m≧1) bits or more in the bit sequence spanning the previous block and the current block, the first bit of the current block is separated from the first bit of the current block; 1"
A digital receiver comprising a second multiplexing means that separates the data and separates the second digital data from the first bit of the block when there is no continuous "0" data of m or more bits. Data transmission equipment. (3) A digital data transmission device consisting of a bit sequence of "0" and "1", comprising a transmitting section as set forth in claim (1) and a receiving unit as set forth in claim (2). A digital data transmission device comprising: