JPH04152561A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04152561A JPH04152561A JP27671790A JP27671790A JPH04152561A JP H04152561 A JPH04152561 A JP H04152561A JP 27671790 A JP27671790 A JP 27671790A JP 27671790 A JP27671790 A JP 27671790A JP H04152561 A JPH04152561 A JP H04152561A
- Authority
- JP
- Japan
- Prior art keywords
- high resistance
- semiconductor device
- polycrystalline silicon
- resistance region
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 6
- 230000003068 static effect Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 101100232435 Arabidopsis thaliana NUC gene Proteins 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の構造の改良に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to improvements in the structure of semiconductor devices.
従来の構造を第２図（α）ｊ（ｂ）にそれぞれ平面図、
断面図を示す。The conventional structure is shown in Fig. 2 (α) and (b) respectively.
A cross-sectional view is shown.
図中に於いて、１は基板、２は素子分離絶縁膜５はゲー
ト絶縁膜、４はゲート電極、５は層間絶縁膜、６は多結
晶シリコン高抵抗部分、７は多結晶シリコン低抵抗部分
、８はレジストパターン９は接続開口部である。In the figure, 1 is a substrate, 2 is an element isolation insulating film 5 is a gate insulating film, 4 is a gate electrode, 5 is an interlayer insulating film, 6 is a polycrystalline silicon high resistance part, and 7 is a polycrystalline silicon low resistance part , 8, the resist pattern 9 is a connection opening.
従来多結晶シリコンを用いた抵抗が用いられているが、
特に不純物を微量に導入または全（導入しないと高抵抗
が得られこれを回路に用いられて米でおり、良（知られ
た例としてスタティックＲＡＭがある。Conventionally, resistors using polycrystalline silicon have been used, but
In particular, if a trace amount of impurities or no impurities are introduced, a high resistance is obtained and this is used in circuits.Static RAM is a well-known example.
従来技術に於いて、第２図Ｃｂ）に示すように、高抵抗
部６と低抵抗部７との境界と接続開口部との距離ｔはレ
ジストパターン８を形成する時のアライメント余裕を考
慮して設定していた。しかし素子の微細化に伴ないこの
アライメント余裕が例えばスタティックＲＡＭで言えば
メモリーセルサイズの縮小化を難しくシ、さらには、こ
れを確保しようとすると高抵抗自体の寸法Ｓを小さくせ
ねばならず、これはＩＤＤ８のノ（ラツキを招いた。In the prior art, as shown in FIG. 2Cb), the distance t between the boundary between the high resistance part 6 and the low resistance part 7 and the connection opening is determined by taking into account the alignment margin when forming the resist pattern 8. was set. However, with the miniaturization of elements, this alignment margin makes it difficult to reduce the memory cell size, for example in static RAM, and furthermore, if this is to be ensured, the dimension S of the high resistance itself must be reduced. This caused IDD8's no(ratsuki).
本発明はかかる不具合を解決することを目的とする。The present invention aims to solve such problems.
本発明は少なくとも２層の配線からなり、上層の配線層
は多結晶シリコンからなり、該上層の配線層には高濃度
不純物が導入された低抵抗領域と不純物を微量を含む又
は含まない高抵抗領域を有す半導体装置に於いて、該２
層の配線層の接続開口部上に前記上層配線に於ける高抵
抗領域と低抵抗領域の境界があることを特徴とする半導
体装置である。The present invention consists of at least two layers of wiring, the upper wiring layer is made of polycrystalline silicon, and the upper wiring layer has a low resistance region doped with high concentration impurities and a high resistance region containing or not containing trace amounts of impurities. In a semiconductor device having a region, said 2
The semiconductor device is characterized in that there is a boundary between a high resistance region and a low resistance region in the upper layer wiring above the connection opening of the wiring layer of the layer.
第１図ｃａ＞ 、 （ｂ＞に本発明の実施例を示す平面
図および断面図であり同一符号は同一部分を示す。FIGS. 1A and 1B are a plan view and a sectional view showing an embodiment of the present invention, and the same reference numerals indicate the same parts.
本発明の構造に於いて、多結晶シリコンの高抵抗部６と
低抵抗部７との境界を接続開口部９上に設けることによ
って、高抵抗部の寸法の確保と縮小化が可能となる。こ
れを実現しようとするときゲート電極４と多結晶シリコ
ン７との接触抵抗が高くなってしまうことが予想される
が、低抵抗部の不純物をＰとしたとき後の熱処理９００
℃Ｎ。In the structure of the present invention, by providing the boundary between the high resistance part 6 and the low resistance part 7 of polycrystalline silicon on the connection opening 9, it is possible to secure and reduce the size of the high resistance part. When trying to realize this, it is expected that the contact resistance between the gate electrode 4 and the polycrystalline silicon 7 will increase, but when the impurity in the low resistance part is P, the subsequent heat treatment 900
℃N.
５０分として１．８μＡｓとしたとき１μ横方向に拡散
する。そのため本発明のような構造を用いても接触抵抗
が高（なる心配はないし、また多少高くなっても高抵抗
部分の抵抗（Ｇ ｒ ％ Ｔ ｒ ）レベルより十分小
さければ良い。でも実際は上記の横方向拡散により問題
ない。When 1.8 μAs is assumed for 50 minutes, it diffuses in the lateral direction by 1 μ. Therefore, even if a structure like the present invention is used, there is no need to worry about the contact resistance becoming high (and even if it becomes a little high, it is fine as long as it is sufficiently smaller than the resistance (G r % T r ) level of the high resistance part. However, in reality, the above-mentioned No problem due to lateral diffusion.
またこの構造を実現する方法はレジストパターン８を変
更すれば可能であることがわかる。It can also be seen that this structure can be realized by changing the resist pattern 8.
以上本発明の構造を実現できた。As described above, the structure of the present invention has been realized.
本発明の構造をとることにより、高抵抗部分の寸法の確
保と微細化を可能とした。これにより例えばスタティッ
クＳ ＲＡＭのセル面積の縮小化と高集積化およびこれ
らによるコストダウンが可能となった。By adopting the structure of the present invention, it is possible to ensure the dimensions of the high resistance portion and to make it fine. This has made it possible, for example, to reduce the cell area of static SRAMs, increase their integration, and reduce costs.
第１図（α）〜（ｂ
図および断面図。
第２図（α）〜（ｂ
面図および断面図。
図中に於いて、
１・・・・・・・・・半導体基板
２・・・・・・・・・素子分離絶縁膜
５・・・・・・・・・ゲート絶縁膜
４・・・・・・・・・ゲート電極
５・−・・・・・・・層間絶縁膜
６・・・・・・・・・多結晶シリコンの高抵抗部分７・
・・・・・・・・多結晶シリコンの低抵抗部分８・・・
・・・・・・レジストパターン９・・・・・・・・・接
続開口部
）は従来技術を説明する平
）は本発明を説明する平面Figures 1 (α) to (b) and cross-sectional views. Figures 2 (α) to (b) and cross-sectional views. In the figures, 1... Semiconductor substrate 2... ......Element isolation insulating film 5...Gate insulating film 4...Gate electrode 5--...Interlayer insulating film 6 ......High resistance part of polycrystalline silicon 7.
・・・・・・Low resistance part of polycrystalline silicon 8...
. . . Resist pattern 9 . . . Connection opening) is a plane for explaining the prior art) is a plane for explaining the present invention
Claims (1)
多結晶シリコンからなり、該上層の配線層には高濃度不
純物が導入された低抵抗領域と高抵抗領域を有す半導体
装置に於いて、該２層の配線層の接続開口部上に前記上
層配線に於ける高抵抗領域と低抵抗領域の境界があるこ
とを特徴とする半導体装置。(1) In a semiconductor device consisting of at least two layers of wiring, the upper wiring layer is made of polycrystalline silicon, and the upper wiring layer has a low resistance region and a high resistance region into which high concentration impurities are introduced. A semiconductor device characterized in that there is a boundary between a high resistance region and a low resistance region in the upper layer wiring above the connection opening of the two wiring layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27671790A JPH04152561A (en) | 1990-10-16 | 1990-10-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27671790A JPH04152561A (en) | 1990-10-16 | 1990-10-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04152561A true JPH04152561A (en) | 1992-05-26 |
Family
ID=17573353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27671790A Pending JPH04152561A (en) | 1990-10-16 | 1990-10-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04152561A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5905307A (en) * | 1995-05-01 | 1999-05-18 | Oki Electric Industry Co., Ltd. | Semiconductor device incorporating multilayer wiring structure |
-
1990
- 1990-10-16 JP JP27671790A patent/JPH04152561A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5905307A (en) * | 1995-05-01 | 1999-05-18 | Oki Electric Industry Co., Ltd. | Semiconductor device incorporating multilayer wiring structure |
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