JPH04150344A - Cell traffic monitor - Google Patents

Abstract

PURPOSE:To make the monitor small and to reduce power consumption even when a VPI number is large by forming the monitor with a program control circuit and a storage circuit used in common and in time division as to plural VPIs. CONSTITUTION:A signal is inputted to a cell detection circuit 2, and when a valid cell is detected thereby, its VPI is identified by a VPI identification circuit 3. A control discrimination circuit 10 accesses an address of the VPI identified in a storage circuit 12, reads a count described in a reference list and adds 1 thereto. The circuit 10 discriminates whether or not the sum exceeds a threshold level. The circuit 10 sends an inhibit output to a terminal 9 to abort a cell based on the contrast condition when the sum exceeds the threshold level. When not in excess, the circuit 10 executes the transmission processing of the cell and returns the added count to the original address of the circuit 12. The circuit 10 reads a list of the VPI to be decremented for each cell time based on a clock and reads the count of the VPI from the reference list, decrements the count by 1 and returns the result to the reference list.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is used for packet communication. The present invention relates to a technique for monitoring traffic of cells (fixed-length packets are referred to as "cells" in this specification) transferred in a packet communication network.

The present invention is used for policing, in which when a cell is transmitted in excess of the pre-contracted traffic, the cell is discarded as a violation of the contract.

[Conventional technology]

In a packet communication network, if a large number of cells arrive at one relay point at the same time, smooth operation becomes impossible. For this reason, telecommunications carriers operating packet communication networks have contracts with users that require: ■ The users are required to use the verticell information set in the header of each cell.
Virtual Path Identif
(rVPIJ in the specification of ier, Co.), do not transmit more than n cells within m cell time for every m cell time, ■ Telecommunications carriers discard cells transmitted in violation of this rule. Things that are a condition of the contract are done. For example m=
3, n-1, only one cell with the same VPI can be transmitted within 3 cell time, but if a cell with the same VPI is transmitted beyond this time, that cell will be discarded. Monitoring and discarding for this purpose is called policing, and is automatically and continuously executed at the entrance of the packet communication network.

As a conventional device for this purpose, the one shown in FIG. 10 is known. This is known as the leaky packet method, and is published in the journals of the American academic society IEEE (J, S, Tur).
ner, New Directions in Com
communicationsIεBEi Communic
ation Magazine Vow, 24. N
o, 10. pp. 8-15, 1986) has an easy-to-understand explanation.

In FIG. 10, a signal to be monitored is manually input to terminal 1. The cell detection circuit 2 is synchronized with this monitored signal and detects valid cells in the signal. The VPI identification circuit 3 identifies the VPT of the valid cell detected by the cell detection circuit 2. VPI is here a −i.

The identification output is distributed to the up/down counters 4a to 41 provided for each VPI, and each time there is an identification output, that is, each time a VPI is identified, the contents of the corresponding up/down counter are incremented by +1. be done. On the other hand, subtraction signals are input from subtraction control circuits 5a to 51 to the subtraction inputs of the up/down counters 4a to 41, respectively. This is generated every m cell times according to a signal from timer 8. These m and n are values set arbitrarily based on the contract with the user mentioned above, and as shown above, V
For PI=a, if m=3 and n=1, the contents of the up/down counter are decremented by 1 every three cell times. A preset threshold value n=l is held in the threshold value holding circuits 7a to 71. The determination circuits 6a to 61 compare the values of the up/down counters 4a to 41 with the threshold values held in the threshold value holding circuits 7a to 71, respectively, and send prohibition outputs to the terminals 9a to 91 when the threshold values are exceeded. do. This prohibited output causes cells to be discarded on the transmission path.

FIG. 11 is a time chart explaining this conventional device, in which FIG. 11(a) shows the value of the up/down counter 4a, and FIG. 11(b) shows the timing when valid cell C is detected.
(C) of the same figure shows the timing of subtraction. The up/down counter 4a is decremented by 1 every three cell times, and when the value of the up/down counter 4a exceeds 3, the cell is discarded. Here, the up/down counter counts up to zero, and does not take a negative value even if valid cells do not arrive consecutively. The subtraction of the counter corresponds to the long-term average cell detection rate,
The threshold value indicates the short-term cell detection bias.

[Problem to be solved by the invention]

This conventional device is effective in principle and can be operated flexibly, but the up/down counter, threshold value holding circuit, judgment circuit, and subtraction control circuit each have a
This has the disadvantage that the amount of hardware increases when used in a practical packet communication network with a large number of VPIOs. Furthermore, as the speed of the packet communication network increases, each piece of hardware will require a high-speed element.

The present invention improves this, and provides a cell traffic monitoring device that can have a compact hardware configuration even when the number of VPIs increases, and can cope with increased communication speeds. With the goal.

[Means to solve the problem]

The present invention stores the counter values and threshold values for a plurality of VPIs as a correspondence table in one storage circuit, and a judgment control child actor is provided in common for the plurality of VPIs, and is configured to refer to and rewrite this correspondence table. The present invention is characterized in that it is composed of a single program control circuit.

By configuring the storage circuit to include associative memory means that allows the correspondence table to be accessed by VPI, it is possible to cope with increased communication speed.

The counter control means set in the program control circuit is
By configuring the subtraction to be performed only for VPIs for which valid cells have been detected by the cell detection circuit, the frequency of access to the storage circuit can be significantly reduced, making it possible to cope with increased communication speed.

[Effect]

A correspondence table that associates VPIs, counter values, and threshold values is set in one storage circuit without providing individual counter means for each VPI. The counter control means and the judgment circuit are constituted by a single program control circuit, and by referring to this correspondence table, reading out its contents, and rewriting the contents, judgment on cell discard and addition/subtraction processing of the counter are executed. Ru.

Therefore, even if the number of VPIs increases, the number of rows in the correspondence table increases, and there is no need to add additional hardware.

Furthermore, by using an associative memory, access to the storage circuit in which the correspondence table is stored is simplified, and speeding up can be achieved.

〔Example〕

FIG. 1 is a block diagram of an apparatus according to a first embodiment of the present invention. In this device, a signal to be monitored is manually input to terminal 1. The monitored signal is a transmission signal passing through one node of a packet communication network. The signal at the terminal 1 is synchronized with the monitored signal and is input to a cell detection circuit 2 which detects valid cells in the signal. The valid cell detected by this cell detection circuit 2 has its VP
I is identified by the VPI identification circuit 3. In the device of the present invention, the counter value and threshold value for each VPI are stored and set in two storage circuits 12 as a correspondence table for each VPI. Further, this counter value is added each time a valid cell of the corresponding VPI is detected by the cell detection circuit 2.
A counter control means that subtracts a preset number of cells every preset cell time, and a determination means that sends out a prohibition signal when the counter value exceeds the corresponding threshold value refer to this correspondence table. In addition, it is configured to perform rewriting, and is characterized in that it is configured by a program control circuit as one control determination circuit 10 provided in common for a plurality of VPIs.

The prohibition output of the control determination circuit 10 is sent to the terminal 9, and the VPI at that time is sent to the terminal 11. Further, a clock signal is supplied to the control determination circuit 10 from a timer circuit.

In addition to storing counter values and threshold values as a correspondence table corresponding to the VPI, the memory circuit 12 also stores counter values and threshold values corresponding to VPI.
A list of VPIs to be subtracted by 1, a list of VPIs to be subtracted by 1 to m2 cell times, and more generally a list of VPIs to be subtracted by 1 to m hours are stored.

FIG. 2 is a flowchart showing the determination operation of the apparatus of the first embodiment. When a valid cell is detected, its VPI is identified. When this VPI (its value is assumed to be )) and the threshold value (Th(X)). Add 1 to the read counter value. In other words, since a valid cell has been detected for that VPI, the counter value is incremented by one. It is determined whether the added result exceeds a threshold value. If it exceeds the limit, a prohibition output is sent to terminal 9 to discard the cell based on the contract conditions. If the value is not exceeded, transfer processing for that cell is executed and the added counter value is returned to the original address in the storage circuit 12.

FIG. 3 is a flowchart showing the counter control operation of the first embodiment device. That is, in addition to the above judgment operation, the control judgment circuit reads a list of VPIs to be subtracted every m1 cell time based on the clock signal, reads counter values from the correspondence table for the VPIs in the list, and adds 1 to the counter value. Subtract and return the counter value to its correspondence table.

This subtraction operation is a non-negative operation whose limit is zero and the counter value never becomes negative.

As described above, according to the present invention, there is no need to provide hardware for each VPI, and the entire device can be downsized. Since multiple valid cells of the same VPI are not detected at the same time from one non-monitoring signal, if this process is executed within one cell time, it is possible to process incoming cells one after another. can. By the way, 150Mb/
Since the 1 cell time is 2.7 .mu.s in the transmission path of 1.5 s, it can be handled by a chip-type CPU.

FIGS. 4 and 5 are explanatory diagrams of an apparatus according to a second embodiment of the present invention. This second embodiment device has the same device configuration as the first embodiment device explained in FIG. 1, but its memory circuit 1
The feature is that the table stored in 2 is shared by a plurality of tables, and that an associative memory is used in which the stored contents can be read using a key.

In general memory circuits, the physical location where data is stored is used as an address, and when an address is given, the data stored at that address is read out. Associative memory here is not an address as a physical location, but
Part of the data stored there is used as a key for access. Here, if VPI is the key, then the V
The address where the PI is stored is accessed, and various parameters corresponding to that VPI can be read.

FIG. 4 shows an example of a correspondence table when using an associative memory. FIG. 5 is a diagram explaining the logic of an associative memory. Here, the associative memory is a storage circuit that reads data at an address when a portion of stored data matches a value given as a human key. In FIG. 5, it is assumed that data such as "RLO 11 0011" is given as an input key. This corresponds to some digits of data stored at each address in the storage circuit. When this input key is given, for each address, this input key is compared with the corresponding digit of the data stored at that address. In the data y, even if the contents of the input key and its corresponding phase partially match, the whole does not match. In other words, there is a mismatch. I proceeded with this in order and found a match in data X. When all the digits of the human key match, a match output is obtained to the AND circuit. Regarding the address where there is a matching output, the data stored at that address is read out over all digits.

Returning to Figure 4, data as shown in Figure 4 is stored in each address, and when this memory circuit is accessed using the VPI identified by the VPI identification circuit as an input key, the corresponding digit is identified. When the address matches the specified VPI, all data at that address, that is, the n value, counter value, and threshold value, are read out. In this way, there is no need to convert the VPI to an address in the memory circuit, and the contents of the corresponding address in the memory circuit can be read out in a very short time.

In the device of the second embodiment, when a valid cell is detected by the cell detection circuit 2 and the VPI of the valid cell is identified by the vPI identification circuit 3, a storage circuit configured with an associative memory uses the VPI as an input key. 12 and read the data at the address that matches the person's key. Add 1 to the counter value of the data, compare it with the threshold value read out at the same time, and if it exceeds the threshold value, send out a prohibition signal for discarding the data. Subtraction of the counter value is performed by accessing the memory circuit 12 using the cell time m as a key and subtracting one from the corresponding counter value. In the device of the second embodiment, the memory circuit 12 is accessed by giving the VPI or the cell time m as a key, so that the access time of the memory circuit can be shortened.

FIG. 6 is a block diagram of the device according to the third embodiment of the present invention. The device of this third embodiment is roughly the same as the device of the first embodiment, but has a special feature in counter control. That is,
In addition to a counter value and a threshold value, a subtraction factor and a detection time of the previous cell are recorded in the storage circuit 12 corresponding to the VPI. Further, the timer 8 not only sends out a simple clock signal but also sends out an absolute time.

With this configuration, constant subtraction of the counter value is omitted until the VPI is identified and determined. In the first embodiment, the counter value is regularly subtracted at cell intervals based on the contract, but in this third embodiment, this steady subtraction operation is suspended, and instead, the VPI Record the time at which it was identified in the correspondence table. Next, when the VPI is identified, calculate the difference between the previous identified time and the current time, calculate how much the counter value should be subtracted from the elapsed time, and use the result of that calculation. The current counter value is determined by comparing the current counter value with the threshold value.

FIG. 7 is a flowchart illustrating the operation of the apparatus of the third embodiment. That is, when the VPI is identified, the VPIO row of the memory circuit 12 is accessed and its contents are read. The elapsed time since the previous cell detection is calculated, and the elapsed time is multiplied by a subtraction factor to determine the number to be subtracted from the counter value.

This number is subtracted from the counter value to make it the current counter value. However, this operation is a non-negative operation that never becomes negative. Compare the current counter value with the threshold value,
If the threshold is exceeded, the cell is discarded, and if it is within the threshold, the cell is transferred.

Then, the counter value and the current time (CCTR) are stored in the storage circuit 12.

With this configuration, the number of accesses to the memory circuit 12 can be significantly reduced.

That is, in this third embodiment, it is only necessary to access the identified VPI, and there is no need to perform regular access to subtract the counter value of a VPI whose use is unknown. Therefore, it is possible to cope with high communication speeds with sufficient margin.

Here, in this third embodiment, depending on the value of m or n, the counter value, the value to be subtracted from the counter, etc. may not necessarily be an integer.

That is, assuming that the contract is for n cells in m cell time, in the third embodiment, the value to be subtracted from the counter value in m time is the elapsed time xn/m. This may not be an integer. It is inconvenient to treat it as a counter unless it becomes an integer. In such a case, as shown in FIG. 8, by setting the subtraction factor, addition value, and threshold value to values multiplied by m, all calculations can be performed by integer processing.

In other words, the value to be subtracted is the above equation multiplied by m, and the elapsed time x n is always an integer. In order to match this, the value to be added every time a cell is detected is xm, and the threshold value is also multiplied by m to obtain Th x m. This operation allows all contents of the memory circuit to be treated as integers.

Here, instead of simply multiplying m as in the above formulas,
Even if m is multiplied by an integer multiple, all the contents of the memory circuit can be treated as integers.

FIG. 9 is a block diagram of an apparatus according to a fourth embodiment of the present invention. This example is an example in which discarding of a cell is determined by merging with other determination conditions. An expansion input arrives at terminal 13. For example, when there is another contract condition regarding the maximum number of cells over a long period, this extended human power is a signal that instructs cell discard as a result of a determination based on the other condition. The output of the OR circuit 14 which inputs this expansion input and the prohibition output of the control determination circuit 10 becomes a signal at the terminal 9 that sends out the prohibition output. It is also necessary to control rewriting of the counter value using a value including this extended input, and the control judgment circuit 10
The AND circuit 15 outputs the logical product of the prohibition output and the extended human power to the control determination circuit 10 .

With this configuration, it is possible to determine cell discard by integrating other monitoring results.

〔Effect of the invention〕

As explained above, according to the present invention, there is no need to provide hardware for each VPI, and multiple (many) VPIs
A monitoring device can be configured by a program control circuit and a storage circuit that are used in common and in a time-sharing manner. Therefore, when the number of VPIs is large, the device becomes extremely compact and consumes less power.

Additionally, it has the effect of making it easier to respond to increased communication speeds.

By using associative memory technology for the storage circuit and its access control, access to the storage circuit is simplified and high-speed processing can be more rationally supported.

In addition, without periodically executing counter subtraction processing, by executing subtraction processing for the values to be subtracted from the elapsed time all at once when the corresponding VPI is accessed, the number of accesses to the storage circuit can be reduced. becomes smaller,
This has the effect of being able to respond more rationally to high-speed processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an apparatus according to a first embodiment of the present invention. FIG. 2 is an operation flowchart of the device of the first embodiment. FIG. 3 is a flowchart of counter control of the device of the first embodiment. FIG. 4 is a configuration diagram of a correspondence table provided in a memory circuit in a device according to a second embodiment of the present invention. FIG. 5 is a diagram explaining the logic of associative memory. FIG. 6 is a block diagram of a device according to a third embodiment of the present invention. FIG. 7 is an operation flowchart of the device of the third embodiment. FIG. 8 is an operation flowchart of the device of the third embodiment (when all counter values are processed using integers). FIG. 9 is a block diagram of an apparatus according to a fourth embodiment of the present invention. FIG. 10 is a block diagram of a conventional device. FIG. 11 is a time chart showing changes in the counter value of the conventional device. 1... Terminal for manually inputting the monitored signal, 2... Cell detection circuit, 3... VPI identification circuit, 4... Up/down counter, 2... Subtraction control circuit, 6... Judgment circuit ,
7... Threshold value holding circuit, 8... Timer, 9... Terminal for sending prohibition output, 10... Control judgment circuit (consisting of program control circuit), 11... VPI is output. terminal (multi-bit signal), 12... storage circuit (correspondence table is stored), 13... terminal to which extended input arrives. Patent applicant: Nippon Telegraph and Telephone Corporation Representative Patent attorney: Naotaka Ide

Claims (1)

[Claims] 1. A cell detection circuit that synchronizes with a monitored signal and detects valid cells in the signal, and a virtual path number (Virtual Path Identity) of the valid cell detected by this cell detection circuit.
a VPI identification circuit for identifying a VPI (hereinafter referred to as "VPI"); and a counter means provided for each VPI; Perform addition and VP
counter control means for subtracting a preset number of cells corresponding to a preset cell time for each cell time; threshold holding means for holding a preset threshold; and when the value of the counter exceeds this threshold In the cell traffic monitoring device, the counter value of the counter means and the threshold value held in the threshold value holding means are stored in one storage circuit as a correspondence table for a plurality of VPIs. The cell traffic monitoring device is characterized in that the determination means and the counter control means refer to and rewrite this correspondence table, and are constituted by a program control circuit that is provided in common for a plurality of VPIs. 2. The cell traffic monitoring device according to claim 1, wherein the storage circuit includes associative memory means that allows access to the correspondence table using VPI and some other contents stored in the correspondence table. 3. VPI accessed to the storage circuit
The program control circuit is configured to access only those VPIs in which valid cells have been detected by the cell detection circuit, and the program control circuit is configured to store the access time in the area. When an access is made, the elapsed time is calculated from the difference between the previous access time and the current time, and based on that elapsed time, the number to be subtracted collectively from the counter value is calculated. Claim 1 comprising means for calculating a counter value.
Cell traffic monitoring device described. 4. The cell traffic monitoring device according to claim 3, wherein the number to be subtracted from the counter value, the number to be added to the counter value, and the read threshold value are respectively m or a value multiplied by an integral multiple of m. 5. The cell according to claim 1, further comprising a terminal for receiving a signal instructing cell discard based on other conditions as an extended input, and a logical sum of the signal input to this terminal and an output prohibition signal of the control determination circuit as the prohibition output. Traffic monitoring equipment.