JPH04149788A - Signal processing processor - Google Patents

Abstract

PURPOSE:To rapidly and highly efficiently execute data transfer between a signal processing processor and an external microprocessor by independently including a 1st address specifying means for specifying an address in a multiport storage means for the internal and plural address specifying means for specifying addresses from external in the signal processing processor. CONSTITUTION:A dual port RAM 20 for newly executing an interface, an address pointer 21 for pointing out the address of the RAM 20 from the internal and an address pointer 22 for pointing out the address of the RAM 20 from the external are added to the signal processing processor 1. The RAM 20 has two independent I/O ports corresponding to one memory area. Thereby, the common memory area can be accessed from two independent processors and data can be exchanged. Consequently, the delay of a processing speed and the deterioration of data transfer efficiency can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal processing processor that is a microprocessor for signal processing.

[Conventional technology]

Conventional signal processing microprocessors often receive constant sample data such as audio signals as input, have a built-in ROM, and independently execute individual functions. Therefore, little consideration was given to exchanging data with other microprocessors, and data was exchanged using a built-in one-word register.

However, with the recent speeding up of signal processing processors and advanced functions such as floating point arithmetic, data exchange with other microprocessors such as coordinate transformation calculations in engineering workstations (EWS) and robot position control has become increasingly difficult. The number of application fields is increasing.

In such application fields, it is necessary to exchange data on a block-by-block basis in a multiprocessor configuration, which is difficult to handle with conventional signal processing processors.

Here, the conventional technology will be explained by taking as an example the data exchange in a multiprocessor configuration using the conventional signal processing processors as described above.

An example of a conventional signal processing processor is shown in FIG.

Referring to FIG. 2, the conventional signal processing processor 1:
floating point adder 1], working register 12,
Multiplier】3, data R, AM14, data RAM1
A pointer 15 pointing to 4, an instruction decoder] 6, and an instruction R
OM 17, a program counter 18 pointing to an instruction execution address, a stack register 19, an internal bus 23,
It consisted of an interface register 24 and a control circuit 25 including a flag for controlling the interface register 24.

Further, in order to explain the operation of the conventional example, FIG. 2 shows an external microprocessor 2, an external memory 3, an address bus 4, and a data bus 5 that constitute a multiprocessor system. There is.

All of the above-mentioned components are well known in the art of configuring microprocessors and the like, so explanations of those that are not directly related to the present invention will be omitted to avoid redundancy.

Next, the operation of the conventional signal processing processor will be explained.

First, the case of outputting data will be explained.

First, data to be outputted by the program stored in the instruction ROM 17 is written into the interface register 24 via the internal bus 23. When data is written to the interface register 24, a flag in the control circuit 25 allows the external microprocessor 2 to confirm that the data exists and read the data.

Microprocessor 2 or interface register 2
When the data from No. 4 is read, the flag in the control circuit 25 is reset to confirm that data No. 5 has been received.

Next, we will not explain the case of inputting data.In this case, as in the case of data output, data is input via the interface and register 24.The external processor 2 interfaces the data and inputs the data via the register
When writing to , the flag in the control circuit 25 is set to cell 1~,
It is checked whether the data has been prepared. When inputting data continuously, check the flag to check whether the external microprocessor 2 has interfaced and written the data to the register 24. there were.

1. Problems to be Solved by the Invention] The conventional signal processing processor described above performs confirmation using flags in order to arbitrate between internal operation timing and external access. When processing data all at once, there is a drawback that the data transfer efficiency becomes extremely low.

For example, if you want to output a large amount of data continuously, the external microprocessor must acknowledge the reception of the data one by one before outputting it, so no matter how fast the signal processing processor internally processes it, the entire system The disadvantage was that the processing speed of the system depended on the processing speed of the external microprocessor.

Also, in the case of data input, there is no problem when processing - pieces of data at a time, but when you want to process multiple pieces of data at once, as in the case of output, the external processor 2 It has the disadvantage of being dependent on processing speed.

Furthermore, even if you try to use the internal bus as is for data input/output, the internal bus is generally controlled by pipeline processing inside the signal processing processor, so control that makes access to the internal bus wait is not possible. , which had the disadvantage of being extremely complex.

[Means to solve the problem]

The signal processing processor of the present invention provides a multi-port memory including a plurality of data input/output ports that independently input and output data from an internal data bus and from at least one external data bus to a set of storage elements. means, first addressing means for specifying addresses of the storage elements for data on the internal data bus, and at least second addressing means for specifying addresses of the storage elements corresponding to the external data buses, respectively. It is something that you have.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

Referring to FIG. 1, the signal processing processor 1 of the present invention includes a dual port RAM 20 for newly executing an interface, and a dual port RAM in place of the conventional interface register 24 and control circuit 25.
an address pointer 21 that points to the address of 20 from within;
An address pointer 22 that points to the address of the dual port RAM 20 from the outside is added.

Here, the dual port RAM 20 is a RAM having two independent data ports for one memory area. Therefore, a feature is that two independent processors can access a common memory area and exchange data via separate buses. Additionally, peripheral circuitry is provided for controlling the priorities of these two sets of data input/output ports, such as well-known semaphore logic.

In addition, the same floating point adder 11, working register 12, multiplier 13, and data RAM 1 as in the conventional example are included.
4, a pointer 15 pointing to a data RAM 14, an instruction decoder 16, an instruction ROM 17, a program counter 18 pointing to an instruction execution address, one stack register, and an internal bus 23.

Furthermore, in order to explain the operation of this embodiment as in the conventional example, FIG. The output is shown.

All of the above-mentioned components are well known in the art of configuring microprocessors and the like, so explanations of those that are not directly related to the present invention will be omitted to avoid redundancy.

Next, the operation of this embodiment will be explained.

First, a case in which external data is read continuously will be explained.

External data is written into the dual port RAM 20 by an external microprocessor 2 by specifying a read address via an address bus 4 with an address pointer 22. Since writing to the dual port RAM 20 can be executed asynchronously regardless of internal processing, there is no need to confirm that the data has been read inside the signal processor 1, and up to a certain amount can be written continuously.

In addition, by writing information such as the amount of data to a certain address of the dual port RAM 20, this is used as a semaphore logic circuit to confirm that the data is complete inside the signal processing processor 1, and then performs the next data processing. You can start.

Next, a case will be described in which internal data is continuously output to the external microprocessor 2.

In this case, the data stored in the data RAM 14 etc. is transferred via the internal data bus 23 to the dual port RAM 20 whose write address is specified by the address pointer 21.
write to. At this time as well, since access is possible regardless of the state of the external bus 5, etc., continuous high-speed writing is possible.

Also, in the same way as writing from the outside, it is possible to notify the external microprocessor 2 that the data is complete via the semaphore logic circuit that is part of the dual port RAM 20.

2 Detailed Description of the Present Invention From 1 to 2, the present invention is not limited to the first embodiment and can be modified in various ways.

For example, dual-board T-
Of course, instead of using RAM, it is also possible to use RAM having three or more bauds, as long as it does not depart from the spirit of the present invention.

[Effect of the invention 1 1゛↓1-As explained, according to the present invention, the signal processing program 17...! 2, which independently has a multi-port storage means, a first attos specification means for internally specifying the address of the storage means for the multiport 1, and a plurality of attos specifying means for specifying from the outside. There is no need to consider the relationship between internal data processing timing and external access, and data transfer between the signal processing processor and the external microprocessor can be performed at high speed and with high efficiency.

Another advantage is that an interface with an external microprocessor can be realized with a simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional signal processing processor. 1... Signal processing processor, 2... External microprocessor, 3... External memory, 4... Atsys bus,
5. Data bus, ]1. Floating point adder, 12.
- Working register, 13... Multiplier, 14...
Data RAM, 15 Pointer, 16 Instruction decoder, 17 Instruction ROM, 18 Program counter, 19 Stack register, 20 Dual board
-RAM, 21.22...address pointer, 23.
・Internal bus, 24...Interface register, 2
5...Control circuit.

Claims (1)

[Scope of Claims] 1. A multi-port memory comprising a plurality of data input/output ports that independently perform data input/output from an internal data bus and at least one external data bus to a set of storage elements. means, first addressing means for specifying addresses of the storage elements for data on the internal data bus, and at least second addressing means for specifying addresses of the storage elements corresponding to the external data buses, respectively. A signal processing processor comprising: 2. The multi-port storage means has an internal data bus and a
2. The signal processing processor according to claim 1, wherein the signal processing processor is a dual port RAM having two input/output ports for two external data buses.