JPH04146671A - Photodetective element incorporating circuit - Google Patents

Abstract

PURPOSE:To enhance a photodiode in response speed by a method wherein N-type high resistivity epitaxial layers are formed on the surface of a low resistivity semiconductor substrate, a photodetective element is composed of a P-type diffusion layer formed on one of the N-type layers and the N-type diffusion layer of an underlying layer, and a signal processing circuit is formed on the N-type well diffusion layer provided on the other N-type layer. CONSTITUTION:An N-type high resistivity epitaxial layer 16 is formed on the surface of an N<+>-type semiconductor substrate 15, and a P-type diffusion layer 3 is formed thereon on the right. Then, an N<+>-type buried diffusion layer 4 is formed on an NPN transistor forming predetermined region of the surface of the P-type diffusion layer 3, and an N-type high resistivity epitaxial layer 2 is formed on all the surface. The total thickness of the N-type high resistivity epitaxial layers 2 and 16 is so set as to enable the distance between the base of an anode diffusion layer 7 of the surface of a photodiode and the surface of the N<+>-semiconductor substrate 15 to be equal to a depletion layer expanded by a reverse bias. To make the N-type high resistivity epitaxial layer 2 adequate in impurity concentration as an NPN transistor, an N-type well diffusion layer 6 is formed on the N<+>-type buried diffusion layer 4, and a P-type isolation diffusion layer 5 is formed on the peripheral part of the P-type diffusion layer 3.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an improvement in a structure for increasing the response speed of a light receiving element incorporating a signal processing circuit.

(Prior Art) Photodetectors with built-in circuits are widely used in optical sensors, photocouplers, etc., and various structures have been developed to increase the response speed of the photodetector without degrading the characteristics of the signal processing circuit. Proposed.

Figure 8 is a schematic cross-sectional view of one example,
This was disclosed in Japanese Patent Application Laid-open No. 122164/1983 filed by Pioneer Video Co., Ltd. on May 11th. A photodiode A is formed on the left side of the surface of the N-type semiconductor substrate 1 as a light receiving element, and a photodiode A is formed on the right side as a signal processing circuit.
A PN transistor B is formed. The photodiode A includes an N-type high resistivity epitaxial layer 2 formed on the surface of an N-type semiconductor substrate 1 and a P layer formed on the surface.
It consists of a type anode diffusion layer 7, an N type well diffusion layer 6 surrounding it, a cathode diffusion layer 8 formed on its surface, etc., and from the anode diffusion layer 7 there are anode terminals 1a,
A cathode terminal 14 is taken out from the cathode diffusion layer 8 . NPN) transistor B is an N-type high resistivity epitaxial layer 2 formed on the surface of an N-type semiconductor substrate 1.
A region surrounded by the P-type diffusion layer 3 and the P-type isolation diffusion layer 5 is formed, and an N-type well diffusion layer is formed on the N÷-type buried diffusion layer 4 provided on the surface of the P-type diffusion layer 3. Collector diffusion layer 8-1 formed on the surface of 6. base diffusion layer 7-1,
It is composed of an emitter diffusion layer 82 and the like formed on the surface thereof. From the collector diffusion layer 8-1, the collector terminal 12
, a base terminal 11 is taken out from the base diffusion layer 7-1, and an emitter terminal 10 is taken out from the emitter diffusion layer 8-2. 9 is a surface protective film such as Sing.

Such a device is manufactured through the steps shown in the schematic cross-sectional views of FIGS. 9 to 11 below.

First, as shown in FIG. 9, a P-type diffusion layer 3 is formed on the right side of the surface of an N-type semiconductor substrate 1 in a region where an NPN transistor is planned. This is to electrically isolate the photodiode and the NPN transistor, which will be formed in a later step. Therefore, the area is larger than that required for an NPN transistor.

Next, as shown in FIG. 10, N+ type buried diffusion layers 4.4, .
* is formed, and an N-type high resistivity epitaxial layer 2 is further laminated on the entire surface.

Next, as shown in FIG. 11, in order to set the impurity concentration of the N-type high resistivity epitaxial layer 2 in the planned NPN transistor region to a concentration suitable for the NPN transistor, an N-type well with a near-term impurity concentration is prepared. A diffusion layer 6 is formed on the N+ type buried diffusion layer 4. At the same time, N type well diffusion layers 6, 6 are also formed on the N+ type buried diffusion layer 4 in the area where the cathode electrode of the photodiode is planned.

Next, P-type isolation diffusion layers 5, 5 are formed above the peripheral edge of the P-type diffusion layer 3 to isolate each element.

As shown in FIG. 1, a P-type anode diffusion layer is formed on the surface between the N-type well diffusion layers 6 and 6 in the photodiode planned region. , a Pfi pace diffusion layer 7-1 is simultaneously formed on the surface of the N-type well diffusion layer 6 in the NPN transistor planned region. Next, an N-type cand diffusion layer 8 (NPN) is formed on the surface of the N-type well diffusion layer 6 in the area where the photodiode is planned.
A collector diffusion layer 8-1 is formed on a part of the surface of the N-type well diffusion layer 6 in the transistor planned area, an emitter diffusion layer 8-2 is formed on a part of the surface of the space diffusion layer 7-1, and the surface is covered with a surface protective film. 9 and make holes at desired locations to provide respective terminals, the device shown in FIG. 8 can be obtained.
Efforts have been made to increase the spread of the depletion layer by providing a high specific resistance. On the other hand, the NPN transistor section can obtain desired characteristics by providing an N-type well diffusion layer 6 with a desired impurity concentration.

(Problems to be Solved by the Invention) However, in the photodiode having the above-described structure, a portion that has not become a depletion layer remains in the N-type high resistivity epitaxial layer 2 or the N-type semiconductor substrate 1 below it. Carriers generated in the non-depleted layer diffuse to reach the depleted layer, which prevents faster response speed.

Further, by using the N-type semiconductor substrate 1, the series resistance of the cathode portion is large, and the time constant (CR) becomes large, which impedes an increase in response speed. The goal is to increase the response speed of the photodiode.

(Means for Solving the Problems) In the present invention, for example, a plurality of N-type high resistivity epitaxial layers are laminated on the surface of an N-type low resistivity semiconductor substrate, and the thickness of these layers is equal to that of the light receiving element. The thickness of the depletion layer is made to be equal to the thickness of the depletion layer which is expanded by the reverse bias applied to the surface, and a light-receiving element is formed by the P-type mineral dispersion layer provided on one surface (provided) and the N-type layer below it, and the light-receiving element is formed by the N
A signal processing circuit was formed in the type well diffusion layer.

(Function) Because of the structure described above, the laminated high resistivity layer becomes a depletion layer, so that the impurity concentration in the part of the photodiode that is not depleted becomes high (and carriers generated outside the depletion layer The life time of the cathode can be shortened, the diffusion current component can be reduced, and the response speed can be increased.Also, by using a substrate with low resistivity, the series resistance of the cathode section can be reduced, and from this point on, this speed increase can be achieved. Contribute to

(Example) Figure IFr1 is a schematic cross-sectional view showing the structure of an example of the present invention. A photodiode A is formed as a light receiving element on the left side of the surface of the low resistivity N+ type semiconductor substrate 15, and an NPN transistor B is formed as a signal processing circuit on the right side. The difference from the conventional example shown in the 4×8 diagram is that the substrate has a low resistivity, and a plurality of epitaxial layers are laminated to a desired thickness. In the example shown in FIG. 1, the cathode terminal is taken from the back side.

An example of taking the cathode terminal from the surface is described with respect to FIG. 5 below. ! ! The same parts as in the conventional example shown in FIG. 8 are denoted by the same reference numerals. This device is manufactured through the steps shown in the schematic cross-sectional views of FIGS. 2 to 4.

First, as shown in FIG. 2, an N-type high resistivity epitaxial layer 16 of about 10 Ωa is formed on the surface of a low resistivity N+ type semiconductor substrate 15, and an NPN layer on the right side of the surface is formed.
) In an area slightly larger than the area where the transistor is to be formed,
A P-type diffusion layer 3 is formed to electrically isolate the photodiode and the NPN transistor.

Next, as shown in FIG.
N) An N+ type buried diffusion layer 4 is formed in a region where a transistor is to be formed, and an N type high resistivity epitaxial layer 2 of about 100Ω1 is laminated on the entire surface thereof. When the photodiode is used with a reverse bias of 5V, the spread of the depletion layer on the cathode side is approximately 12 μm, so the total thickness of the N-type high resistivity epitaxial layers 2 and 16 is:
The distance from the bottom of the anode diffusion layer on the surface of the photodiode to the surface of the N+ type semiconductor substrate 15 is set to be 12 μm. The thickness of the N-type high resistivity epitaxial layer 2 is:
The thickness is set to 2 to 4 μm in order to obtain a high-performance NPN transistor.

Next, as shown in FIG. 4, in order to set the impurity concentration of the N-type high resistivity epitaxial layer 2 in the planned NPN transistor region to a value suitable for the NPN transistor, a layer is added on top of the N+-type buried diffusion layer 4. , an N-type well diffusion layer 6 is formed, and a P-type isolation diffusion layer 5 is further formed on the peripheral edge of the P-type diffusion layer 3 for isolation between each element.

Next, as shown in FIG. 1, an anode diffusion layer 7 is provided on the surface of the photodiode A portion.

NPN) On the surface of the N-type well diffusion layer 60 in the transistor B portion, an N+ type collector diffusion layer 8-11 and a P-type pace diffusion layer 7-1 are formed. An emitter diffusion layer 8-2 is formed. These surfaces are covered with a surface protection film 1. Drill holes at desired locations, anode terminal 13I collector terminal 12. Pace terminal 11. An emitter terminal 10 and the like are provided. The cathode terminal is provided on the back surface of the N+ type semiconductor substrate 15, as described above.

I! FIG. 5 shows another embodiment in which N+ type buried diffusion layers 4, 4 are formed in advance at the boundary between N type high resistivity epitaxial layers 16 and 2 in the region of photodiode A, and an N type well diffusion layer is formed on the N+ type buried diffusion layers 4, 4. The layers 6, 6 are formed, and the cathode terminal 14 is taken out from the N+ type cathode diffusion layer 8 on the surface thereof.

FIG. 6 shows yet another embodiment, in which, before forming the N-type high resistivity epitaxial layer 16 of FIG.
A P type diffusion layer 3 is formed in a region of an N+ type semiconductor substrate 15 where an NPN transistor is to be formed, and is made to rise up by heat treatment to separate each element.

Thereby, the parasitic capacitance between the collector of the NPN transistor and the P-type diffusion layer 3 can be reduced.

FIG. 7 shows yet another improved embodiment.

The difference from Figure 1 is that the N-type high resistivity epitaxial layer 1
6, a thin N layer is deposited on the surface of the N+ type semiconductor substrate 15.
A high-resistivity epitaxial layer 17 is laminated, a P-type diffusion layer 3 is formed on the surface of the epitaxial layer 17 in a region where an NPN transistor is to be formed, and is grown up by subsequent heat treatment to separate each element. As a result, the parasitic capacitance between the NPN transistor and the P-type diffusion layer 3 can be reduced, and the parasitic capacitance between the N+-type semiconductor substrate 15, which is the cathode portion of the photodiode, and the P-type diffusion layer 3 can be reduced.

In each of the above embodiments, the photodiode is a low resistivity N+
The NPN transistor is formed in a portion of a plurality of high resistivity epitaxial layers laminated on the laminated semiconductor substrate 15, and the NPN well diffusion layer is formed in the laminated high resistivity epitaxial layer. is formed.

Each of the above embodiments describes means for shortening the lifetime of carriers generated outside the depletion layer of a photodiode and reducing the diffusion current component reaching the depletion layer by using a low resistivity N+ type semiconductor substrate 15. However, similar structures can also be achieved using other means. For example, even if an N- type semiconductor substrate with high resistivity is used as in the conventional example, the concentration of impurities other than the depletion layer of the photodiode may be increased by performing N+ type diffusion from the back surface of the substrate.

It can also be applied when the substrate is P type.

(Effects of the Invention) Since the present invention has the above-described structure, the thickness of the high resistivity epitaxial layer can be optimized with respect to the depletion layer width of the photodiode portion, and a low resistivity N+ type semiconductor substrate can be used. By doing so, the impurity concentration outside the depletion layer can be increased, and the lifetime of carriers generated outside the depletion layer can be shortened.
The diffusion current component reaching the depletion layer can be reduced, and the response speed of the photodiode can be increased. Furthermore, since the series resistance of the cathode portion is reduced, the time constant can be reduced, and the response speed can also be increased thereby.

Note that the NPN transistor can be formed in a well diffusion layer with an optimal impurity concentration.

[Brief explanation of drawings]

FIG. 1 is a schematic sectional view of one embodiment of the present invention, and FIGS.
The figure is a schematic sectional view of each manufacturing process of the embodiment shown in FIG. 1, and FIGS. 5 to 7 are schematic sectional views of other embodiments of the present invention, respectively.
FIG. 8 is a schematic cross-sectional view of a conventional example, and FIGS. 9 to 11 are schematic cross-sectional views of each manufacturing process of the conventional example shown in FIG. A... Photodiode, B... NPN) transistor, 1... N type semiconductor substrate, 2... N type high specific resistance epitaxial layer, 3... P type diffusion layer, 4... N+ type Buried diffusion layer, 5...P-type isolation diffusion layer, 6...N
Type well diffusion layer, 7... Anode diffusion layer, 7-1...
・Base diffusion layer, 8... Cathode diffusion layer, 8-1...
・Collector diffusion layer, 8-2... Emitter diffusion layer, 9・
・Surface protection film, 10... Emitter terminal, 11... Pace filA element, xz... Collector terminal, 13...
Anode terminal, 14...Cathode terminal, 15...N
+ type semiconductor substrate, 16...N type high resistivity epitaxial layer Fig.

Claims (1)

[Claims] 1. Laminating a plurality of first conductivity type high resistivity epitaxial layers on the surface of a first conductivity type low resistivity semiconductor substrate,
These thicknesses are made to be equal to the thickness of the depletion layer that expands due to the reverse bias applied to the light receiving element, and the light receiving element is A light-receiving element with a built-in circuit, in which a signal processing circuit is formed in a well diffusion layer provided on the other side of the surface.