JPH0414373B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a storage control system, and particularly to a control system for a storage device forming a three-layer structure.

[Background of the invention]

Conventionally, storage devices have been divided into main storage, intermediate buffer,
A system is known in which there are three levels of buffer storage, a copy of some data in the main memory is stored in an intermediate buffer, and a copy of some data in the intermediate buffer is further stored in the buffer storage. For example, in "Nikkei Electronics" published on May 31, 1982, Toshio Hiraguri et al. discussed the topic "Large-sized computer M-380/382 with improved performance through three-layer memory system and high-density technology." A similar technique is also disclosed in JP-A-52-35533.

This three-layer storage device is important for improving the performance of high-end models such as large computers, but for lower-end models that do not require that much performance,
In some cases, two levels of buffer storage and main storage are sufficient. However, in the past, no consideration was given to easily realizing the transition from 3-level to 2-level and from a certain 2-level to 3-level, and compatibility between these was impossible.

An example of such a conventional configuration is shown in FIG. In FIG. 2, 100 is a central processing unit, which has a built-in buffer storage (BS) 1. 2 is the intermediate buffer (WS), 3 is the main memory (MS),
WS2 stores a copy of some data from MS3,
A copy of some data from WS2 is sent to the central processing unit 10.
BS1 of 0 is stored. 4 is a WS address array (WAA) that stores the main memory addresses of data in WS2, and the central processing unit 100 also has a similar address array for BS1.

Generally, if desired data exists in BS1, the central processing unit 100 obtains the desired data from the BS1 in the case of fetching, and obtains the desired data from BS1 in the case of storing.
Rewrite the corresponding data in WS2 with store data. If the desired data does not exist in BS1 or in the case of a store, the central processing unit 100 issues a BS access request (fetch request or store request) to the WS control circuit 7 through the line 30,
In the case of a store request, store data is also stored in the store stack data register 10 through line 20.

The WS control circuit 7 is connected to the BS from the central processing unit 100.
When receiving an access request, refer to WAA4,
Check whether the desired data exists in WS2. When it is found that the desired data exists in WS2, in the case of a fetch, the corresponding area of WS2 is accessed through the line 32 based on the reference result of WAA4, and the fetch data from WS2 is stored in the fetch data register 6. Then, it is further transferred to the central processing unit 100 through the data line 21, and in the case of a store, the store data in the register 10 is selected by the selector 9 and stored in the store data register 5, and then transferred to the corresponding area of WS2 indicated by the line 32. Store. If the desired data does not exist in WS2, WS control circuit 7 issues a block transfer request to MS control circuit 8 through line 33.

When the MS control circuit 8 receives the block transfer request from the WS control circuit 7, the MS control circuit 8 transmits the block transfer request through the line 34.
3 and reads the block containing the desired data from MC3. This block data is stored in the WS 2 via the line 22 and sequentially through the selector 9 and the store data register 5 under the control of the WS control circuit 7. When this block transfer is completed, the WS control circuit 7
Desired data is read out again from WS2 and transferred to central processing unit 100, and in the case of store, store data in store stack data register 10 is selected by selector 9 and stored in WS2 through store data register 5.

Furthermore, when transferring blocks from MS3 to WS2,
If there is no empty area in WS2, WS control circuit 7
A block to be evicted by the WS2 is selected by a predetermined algorithm (for example, LRU method), and if that block has been rewritten while the WS exists, the data of that block is sequentially fetched from the WS2 to the fetch data register 6. and at the same time
A block store request is issued to the MS control circuit 8 and stored to the MS 3 via line 21. After that, W.S.
The block containing the desired data is transferred from the MS3 to the empty area 2 via the twisted line 22, the selector 9, and the store data register 5.

In this way, in the configuration shown in FIG. 2, all access requests from the central processing unit 100 are sent to the WS control circuit 7.
The data line also exists only between WS2 and WS2. Also, access to MS3 is limited to block stores and fetches, so
The MS control circuit 8 has only that control function. Therefore, if the WS2 is removed, the entire system becomes inoperable, and it is impossible to make the WS2 detachable.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a storage control method that makes it possible to separate intermediate buffers in a three-layered storage device.

[Summary of the invention]

The present invention enables access to the main storage device as well as the intermediate buffer from an access request source such as a central processing unit or an input/output device that has a built-in buffer storage, and also allows access to the main storage device to be performed not only by block transfer. It is possible to store and fetch in 8-byte, 32-byte, etc. units, so that even if the intermediate buffer is removed, the main memory can be accessed directly from the access request source.

[Embodiments of the invention]

FIG. 1 is a block diagram of one embodiment of the present invention. In FIG. 1, a central processing unit 100 has a built-in buffer storage (BS) 1, and normally,
Intermediate buffer (WS) 2 and main memory (MS)
Together with 3, it forms a 3-tier storage device. That is,
WS2 stores some data of MS3, and BS1
A copy of some of the data from WS2 is stored.
WS2 is under the control of WS control circuit 7, and MS3 is
It is under the control of the MS control circuit 8. WS address array (WAA) 4 stores main memory addresses of data existing in WS2. This address array similar to WAA4 is also used in the central processing unit 100.
It has against BS1.

The central processing unit 100 includes AND circuits 102 and 10
3, an access request can be issued to either the WS control circuit 7 or the MS control circuit 8. Therefore, the MS control circuit 8 can receive access requests from the WS control circuit 7 as well as from the central processing unit 100. Store data from central processing unit 100 is stored in store stack data register 10. The store data in this register 10 is stored in the store data register 5 via the selector 9, and then the WS2 and MS
It can be stored in any of 3. Similarly, fetch data register 6 contains WS2 and
Data fetched from any of the MS3s can be stored via selector 101.

The operation shown in FIG. 1 will be explained below. WS2
When operating by incorporating the central processing unit 10
0 is the AND circuit 10 with the line 111 being logic “1”
2 is turned on, and the AND circuit 103 is turned off. In this case, an access request issued from central processing unit 100 on line 110 is passed through AND circuit 102.
It is given to the WS control circuit 7. The WS control circuit 7 is
When an access request is received from the central processing unit 100, the WAA4 is referred to check whether the desired data exists in the WS2. Then, if the desired data exists in WS2, WS2 is used in the fetch operation.
2, the corresponding data is fetched and transferred to the central processing unit 100 via the line 112, the selector 101, the fetch register 6, and the line 114. In the store operation, the data is fetched from the central processing unit 100 via the line 20 to the store stack data register 10. The data stored in is sent via selector 9 and store register 5.
Store in WS2. If the desired data does not exist in WS2, WS control circuit 7 issues a block transfer request to MS control circuit 8 through line 33.

When the MS control circuit 8 receives a block transfer from the WS control circuit 7, it sequentially reads the data of the corresponding block from the MS3, and transfers the data to the line 113 and the selector 10.
1, the fetch data 6 is sequentially stored in the store data register 5 via the line 114 and the selector 9.
The data in this register 5 is stored in the WS2 under the control of the WS control circuit 7. When this block transfer is completed, the WS control circuit 7 re-reads the desired data from WS2 in the case of fetch and transfers it to the central processing unit 100, and in the case of store, stores the store data in the store stack data register 10 to WS2. do.

In this way, when WS2 is incorporated and operated, it is basically the same as in Fig. 2.

Next, if WS2 does not exist, or if it does exist but is inactive, the central processing unit 10
0 is the AND circuit 10 with the line 111 being logic “0”
3 is turned on, and the AND circuit 102 is turned off. In this case, the access request output from the central processing unit 100 to the line 110 is passed through the AND circuit 103.
The signal is applied to the MS control circuit 8. The MS control circuit 8 is
When receiving an access request from the central processing unit 100, the MS 3 performs normal reading and writing in units of 8 bytes or 32 bytes, for example, in accordance with the access request. That is, in the case of a fetch request, MS control circuit 8 accesses MS3 via line 34 and
The fetch data from line 11 is selected by the selector 101 and stored in the fetch data register 6.
4 to the central processing unit 100. In addition, in the case of a store request, when the store data in the store stack data register 10 is selected by the selector 9 and stored in the store data register 5, the MS3 is accessed via the line 34 and the data in the register 5 is transferred to the MS3. Store.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a main storage device (first storage device), an intermediate buffer (second storage device), and a buffer storage (third storage device) built in the processing device are provided. ), the processing device is provided with a path that allows access to both the intermediate buffer and the main memory, and the main memory control circuit (second control means) is provided with a path that allows access to both the intermediate buffer and the main memory.
In addition to controlling block transfers, by providing a function to control access requests from processing devices, control can be performed whether the intermediate buffer is installed or removed. In other words, it is possible to control the storage device without changing the configuration of the control circuit, regardless of whether the storage device has two tiers of main storage, intermediate buffer, and buffer storage, or two tiers of main storage and buffer storage. . Therefore, the hierarchical structure of the storage device has been changed from 3 levels to 2 levels to 2 levels.
It is possible to freely change from one layer to three layers, making it easy to change the model of the computer system (for example, a relatively low performance/low price model with two layers, a high performance/high price model with three layers, etc.) .

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
The figure is a conventional block diagram. 1...Buffer storage (BS), 2...Intermediate buffer (WS), 3...Main storage (MS), 7
...WS control circuit, 8 ...MS control circuit, 100
... central processing unit, 110 ... access request line,
111...WS presence/absence control line.

Claims (1)

[Scope of Claims] 1. A first storage device, a removable second storage device that stores a copy of some data in the first storage device, and a second storage device that is built in a processing device that is an access request source. and a third storage device that stores a copy of some data of the second or first storage device, each of the second storage device and the first storage device connecting means for connecting both read/write data lines of the second storage device to the processing device; If the access request is installed, the selection means is applied to the second storage device side, and if the access request is not installed, the selection means is applied to the first storage device side; Check whether the desired data exists in the second storage device, and if so, access the second storage device and transfer the read data from the second storage device to the processing device in the fetch request. , a first control means that writes write data from the processing device to the second storage device in a store request, and issues a block transfer request to the first storage device if the data does not exist; The first storage device is accessed in response to an access request or a block transfer request given to the first storage device, and when an access request is made from the processing device, the fetch request is used to transfer data read from the first storage device to the processing device. Transfer to the device,
In a store request, write data from the processing device is written to the first storage device, and in a block transfer request from the first control means, a block containing desired data is read from the first storage device and transferred to the first storage device. 1. A storage control system comprising: second control means for block transfer to a second storage device.