JPH04142774A - Master slice type semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve a semiconductor integrated circuit device in degree of freedom of automatic arrangement and wiring so as to enable an automatic arrangement and wiring process to be carried out in a short time by a method wherein at least a wiring formed of a conductive layer which is not used in an automatic arrangement and wiring process is arranged in a wiring region making an angle with both the direction of the rows of basic cells and a direction vertical to the rows of the basic cells. CONSTITUTION:As wirings 14 formed of a conductive layer which is not used in an automatic arrangement and wiring process are arranged in a wiring region 13 between basic cell rows 11 and 12 making an angle with the direction of the rows 11 and 12 of basic cells, wirings 15a and 15e out of wirings 15a-15e formed on a first wiring layer through an automatic arrangement and wiring process can be connected to each other through the wirings 14. By this setup, the wirings 15a and 15e which are deviated from each other in the direction of the basic cell rows and can not be connected together in a conventional wiring method can be connected together.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a master slice type semiconductor integrated circuit device in which a wiring region is arranged between a plurality of basic cell rows each formed by arranging a large number of basic cells. It is something.

(Prior Art) The master slice type semiconductor integrated circuit device described above is known. In such a semiconductor integrated circuit device, even the transistor elements are manufactured in advance, and wiring to connect these transistors according to the required logic function cells is later formed as multilayer wiring within the wiring area. That's what I do. This wiring is generally performed by automatic placement and wiring technology using CAD. By adopting such a master slice type semiconductor integrated circuit device, it is possible to quickly respond to various user requests, and the TAT (Turn Around Time
) can be shortened.

Recently, logic function cells have tended to become increasingly complex. For example, if a large-scale logic functional cell such as a shift register or a counter is constructed using one basic cell column, long wiring is required, which is not desirable. Therefore, one logic function cell is constructed from two adjacent basic cell columns. For example, when using two layers of wiring in automatic placement and wiring, the first wiring layer mainly forms wiring that extends in a direction parallel to the basic cell rows, and the second wiring layer mainly forms wiring that extends parallel to the basic cell rows. Although wirings extending in orthogonal directions are mainly formed, when trying to configure one large-scale logic function cell using multiple basic cell rows as described above, wires extending in a direction orthogonal to the basic cell rows are formed. Since wiring is definitely required, it is necessary to use the second wiring layer. Therefore, there is a drawback that the use of the second wiring layer is limited in automatic placement and wiring.

In order to eliminate such drawbacks, for example, Japanese Patent Application Laid-Open No. 2-9
Publication No. 6370 discloses that a conductive layer that is not used in automatic placement and wiring is used in the wiring area between the basic cell rows to create a conductive pattern that extends in a direction perpendicular to the basic cell rows in the same manner as the gate input of the basic cells. It is described that they are formed at intervals. If such a conductive pattern is formed, adjacent basic cell rows can be connected using this conductive pattern, so there is no restriction on wiring in the direction perpendicular to the basic cell rows during automatic placement and routing. receive less.

(Problems to be Solved by the Invention) FIG. 5 diagrammatically shows the configuration of the conventional master slice type semiconductor integrated circuit device described above. A wiring region 3 is provided between basic cell rows 1 and 2, and is of a so-called channel type. Wirings 4a to 4e extending in a direction parallel to basic cell rows 1 and 2 are wirings formed of a first-layer conductive layer, and wiring 5 extending in a direction perpendicular to the basic cell rows is a wiring formed in a second-layer conductive layer. These wirings are formed using conductive layers, and these wirings are formed by automatic placement and wiring. Further, the wiring 6 shown by the broken line is a wiring pattern formed of a conductive layer that is not used in automatic placement and wiring, and can be formed of, for example, polycrystalline silicon formed on the wafer surface with an insulating film interposed therebetween. Since such wiring 6 is formed between basic cell rows 1 and 2 in a direction perpendicular to the basic cell row, these wires can be used to arrange the wires so that they are shifted from each other when viewed in the direction perpendicular to the basic cell row. Even if an attempt is made to connect the wires, for example, wires 4a and 4e, it is impossible. As described above, the conventional master slice type semiconductor integrated circuit device has wiring 6 formed using a conductive layer that is not used in automatic placement and wiring, but the efficiency of using these wiring is poor, and therefore automatic placement - Wiring is limited, automatic placement and wiring takes a long time, and the wiring becomes long.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a master slice type semiconductor integrated circuit device in which wiring with high utilization efficiency is formed of a conductive layer that is not used in automatic placement and wiring.

(Means and Effects for Solving the Problems) A master slice type semiconductor integrated circuit device of the present invention arranges a wiring area between a plurality of basic cell rows in which a large number of basic cells are arranged, and within this wiring area. , characterized in that at least one wiring formed using a conductive layer that is not used in automatic placement and wiring is arranged obliquely with respect to both the arrangement direction of the basic cell rows and the direction perpendicular to this arrangement direction. It is.

FIG. 1 is a diagram showing the basic configuration of a master slice type semiconductor integrated circuit device according to the present invention. In the present invention, in the wiring region 13 between the basic cell rows 11 and 12, the wiring 14 made of a conductive layer that is not used in automatic placement and wiring is formed obliquely with respect to the arrangement direction of the basic cell rows. As shown in FIG. 2, among the wirings 15a to 15e formed in the first wiring layer by automatic placement and wiring, the wirings 15a and 15e can be interconnected by the wiring 14.

The wirings 15c and 15d can be connected using the wiring 16 formed in the second wiring layer by automatic placement and wiring, as in the prior art. As described above, according to the present invention, the wirings 15a and 15e, which were previously impossible to connect, can be connected.
It is possible to connect wires that are deviated in the direction perpendicular to the wiring direction of the basic cell rows, as shown in the figure, and there are no restrictions on automatic placement and routing, making automatic placement and routing more efficient. , the design time can be shortened, and the length of the wiring can be shortened.

(Embodiment) FIG. 3 is a plan view showing the configuration of an embodiment of a master slice type semiconductor integrated circuit device according to the present invention, in which a conductive layer used in automatic placement and wiring is omitted. Basic cells 21 in the upper basic cell row facing each other across the wiring area 23
The configuration of the basic cell 22 in the lower basic cell row is the same, so the configuration of the upper basic cell will be explained. In this example, the basic cell 21 has four P-channel MOs.
3FET and four N-channel MO3FETs are formed. That is, an N-type region 24 constituting a source or drain is formed on the surface of a P-type silicon substrate, and a gate electrode 25 made of polycrystalline silicon is formed between these regions. Both ends of each gate electrode 25 are enlarged to form a contact region. Further, a P-type head region 26 constituting a source or drain is formed on the surface of an N-type well formed in a P-type silicon substrate, and a gate electrode 27 made of polycrystalline silicon is formed between these regions. There is. Both ends of these gate electrodes are also enlarged. The four NMOS transistors and the four PMOS transistors are arranged in a direction perpendicular to the direction in which the basic cells 21 and 22 are arranged. In a wiring region 23 formed between successive basic cell rows 21 and 22, a wiring 28 is formed using a conductive layer that is not used in automatic placement and wiring.

In the present invention, this wiring 28 is connected to the basic cell rows 21 and 22.
Rather than being formed extending in a direction perpendicular to the arrangement direction of the basic cell rows, they are formed obliquely to both the arrangement direction of the basic cell rows and the direction orthogonal to this arrangement direction. In this example, three wiring lines 28 are formed at equal intervals between each basic cell 21 and 22.
This number is arbitrary, and the inclination angle can also be arbitrarily determined. Further, these wirings 28 are made of polycrystalline silicon and can be formed at the same time as the gate electrodes 25 and 27.

FIG. 4 shows a state in which wiring has been formed by automatically placing and wiring the gate array described above. In this example, the wiring is formed using two layers of aluminum conductive layers, but to make the drawing clearer, the first layer of aluminum wiring is hatched downward to the left, and the second layer of aluminum wiring is hatched. are shown with downward-sloping hatching. 1st as usual
The aluminum wires in the layer mainly form wires extending in the arrangement direction of the basic cell columns 21 and 22, and the second aluminum wires mainly form wires extending in a direction perpendicular to this arrangement direction. In addition, the area of the MOS transistor and the wiring 2
The contact area between 8 and the first layer aluminum wiring is shown by a black square,
The contact area between the first layer aluminum wiring and the second layer aluminum wiring is shown by an open square. In this example, a set/reset type flip-flop as shown in FIG. 4 is constructed. In this example, the PMQ on the left side of the basic cell 21
S) Wiring 28 where the commonly connected gate of the transistor and the left NMOS transistor is not used for automatic placement and wiring.
The common drains of the PMQS transistors in the basic cell column 21 are connected to the drains of the transistors on the left side of the basic cell column 22 via a wiring 28 that is not used for automatic placement and wiring, and the common drains of the PMQS transistors on the right side of the basic cell column 22 are connected to the drains of the transistors on the right side of the basic cell column 22. Connect to commonly connected gates of NMOS transistors. In this way, the second layer wirings that are shifted from each other in the direction perpendicular to the arrangement direction of the basic cell rows 21 and 22 can be connected via the wirings 28 that are not used for automatic placement and wiring.

The present invention is not limited to the embodiments described above, but can be modified and modified in many ways. For example, in the above-described embodiment, the conductive layer not used for automatic placement and wiring was made of polycrystalline silicon formed on a silicon wafer with an insulating film interposed therebetween, but it may also be made of a high-melting point metal such as tungsten or molybdenum. can. Furthermore, the number and inclination angle of wiring formed between basic cell rows can be arbitrarily determined.

(Effects of the Invention) According to the master slice type semiconductor integrated circuit device of the present invention described above, wiring made of a conductive layer that is not used in automatic placement and wiring is placed in the wiring area between successive basic cell rows. Since the wires are formed at an angle with respect to both the arrangement direction and the direction perpendicular to the arrangement direction, it is possible, for example, to interconnect the second wires by crossing the first wires. - The degree of freedom in wiring is increased, automatic placement and wiring can be performed in a short time, and user requests can be quickly responded to.

[Brief explanation of the drawing]

1 and 2 are diagrams showing the basic configuration of a master slice type semiconductor integrated circuit device according to the present invention, FIG. 3 is a plan view showing the configuration of one embodiment thereof, and FIG. FIG. 5 is a plan view showing a state in which a flip-flop is constructed by automatically placing and wiring the semiconductor integrated circuit device shown in FIG. be. 11, 12... Basic cell row 13... Wiring area 1
4...Wiring 15a to 15 not used for automatic placement/wiring
e, 16... Wiring 21 used in automatic placement and wiring,
22... Basic cell row 23... Wiring area 24...
・N-type region 25.27...gate electrode 26
...P-type area 28...Wiring not used in automatic placement/routing Figure 1 Figure 2

Claims (1)

[Claims] 1. Place a wiring area between multiple basic cell columns in which a large number of basic cells are arranged, and place at least one wiring formed using a conductive layer that is not used in automatic placement and wiring in this wiring area as a basic cell. 1. A master slice type semiconductor integrated circuit device, characterized in that the device is arranged obliquely with respect to both a column arrangement direction and a direction perpendicular to this arrangement direction.