JPH04137070U - semiconductor storage device - Google Patents

Abstract

(57) [Summary] [Structure] MOS transistor (flip-flop drive transistor) of TFT load SRAM memory cell and TF
Connections between the T's are made via the second conductor layer 3c. Further, the sources and drains of the two TFTs are oriented in the same direction. [Effect] The offsets of the two TFTs become the same regardless of misalignment of the ion implantation mask when forming the source and drain. Furthermore, constraints on TFT layout are relaxed.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

The present invention relates to semiconductor memory devices, particularly to static RAM memory cells. do.

0002

[Conventional technology]

Until recently, static RAM memory cells had four MOS transistors and two It used to consist of two resistive elements, but as the capacity increased, the resistive elements became more resistant. As a result, the current supply capacity decreases, and the holding state may be destroyed due to junction leakage current or radiation. started to be raised as an issue. As a countermeasure to this problem, thin film transistors can be used instead of resistive elements. A memory cell using a transistor (TFT) has been proposed. The circuit diagram is shown in Figure 4. vinegar. Examples of SRAM memory cells with this TFT load are shown in FIGS. 5 to 7.

0003 Figure 5 shows MOS transistors M1 and M2 formed on a silicon substrate and their related components. 6 is a pattern layout diagram of the continuous portion, and FIG. 6 is formed on the one shown in FIG. 5. This is a pattern layout diagram of TFTs T1 and T2 and their related parts. The cows overlap. Figure 7 shows a semiconductor chip cut along the line corresponding to the X-X line in Figures 5 and 6. FIG. In Fig. 2, 101a, 101b, 101c are silicon substrates. In the active region formed in 111, the drain, channel, A sauce is formed. 102a and 102b are the first layer of silicon or silicon. The conductor layer (first conductor layer) made of a conductive alloy is used to connect the gates of the first and second MOS transistors, respectively. becomes the default electrode. Here, the MOS transistors 101a and 102a are connected to the first The MOS transistor M1, 101b, 102b is the second MOS transistor. MOS transistor M2 is assumed to be MOS transistor M2. Also, the first and second MOS transistors are N-chip. It is a channel type. 105a to 105c are active regions and gates of MOS transistors This is the bonding area of the electrodes. 103 gives ground potential to the source of the MOS transistor A second silicon or silicon alloy conductor layer (second conductor layer) for A contact 104 connects to the active region. In addition, there is a third , fourth MOS transistors M3 and M4 are formed, but this is an important part for the present invention. Since it is not a minute, it is omitted. 106a and 106b in FIG. 6 are TFT gates, respectively. This is the third silicon or silicon alloy conductor layer (third conductor layer), which is the third layer of silicon or silicon alloy. They are connected to 102a and 102b by contacts 108a and 108b, respectively. 107a and 107b are connected to the drain, channel, source and source of TFT This is the fourth silicon layer (fourth conductor layer) that serves as the wiring for the high-potential power supply. 106a and 106b by rain side contacts 109a and 109b, respectively. Connected. The first TFT T1, 1 of the TFTs composed of 106a and 107a The TFT formed by TFTs 06b and 107b is referred to as a second TFT T2. 1st and 2nd TF T T1 and T2 are of P channel type.

0004 TFTs used in memory cells have an offset region on the drain side. It is known that leakage current during off-time can be reduced. 110a and 110b in FIG. is used when performing ion implantation to form the source and drain regions of TFTs. It is a mask pattern, and has an optical pattern of dimensions Z1 and Z2 on the drain side of the first and second TFTs. A offset is formed. For static type RAM of 1M to 4M bits, Z1, Z 2 are both 0.6 μm.

[0005]

[Problem that the idea aims to solve]

In this conventional semiconductor memory device, the arrangement of the drain and source of the first and second TFTs is The direction is reversed. For this reason, mask patterns 110a and 110b are formed. Depending on the direction of misalignment, there will be a difference between Z1 and Z2, and the off-current will be unbalanced. There is a risk that the operation may become unstable. For example, a mask pattern can be added to a drawing. On the other hand, if it shifts upward by 0.1 μm, Z1=0.6+0.1=0.7(μ m), Z2 = 0.6 - 0.1 = 0.5 (μm), and the total offset is 0.2 μm. An imbalance occurs.

[0006] In addition, the third conductor layer and fourth conductor layer forming the TFT are directly connected to the gate electrode of the first conductor layer. Because they are connected to each other, there are strict layout constraints and TFT channel length. will be subject to restrictions.

[0007]

[Means to solve the problem]

The present invention consists of silicon or silicon alloys with different layers on a silicon substrate. a drain having one to a fourth conductor layer and formed on the surface of the silicon substrate; a conductor region, a source region, and a gate electrode made of the first conductor layer as the lowermost layer. first and second MOS transistors of a first conductivity type and the third conductor layer as gates; , a second conductor layer in which a drain region, a channel region, and a source region are formed in the fourth conductor layer. the first MOS transistor, the first MOS transistor, and the first TFT; The drain region of each TFT and the gate electrode of the second MOS transistor, The gate electrodes of the second TFT are all connected at the first node, and the second MOS transistor is connected to the gate electrode of the second TFT. a drain region of each of the second TFTs and the first MOS transistor; The gate electrode of the star and the gate electrode of the first TFT are all connected at a second node, The source regions of the first and second MOS transistors are used as a reference power source, and the first and second MOS transistors are connected to the source regions of the first and second MOS transistors. A flip-flop in which the source region of the second TFT is connected to the first power supply is used as a memory cell. In the semiconductor memory device including the drain regions of the first and second TFTs and The source regions are oriented in the same direction, and the first and second nodes are connected to the silicon substrate, the front A wiring portion formed by a second conductor layer is provided between the first conductor layer and the third and fourth conductor layers. It is said that it has a structure that allows

[0008]

【Example】

Next, the present invention will be explained with reference to the drawings.

[0009] FIG. 1 shows a first embodiment of a semiconductor memory device according to the present invention. 2 is a pattern layout diagram of MOS transistors formed in the MOS transistor and related parts, Figure 2 shows the pattern of the TFT formed on the one shown in Figure 1 and its related parts. The origin A overlaps with the origin A. Figure 3 shows the section corresponding to the X-X line in Figures 1 and 2. FIG. 2 is a cross-sectional view of a cut semiconductor chip. 1a, 1b, 1c are formed on a silicon substrate. The drain region, channel region, and source region of the MOS transistor are space area is formed. 2a and 2b are the silicon or silicon alloy conductors of the first layer. The body layer becomes the gate electrode of the MOS transistor. Here, MO by 1a and 2a The S transistor is a MOS transistor formed by the first MOS transistors M1, 1b, and 2b. The transistor is assumed to be a second MOS transistor M2. Also, the first and second MOS transistors The transistors M1 and M2 are of N-channel type. 5a to 5c are active regions and gate electrodes This is the junction area. 3a is for applying ground potential to the source of the MOS transistor. This is the wiring of the second conductor layer (second conductor layer) made of silicon or silicon alloy. , are connected to the active region by contacts 4a. 3b and 3c are the second The wiring is a conductor layer, and is connected to 2a and 2b by contacts 4b and 4c, respectively. Continued.

0010 6a and 6b are third conductor layers made of silicon or silicon alloy (third conductor layer). ), and becomes the gate electrode of the TFT, and 6a becomes 2b due to contacts 8a and 8b. , 6b is connected to 3b. 7 in FIG. 2 is the fourth silicon layer according to the present invention ( 4th conductor layer) and has 7a and 7b which become the drain region and channel region of the TFT. do. The other part of 7 is the source region of the TFT and the wiring for the high potential power supply. . TFT drains 7a and 7b are connected to 3c and 3c by contacts 9a and 9b, respectively. 6b. 10a and 10b are TFT sources and drains formed by ion implantation. This is a mask pattern to provide an offset on the drain side when forming the drain region. Ru. 6a, 7b is the first TFT T1, 6b, 7a is the TFT It is assumed that the second TFT is T2. Also, the first and second TFTs T1 and T2 are P channel It is a type.

[0011] The semiconductor device according to the present invention, the configuration of which has been described above, has drains of the first and second TFTs. Since the source and source are oriented in the same direction, the mask patterns 10a and 10b are visible. Even if misalignment occurs, no imbalance will occur in offsets X1 and X2. Conventional example In order to compare with If it is 0.1 μm upward in the drawing, then actually X1=0.6+0.1=0. 7 μm, X2=0.6+0.1=0.7 μm, and there is no difference between the two.

0012 Furthermore, in the present invention, the fourth conductor layer of the TFT and the first conductor layer of the MOS transistor are Since wiring is done using the second conductor layer, the degree of freedom in layout increases, and the TFT channel The length and offset length can be freely set without being restricted by the base material.

[0013] FIG. 8 shows a MOS transistor formed on a silicon substrate in the second embodiment of the present invention. FIG. 9 is a pattern layout diagram of transistors and related parts, and FIG. 9 is shown in FIG. 8. This is a pattern layout diagram of the TFT formed on the object and its related parts, and the origin A overlaps. Figure 10 shows a semiconductor chip cut along the line corresponding to the X-X line in Figures 8 and 9. FIG.

[0014] The parts 201a to 210b in the figure are the parts 1a to 10b in the first embodiment. , so the explanation will be omitted.

[0015] The difference between this embodiment and the first embodiment is that the first conductor layer 203c extends to the bottom of the drawing. The gate electrode 206a of the TFT is connected to 203c through the contact 208a. This is the point. In the first embodiment, the gate 6a of the TFT is a MOS transistor. Although it can be said that there are still positional restrictions because it is directly connected to gate 2b of the This can be avoided in the embodiment.

[0016]

[Effect of the idea]

As explained above, the present invention solves the problem of draining the TFT, which is the load of the SRAM memory cell. By orienting the in and source in the same direction, the offset mask pattern of the TFT can be realized. Even if the turn causes misalignment, an imbalance will occur in the offset amount of the two TFTs. None. Therefore, a semiconductor memory device with stable operation can be obtained. Also, on the TFT substrate Since it has a second conductor layer that connects the MOS transistor, it is easy to design the TFT. The degree of freedom is increased, and the layout is less affected by the underlying MOS transistor. It disappears.

[Brief explanation of drawings]

FIG. 1 is a pattern layout diagram used to explain a first embodiment of the present invention.

FIG. 2 is a pattern layout diagram used to explain the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor chip showing a first embodiment of the present invention.

FIG. 4 is a circuit diagram of an SRAM memory cell.

FIG. 5 is a pattern layout diagram used to explain a conventional example.

FIG. 6 is a pattern layout diagram used to explain a conventional example.

FIG. 7 is a cross-sectional view of a semiconductor chip showing a conventional example.

FIG. 8 is a pattern layout diagram used to explain a second embodiment of the present invention.

FIG. 9 is a pattern layout diagram used to explain a second embodiment of the present invention.

FIG. 10 is a cross-sectional view of a semiconductor chip showing a second embodiment.

[Explanation of symbols]

1a-1c, 101a-101c, 201a-201c
Active regions 2a, 2b, 102a, 102b, 202a, 202b on silicon substrate
First conductor layer (gate electrode of MOS transistor) 3a-3c, 103, 203a-203c Second conductor layer (wiring) 4a-4c, 104, 204a-204c Contact between second conductor layer and lower layer 5a-5c, 105a ~105c, 205a, 205c
Contacts 6a, 6b, 106a, 106b, 206a, 206c between the second conductor layer and the active region
Third conductor layer (TFT gate electrode) 7, 7a, 7b, 107a, 107b, 207 4th
Conductor layers 8a, 8b, 108a, 108b, 208a, 208b
Contacts 9a, 9b, 109a, 109b, 209a, 209b between the third conductor layer and the lower layer
Contacts 10a, 10b, 110a, 110b, 210a, 21 between the fourth conductor layer and the lower layer
0b mask pattern

Claims (2)

[Scope of utility model registration request] 1. A first conductor layer to a fourth conductor layer made of silicon or a silicon alloy having different layers on a silicon substrate, a drain region and a source region formed on a surface portion of the silicon substrate, and a first conductor layer to a fourth conductor layer made of silicon or a silicon alloy in different layers; first and second MOS transistors of a first conductivity type each having a gate electrode made of one conductor layer; It has first and second TFTs of two conductivity types, the first MOS transistor, a drain region of each of the first TFTs, a gate electrode of the second MOS transistor, and a gate of the second TFT. The electrodes are all connected at the first node, and the second MOS transistor, the second T
The drain region of each FT, the gate electrode of the first MOS transistor, and the gate electrode of the first TFT are all connected at a second node, and the source regions of the first and second MOS transistors are connected to a reference power source. , the first and second T
In a semiconductor memory device in which a memory cell includes a flip-flop in which a source region of an FT is connected to a first power supply, the drain region and the source region of the first and second TFTs are oriented in the same direction, and the first and second TFTs are arranged in the same direction. 2. A semiconductor memory device, wherein the node No. 2 is constituted by a wiring portion formed by a second conductor layer provided between the silicon substrate, the first conductor layer, and the third and fourth conductor layers. 2. The drain region of the first (or second) TFT, the gate electrode of the second (or first) TFT, and the gate electrode of the second (or first) MOS transistor are each made of a second conductor. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is bonded to the layer.