JPH04134957A - Image processor - Google Patents

Abstract

PURPOSE:To transfer data suitable for an image process, and to smoothly execute the image processing at the joint of a buffer by taking two different scan system for a read-out and a write-in. CONSTITUTION:This is an image processor storing color image data such as a color facsimile equipment or a scanner printer in a buffer memory and executing the image processing, and an image processor 100 and a buffer memory 104 are equipped. In this case, the two different systems are taken, that is, to the same buffer, the write of the image data is executed by a raster scan system, and the read is executed by a shuttle scan system. And when reading out the image data by the scan shuttle system, a read image data length is changed optionally in the direction of a shuttle scan. Thus, on the same buffer memory, the order of the read and write of the two different image data can be realized, and the image process at the joint of the buffer can be executed smoothly.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image processing device, and particularly relates to an image processing device such as a color facsimile or scanner printer that stores color image data in a buffer memory and performs image processing. .

[Prior Art] Conventionally, in this type of image processing apparatus, as shown in FIG. 8, when image data is transferred, several lines are temporarily stored in a buffer memory 50 and written. Generally, they are read in the same order. This method using a buffer memory is often used when there is a difference in processing speed between the writing side and the reading side, or when an intermediate image processing section requires data for several lines before and after.

Here, the conventional image data reading and writing order will be explained.

When considering the connection between a scanner printer, which is an integrated scanner and printer, and a buffer memory, as shown in Figure 9(a), the scanner uses a reading sensor (not shown), and the printer uses a print head (not shown). ) are arranged in the vertical direction (Y direction in the figure) with respect to the original or printing paper, and in the horizontal direction (X direction in the figure) with respect to the original (print paper).
(direction). This is called the shuttle scan method.

<Shuttle Scan Format> As shown in FIG. 9(a), a scanner printer serially scans an image in units of 128 pixels. That is, the ninth
The scanner sensor or printer head is lined up with 128 pixels in the Y direction in Figure (a), and the sensor (or head)
is scanned in the X direction in the figure. Therefore, the order in which images are transferred starts from the upper left pixel on the document or paper, and the sensors (or heads) are lined up as shown in Figure 9(b). Send 128 pixels in the serial scan direction, then send 128 pixels at a position shifted by one pixel in the serial scan direction. Repeat the same operation until the right edge of the paper.

Raster scan format〉 As shown in Figure 9 (C), the raster scan format scans 128 lines of the same number horizontally from the top of the paper.
This is a method of sending lines sequentially.

Image data handled by ordinary computers and communications uses this format.

FIG. 10 shows the order in which the image data stored in the buffer memory is processed, particularly the processing that requires pixel data around the pixel of interest.

FIG. 10(a) shows an example in which image data from a buffer memory that handles binary data is converted from binary data to multivalued data in subsequent processing. Here, multivalue processing and it, binary data, that is, 1bit
This is a process of restoring t data to n-bit (n is an integer) multivalued image data by weighting the data around the pixel of interest using the redundancy of the image data.

In Figure 10(b), when dealing with buffer memory multilevel data, the data stored in the memory is already multilevel data, so the data read from the buffer memory is immediately read out without performing multilevel conversion processing. Image processing is performed, and then binarization processing is performed.

In the above-mentioned processing, after multi-value processing, various processes such as image processing are performed, and then binarization processing is performed. This binarization process is a process for converting the data into a format that can be printed by a printer, such as an output device such as an inkjet printer! Since printing is performed by selecting two types of printing, either applying ink or not, the image data sent to the printer must also be given as binary data.

Note that the binarization process here refers to a binarization method such as an error diffusion method or a minimum average error method, but since the algorithm thereof is well known, a detailed explanation will be omitted.

Next, an example of conventional multivalue processing will be shown.

FIG. 11(a) is a diagram showing the state of pixels in the vicinity of the pixel of interest 55, where the bit "1" is indicated by a black circle.
” stands, and the white circle indicates bit “0”.
is standing.

Therefore, by combining this pixel with the weight value of the 3×3 window matrix shown in FIG. 11(b), the multivalued data can be restored. In this example, the 11th
1111° (10 indicates decimal) shown in Figure (C) is multi-value restored data.

FIG. 12 shows an example of a 3×5 weighting coefficient window in the case of the shuttle scan method. The weighting coefficients are shown in (a) of the figure, and this process also uses a window to allocate the error during binarization to the vicinity of the pixel of interest according to each weighting coefficient. Note that FIG. 12(b) shows the propagation of errors.

The above two processes include window processing that requires the pixel of interest and its surrounding pixel data, so at the junction of the block buffer memories, the value of the block buffer memory before the pixel currently being processed is required. , or the data in the next block buffer may be required.

Therefore, FIG. 13 shows the window processing at the buffer joint.

Figure 13(a) shows the processing at the junction of buffer memories during multi-value processing using a 3x3 window, and one line of data is required for each of the buffer memories before and after. . FIG. 13(b) shows the state of the joint during binarization processing, and in this processing, m lines of data in the next stage block buffer memory (usually m is 7 lines, although there are some differences depending on the processing method). line) is required.

[Problems to be Solved by the Invention] However, in the conventional example described above, the order in which image data is written to the buffer memory and the order in which it is read out must be the same, and two different image data reading operations are performed with respect to the same buffer memory. The disadvantage is that the writing order cannot be realized.

Also, when reading image data from the buffer memory using the shuttle scan method, the data is interrupted at the joints of the buffer memory, so it is necessary to perform window processing as image processing on the image data stored in the buffer memory. This method has the disadvantage that pixel data around the pixel of interest cannot be extracted, and overall image processing cannot be performed smoothly.

[Means for Solving the Problems] The present invention has been made for the purpose of solving the above-mentioned problems, and includes the following configuration as one means for solving the above-mentioned problems.

That is, a plurality of image data storage means for storing image data by associating one address with one pixel data, a write control means for writing image data in the image data storage means using a Herastar scan method; readout control means for reading image data from the image data storage means on which writing has been performed using the shuttle scan method; , arbitrarily change the read image data length in the shuttle scan direction.

[Operation] With the above configuration, two different image data reading and writing orders are realized on the same buffer memory, and image processing at the buffer joint is smoothly executed.

[Embodiment] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of an entire image processing apparatus that is an embodiment of the present invention.

In FIG. 1, an image processing device 100 is connected to a communication line 101.
The communication control unit 102 receives data from the CPU 1.
03 to store it in the buffer memory 104,
The data in the buffer memories 10 and 4 are transferred to the communication control unit 102.
is sent to the communication line 101 via. The CPU 103 is
In addition to being involved in these data transmission and reception, the ROM105
Image processing device 1 according to the control program stored in
Controls the entire 00.

The data stored in the buffer memory 104 is displayed on the image display section 107 as necessary.

FIG. 2 shows the buffer memory 1 of the image processing device of this embodiment.
04 and its peripheral circuitry. FIG.

In FIG. 2, buffers 11 to 13 are memories for temporarily storing image data, and the relationship between addresses and data for these memories is 1 pixel data (lp
ixel: RGB, CMY.

CMYK, etc.) is given one address.

In other words, RG with one bit corresponding to each color of pixel data
If the buffer memory is for B data (binarized data), for example, "110□" is stored at address OO of the memory.
The fact that the value (2 indicates binary) is stored means that only RG exists as color pixel data. The buffer memory for this purpose has a memory device configuration that includes, for example, 3 RAMs with a 1-bit data output.
This is achieved by arranging them in parallel.

Similarly, in the case of a buffer memory for CMYK data, four 1-bit data output RAMs may be arranged in parallel, or one 4-bit data output RAM may be configured.

Furthermore, if the buffer memory is for 8-bit RGB data (multilevel data) for each color, for example, the value "80EEFFH (H indicates hexadecimal)" stored at address 00 means that the R value is 80. The value of G is EE, the value of B is FF,
This means that it exists as color pixel data. This can be achieved by arranging three 8-bit data output RAMs in parallel, similar to the memory arrangement in a normal microprocessor.

As shown in FIG. 2, the buffer memory of the image processing apparatus of this embodiment has three buffers each having a configuration of one pixel data and one address. In this buffer memory, reading using the shuttle scan method is performed as described later.
Since there is a portion where data is read repeatedly, it is configured with three buffers so that data can be written and read from the buffer memory simultaneously in parallel.

In the buffer memory shown in FIG. 2, an address generator 1 generates an address for reading data. and,
Addresses are applied via the path buffers 2, 4.6 of the address bus under the control of the control signals AEO-AE2, and data is output via the path buffers 8-10 of the data bus under the control of the control signals DEO-DE2. be done.

As a result, data can be read by addressing any one of the three buffers. Further, the decoders 3, 5.7 receive the read address from the address generator 1 and the control signal AEO-AE2, and
A chip select signal is output to the buffer to be selected.

FIG. 3 shows the relationship between the memory block configuration of the buffer memory and the read and write access orders.

Each buffer in the buffer memory shown in Figure 3 has a size of 256 bits in the Y direction, which is twice the size of 128 bits (called a block buffer), and a size of 5 Kbits in the X direction (assuming A3 size at 400 dpi). . Buffers of this size are lined up in the order of buffers 1 to 3.

Writing of image data to the buffer memory is repeated in the numerical order shown on the right side of FIG. Writing here is performed in the X direction using a raster scan method, and the address in the Y direction is counted up every time writing in the X direction is completed. When the count-up reaches 128 in the Y direction of the buffer, writing of one block of image data is completed. This ■−■−■−■−■−■→
■Repeat.

On the other hand, the reading of image data from the buffer memory is repeated in the numerical order shown on the left side of FIG. The readout here is performed in the Y direction using the shuttle scan method.
Count up in the X direction. In this memory reading, image data for several lines before and after the block buffer, which is necessary for image processing after reading the image data, is read out redundantly. The arrows attached to the numbers shown on the left side of FIG. 3 also take into account their overlapping parts. This reading is repeated in the order of ■→■→■−■→■−■→■.

What should be noted in the image data read processing in this buffer memory is that, for example, the arrow accompanying the read order number This is the point that it includes. Therefore, when processing with read order number ■ is being performed, buffers 1 and 2 are accessed on the read side, and only buffer 3 can be accessed on the write side. In this way, on the reading side, two of the block buffers divided into six blocks are always occupied. Therefore, in order to perform buffer access control on the write side and the read side to prevent addresses and data from colliding with each other, this buffer memory has three independent address buses and data buses corresponding to the buffers.

Therefore, a memory read operation in the buffer memory shown in FIG. 2 will be explained.

FIG. 4 is a block diagram showing the configuration of the address generating section 1 shown in FIG. 2, in which the lower addresses of the buffer memory are arranged in the memory Y direction, and the upper addresses are arranged in the X direction. By arranging the addresses in this way, the Y-direction counter is counted up first on the memory reading side, thereby realizing the desired shuttle scan.

A preset value to the Y address counter 33 is inputted to the Noratch 31 in FIG. 4 as a count value in the Y direction from the CPU 103. This causes address bus A. -A,
1280α (a is the value of the redundant data readout part in shuttle scan readout, 2
(determined by the window size during digitization processing or multi-value quantization processing) count start and end positions are set. Further, the CPU 103 inputs the count end value in the X direction (here, 5 kbit) to the latch 32 . As a result, each time the Y address counter 33 counts up 128+(2, a ripple out signal is output, and the X address counter 34 outputs a ripple out signal from the address buses A8 to A2.
The address output for ゜ is updated.

Next, a write operation in this buffer memory will be explained.

FIG. 5 is a block diagram showing the configuration of the address generation section 25 shown in FIG. Count up directions sequentially. That is, the lower addresses of the buffer memory are arranged in the memory X direction, and the upper addresses are arranged in the Y direction.

When writing using the raster scan method, do not take into account duplicate data between block buffers, so a ripple out signal is output every time an address equivalent to 5 kbit is output in the X direction on address buses A0 to A12. , 128 lines of addresses in the Y direction are output from the address buses A+x to A2°, thereby completing writing for one block buffer.

As shown in Figure 2, on the write side of this buffer memory, the generated address is transferred to the path buffer 1 of the address bus.
4, 16, and 18, and also inputs data to the buffer memory through path buffers 20 to 22 of the data bus. Here, data is written by addressing any one of the three buffers.

Furthermore, decoders 15, 17, and 19 receive write addresses and control signals AE3 to AE5, and output chip select signals to buffers to be selected.

FIG. 6 is a timing chart showing the timing on the read side of the block buffer. Further, FIG. 7 is a timing chart showing write timing.

In FIG. 6, BVE is a read enable signal for one block buffer data, and VE is a Y direction read enable signal. Image data VD by 4 clocks
OUT is read out in point order. In this timing chart, the image data is RGBX, but this is RGB
This is because it corresponds to CMYK, which is the addition of black K to CMY, which has a complementary color relationship, and may be an RGB order without X.

Hereinafter, with reference to the block diagram of the buffer memory shown in FIG. 2 and the buffer configuration shown in FIG. 3, write and read operations for the block buffer of this buffer memory will be described in detail.

(1) Write operation to buffer l In order to select buffer l, control signal AE3 DE3 is made active (logic "L"). The address from the writing side increases sequentially to A o -A + a, and when the count is up, it increases to the A-th address. This address is applied to buffer 1 via address bus 1, and at the same time write data is applied to buffer l via data bus 1. As a result, data is written to a predetermined address in buffer 1.

The above operation is repeated for 128 lines, and then data is written from the 129th line to the 256th line by the same operation.

(2) Write operation to buffer 2 To select buffer 2, control signal AE4 DE4 is made active (logic "L"). Then, data for 128 lines is written in the same operation as in (1).

By writing in (1) and (2) above, the processing from ■-■→■ among the write access numbers shown on the right side of FIG. 3 is completed.

(3) Writing to buffer 2 and reading from buffer 1 Continuing from (2) above, 128 lines of data are written to buffer 2.

At this time, reading data from the buffer 1 from the reading side is as follows. That is, to select buffer 1, control signals AEO and DEO are activated (logic "L").
), and in synchronization with the pixel clock T, the pixel data (R
,G,B.

X) is read out. In the address generation section 1, as shown in FIG. 4, an address counter operates based on the pixel clock.
After counting 128+α pixels in the Y direction, the upper address is increased by ripple out.

Also, if you set the count value in the X direction in advance,
The upper limit value of the X address counter can be set through the latch 32 of FIG.

In the first read operation, that is, in the first half block of buffer 1, there is no image data of the previous line, so reading starts from the beginning of buffer 1. Also, for the image data of the latter few lines, the current read point is buffer 1.
Since it falls within the range of , it is sufficient to simply count up 128+α.

With the operations up to this point, the processing for write access numbers ■-〇-〇-〇 shown on the right side of Figure 3 has been completed, and the
This means that the process indicated by the read access number (■) shown on the left side of the figure has been completed.

(4) Writing to buffer 3 and buffer 1. Read operation from buffer 2 In order to select buffer 3, control signal AE5 DE5 is made active (logic "L"). Similar to the process in (1) above, 128 lines of image data are written to the buffer 3. At the same time, in order to read image data from buffers 1 and 2, control signals AEO and AEI are activated (logic "L") to select buffers 1 and 2.

On the data bus side, first, the control signal DEO is set to the active state of logic "L", and the last line point of the first half block of buffer 1, that is, the count value in the Y direction, is set to 1.
When set to 27, the address generator 1 counts up along with the pixel clock, and counts up the 128th to 255th lines of the second half block of the buffer 1.

Address generation unit 1 bs l After counting 28 lines, the counter returns to 0 and then counts 0 minutes. At this time, on the data bus side, the control signal is switched to DEI. By doing this, pixel data for several lines in the first half of the buffer 2 is read out. And +0
After reading the pixel data for 10 minutes, the control signal DEO is selected again and reading from the buffer 1 is performed. That is, each time the count in the Y direction is completed, the count in the X direction is increased, and this operation is repeated thereafter.

As a result of the above operations, the processing for the write access numbers up to ■ shown on the right side of FIG. 3 has been completed, and the processing for the read access numbers (■) shown on the left side of FIG. 3 has been completed.

(5) Writing to buffer 3 and reading from buffer 1 and buffer 2 In order to select buffer 3, control signal AE5 DE5 is made active (logic "L"). And (4) above
Following the processing in , 128 lines of image data from 128 to 255 are written. At the same time, buffer 1
and reads image data from buffer 2.

To select buffer l and buffer 2, control signal AE
O, AEI is made active (logic "L"). Here, only the final line of the second half of buffer 1 is read out, and the readout of buffer 2 is immediately started. That is, the initial address count value in the Y direction is set to 255, and the control signal D is
Keep EO active (logic "L"). Immediately after reading the last line of buffer 1 is completed, control signal DEI is made active (logic "L") to select buffer 2. Thus, O~128+ in the Y direction
After counting up for α and reading image data from buffer 2, one pixel is read out from buffer 1 again, counting up in the X direction, and repeating the above operation.

As a result of the above operations, the processing for the write access numbers up to ■ shown on the right side of FIG. 3 has been completed, and the processing for the read access numbers (■) shown on the left side of FIG. 3 has been completed.

Thereafter, operations similar to those described above are repeated to perform writing and reading to and from this buffer memory.

As explained above, according to this embodiment, it is possible to easily implement two different methods: writing image data to the same buffer using the raster scan method and reading it using the shuttle scan method. effective.

In addition, when reading using the shuttle scan method, the block buffer currently being read and part of the image data before and after that block buffer can be read out redundantly, making it easier to perform image processing at buffer joints. This has the effect of making everything run smoothly.

It should be noted that the present invention is not limited to the above-mentioned embodiments,
For example, instead of writing and reading from the buffer memory at the same time, a method may be adopted in which two buffer memories are used and writing and reading are alternately performed.

[Effects of the Invention] As explained above, according to the present invention, by adopting two different scanning methods for reading and writing image data, data transfer convenient for image processing can be performed.
This has the effect that image processing at the joint between buffers can be performed smoothly.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an image processing device that is an embodiment of the present invention, Fig. 2 is a detailed block diagram of a buffer memory of the embodiment and its peripheral circuits, and Fig. 3 is a memory block configuration and readout of the buffer memory. , and the relationship with the write access order; FIG. 4 is a block diagram showing the configuration of the address generation section l; FIG. 5 is a block diagram showing the configuration of the address generation section 25; FIG. 6 is block buffer readout. FIG. 7 is a timing chart showing block buffer write timing. FIG. 8 is a diagram explaining image data transfer in a conventional image processing device. FIG. 9(a) is a diagram showing image data transfer in a conventional image processing device. Figure 9(b) is a diagram showing the arrangement of image data in the shuttle scan method, and Figure 9(C) is a diagram showing the arrangement of image data in the raster scan method. 10(a) is a diagram showing the conversion process procedure between the binary buffer memory and image data, FIG. 10(b) is a diagram showing the conversion process procedure between the multilevel buffer memory and image data, and FIG. 11( Figure 11 (a) is a diagram showing the state of pixels in the vicinity of the pixel of interest, Figure 11 (b) is a diagram showing an example of weight values of a 3 x 3 window matrix, and Figure 11 (c) is a diagram showing restored multi-level data. Figure 12(a) shows the 3×5 case of the shuttle scan method.
Figure 12(b) is a diagram showing an example of the weighting coefficient window of 3.
Figure 13(a) is a diagram showing error propagation in a ×5 weighting coefficient window, Figure 13(a) is a diagram showing processing at a buffer joint during multi-value processing using a 3 × 3 window, Figure 13 ( b) is 2 using a 3x5 weighting factor window.
FIG. 7 is a diagram showing a state of processing at a buffer joint during valorization processing. In the figure, 1.25...address generation section, 11-13...
・Buffer, 34.37...X address counter, 3
3.38...Y address counter, 100...image processing device, 104...buffer memory. Patent applicant Canon Co., Ltd. No. 4 No. 5

Claims (2)

[Claims] (1) a plurality of image data storage means for storing image data by associating one address with one pixel data; and a write control means for writing image data in the image data storage means using a hera star scan method; An image processing apparatus comprising: readout control means for reading image data from the image data storage means written by the write control means using a shuttle scan method. (2) The image processing apparatus according to claim 1, wherein the readout control means is capable of arbitrarily changing the readout image data length in the shuttle scan direction when reading out the image data using the shuttle scan method.