JPH04134927A - Decode processing unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Continuous analog data such as image data and audio data is sampled and converted from analog to digital, and a plurality of continuous analog data are converted into one unit and transmitted or recorded together with an error correction code. Regarding a decoding processing device suitable for decoding a unit data string, the purpose is to perform high-quality decoding processing even when the number of error bits in a unit data string exceeds N bits and is less than N bits. , preprocessing means for sampling and analog-to-digital conversion of continuous analog data, receiving or reading unit data strings transmitted or recorded together with error correction codes, and sequentially transmitting the data strings; , receives the unit data string sent out from the preprocessing means, and sends it out as is when it is determined that there is no error in the unit data string based on the error correction code;
If the error is within M bits, it is sent after correcting the error bit, and if it exceeds M bits and is within N bits, it is sent without correcting the error and with information to that effect attached. an error correction processing means for decomposing the unit data string sent from the error correction processing means into its constituent data and outputting it sequentially; At the same time, as for the data to which the presence of error bit has been added, the interpolated data is calculated based on a predetermined number of data before and after the data, and the difference value between the original data and the interpolated data exceeds a specified value. interpolation in which a certain error bit in the original data is inverted so that the difference value is within a specified value, and the unit data string is returned to the error correction processing means for reprocessing. The apparatus includes a processing means, and a reproduction processing means for reproducing the original analog data based on the digital data passed through the interpolation processing means.

[Industrial application field]

This invention samples continuous analog data such as image data and audio data, converts it from analog to digital, and decodes a unit data string that is transmitted or recorded together with an error correction code, with a plurality of continuous analog data being converted into one unit. The present invention relates to a decoding processing device suitable for decoding.

In data transmission that uses the atmosphere as a route, such as microwave communication and satellite broadcasting, the received C/N ratio may decrease due to the influence of rain.

In order to ensure sufficient data quality even when the reception C/N ratio decreases, error correction of transmission codes is necessary.

For example, the A-mode and B-mode frames (1,35
Correction code (SEC-D
5EC-DED has 1-bit error correction ability and 2-bit error detection ability and is used in normal mode, while DEC-TED has 2-bit error correction ability and 3-bit error detection ability. It has detection ability and is used in enhanced mode.

In general, error control using error correction codes is possible when various symbols are dispersed into code patterns other than code words due to some kind of error, and when the dispersed region is isolated, error correction is possible. Furthermore, if the distributed regions partially overlap, error detection is possible although correction cannot be performed.

FIG. 3(a) is a conceptual diagram of error correction, and FIG. 3(b) is a conceptual diagram of error detection. In these figures, a1 to a3
and a11-a13 are code words, b1-b3 and bll-
b13 is a region dispersed due to errors, and C1 and C11 are regions of the entire sequence of length n.

In other words, in the enhanced mode described above, if the transmission error is 2 bits or less, it can be corrected (error correction), and if it exceeds 2 bits and is 3 bits or less, it is possible to detect the presence of an error (
(error detection), and when an error is detected, data interpolation processing is often performed for the purpose of improving data quality.

[Conventional technology]

FIG. 4 is a block diagram showing the configuration of a conventional decoding processing device. In the figure, a preprocessing unit 1 samples continuous analog data and converts it from analog to digital, sets a plurality of continuous analog data as one unit, and receives as input a unit data string transmitted or recorded together with an error correction code. It is received or read and sequentially sent to the error correction processing section 2.

The error correction processing section 2 receives the unit data string sent from the preprocessing section 1, and when it is determined that there is no error in the unit data string based on the error correction code, it directly sends it to the deinterleaving section 3. When the error is within M bits, the error bit is corrected and then sent to the deinterleaving section 3, and when it exceeds M bits and is within N bits, the error is corrected. This is sent to the de-interleave section 3 with information to that effect added.

The de-interleaving unit 3 decomposes the unit data string sent from the error correction processing unit 2 into its constituent data and sequentially outputs the data.

The interpolation processing unit 4 receives the individual constituent data sent for each unit data string from the de-interleaving unit 3, and interpolates the data to which an error bit has been added based on a predetermined number of data before and after the data. The data is obtained and sent to the audio reproduction processing section 5.

FIG. 5 is a block diagram showing the configuration of the conventional interpolation processing section 4. As shown in FIG. In the figure, data DIN that arrives in time order (data constituting a unit data string) is stored in the register 6, the second register 7, and the third register 8 in order. In other words, the current data dO from the first register 6 is
The previous data d1 is taken out from the second register 7, and the two previous data d2 is taken out from the third register 8. d
O and d2 are input to the interpolation processing circuit 9, and the interpolation processing circuit 9
The output dH is inputted to the A and B terminals of the selector 10 along with dl.

The interpolation processing circuit 9 generates interpolated data dH for the data d1 immediately before the current data, and calculates the correlation between the current data dO and the data d2 immediately before, and uses the correlation result as d.
Let it be H. The selector 10 outputs either the input of the A or B terminal as data DOUT according to the state (1" or 10") of the error detection flag F input to the select terminal S.

F-“0” indicates error correction/error correction for the previous data d1.
This indicates that at least "error detection" was not detected as a result of the detection. In this case, the selector 10 selects the previous data d1.

As a result of error correction and detection, F-“1” is “
This indicates that an error has been detected. In this case, selector 10 selects interpolated data dH.

Therefore, the interpolated data dH of this dl can be output in place of the previous data d1 that was "error-detected", and the data quality at the time of error detection can be improved.

The audio reproduction processing section 5 reproduces the original analog audio data based on the digital data that has passed through the interpolation processing section 4.

However, in such a conventional decoding processing device, while receiving the unit data string sent from the preprocessing section 1, based on the error correction code, the error in the unit data string exceeds M bits and N bits are detected. When the error was determined to be within a bit, information to that effect was attached to all the constituent data and sent to the de-interleaving unit 3 without correcting the error, as shown in FIG. 6, for example. Assume that the unit data string contains four pieces of data each consisting of 14 bits, and M-1, N
When set to -2, the problem is that all data is always interpolated even though at least two of the four data are correct, resulting in distortion and lower data quality. was there.

[Problem to be solved by the invention]

As described above, the conventional decoding processing device receives the unit data string sent from the preprocessing section 1, and detects errors exceeding M bits and N bits in the unit data string based on the error correction code. When the error was within a bit, information to that effect was attached to all the constituent data and sent to the de-interleaving unit 3 without correcting the error, for example, as shown in Fig. 6. To,
Assuming that the unit data string contains four pieces of data each consisting of 14 bits, and if M=1 and N=2, at least two of the four pieces of data are correct. However, there is a problem in that all data is always subjected to interpolation processing, resulting in a warp and a decrease in data quality.

This invention was made in view of the above-mentioned problems, and its purpose is to provide high quality even when the number of error bits in a unit data string exceeds N bits and is less than N bits. An object of the present invention is to provide a decoding processing device that can perform decoding processing.

[Means to solve the problem]

FIG. 1 shows the configuration of a decoding processing device according to the present invention.

Preprocessing means 1 for sampling and analog-to-digital conversion of continuous analog data, receiving or reading a unit data string transmitted or recorded together with an error correction code, and sequentially sending out the data string, with a plurality of continuous analog data as one unit.
1, and receives the unit data string sent from the preprocessing means, and when it is determined that there is no error in the unit data string based on the error correction code, sends it out as is, and it is determined that the error is within M bits. Sometimes, the error bit is corrected and then sent, and the error bit exceeds M bits and N
Error correction processing means 1 that sends the error with information to that effect without correcting it when the error is within a bit.
2, a deinterleaving means 13 for decomposing the unit data string sent from the error correction processing means into its constituent data and sequentially outputting the data; In addition to receiving the configuration data, for data with an error bit added, interpolation data is calculated based on a predetermined number of data before and after the data, and if the difference value between the original data and interpolation data exceeds a specified value, , invert a certain error bit in the original data so that the difference value is within the specified value,
An interpolation processing means 14 returns the unit data string to the error correction processing means for reprocessing, and a reproduction processing means 15 reproduces the original analog data based on the digital data passed through the interpolation processing means. .

[Effect]

According to such a configuration, for data to which an error bit has been added, interpolated data is obtained based on a predetermined number of data before and after the data, and the difference value between the original data and the interpolated data exceeds a specified value. , the original data string is returned to the error correction processing means 12 for reprocessing so that the difference value is within a predetermined value. becomes possible.

〔Example〕

FIG. 2 is a block diagram showing the detailed configuration of the interpolation processing unit 14, which is a main part of the decoding processing device according to the present invention.

In the figure, data DIN arriving in time order (data constituting a unit data string) are sequentially arranged in the first register 16,
It is stored in the second register 17 and the third register 18.

That is, the current data dO from the first register 16 is
The previous data d1 is output from the second register 17, and the third
The two previous data d2 is taken out from the register 18.

dO and d2 are input to the interpolation processing circuit 19, and the output dH of the interpolation processing circuit 19 is input to A of the selector 20, along with dl.
Input to B terminal.

The interpolation processing circuit 19 generates interpolated data dH for data d1 immediately before the current data, and
The correlation between the data d2 and the two previous data d2 is taken, and the correlation result is defined as dH. The selector 20 determines the state of the output of the AND gate 21 (“1” or “2”) input to the select terminal S.
), input any of the ASB terminals to data DO.
Output as UT.

Here, the AND gate 21 outputs the AND of the interpolation processing flag F and the output of the difference value comparator 22. Further, the interpolation processing flag F is controlled as follows by the action of the error correction processing section 12 shown in FIG. That is, the threshold value M in the error correction processing section 12
Assume that the values of %N are M-1 and N-2. In such a setting, for example 63 as shown in FIG.
When processing a bit data string (14-bit data x 4 pieces + 7-bit error correction code), if the number of error bits in the data string is 2 bits, the interpolation processing flag is set for each of the 4 pieces of data. F is set to 1''.In other words, in this case, it is determined that all four pieces of data have errors, even though the number of pieces of error data in the data string is two at most.

On the other hand, the difference value comparator 22 always compares the interpolated data dH and the current data d1, and if the difference between the two is within the specified value of 6% (that is, the correct data is in the register 17). (if stored), the output of the difference value comparator 22 becomes "0". Then, the output of the AND gate 21 becomes "0" due to the output "0" of the difference value comparison 22, the terminal A is selected as the input of the selector 20, and the current data d1 is directly sent to the audio reproduction processing section 15 as the output data DOUT. This will be sent out as follows.

On the other hand, if the difference between the two is not within the specified value of 6% (that is, if incorrect data is stored in the register 17), the output of the difference value comparator 22 will be 1". Then, The output of the AND gate 21 becomes "1" due to the output "1" of the difference value comparison 22, the terminal B is selected as the input of the selector 20, and the interpolated data dH is processed as the output data DOUT instead of the current data d1. At the same time, the differential value comparator 2
The bit adjustment circuit 23 is differentially controlled by the output "1" of 2,
The error bits among the 14 bits that make up the current data d1 are inverted and the data is corrected so that the difference between the current data d1 and the interpolated data dH is within a specified value of 6%, and then this correction is performed. The four pieces of data (one unit of data) including the detected data are returned to the error correction processing section and subjected to error correction/detection processing again. At this time, the number of error bits in one unit of data will have decreased by one bit from the original value due to the above correction process, so error correction is performed instead of just error detection. In addition,
Those skilled in the art will easily understand that when one unit of data is returned to the error correction processing section 12, it is preferable to close the output of the selector 20 by an appropriate gate circuit during that time. will be done.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, even if error correction is impossible because the number of error pins in a unit data string exceeds M bits and is less than N bits, the interpolation processing means High-quality decoding becomes possible due to the bit correction effect.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a decoding processing device according to the present invention, Fig. 2 is a block diagram of an interpolation processing unit according to the present invention, Fig. 3 is a diagram explaining error correction and error detection, and Fig. 4 is a conventional decoding process. FIG. 5 is a block diagram of a conventional interpolation processing section, and FIG. 6 is an explanatory diagram showing an interleave matrix. 11... Preprocessing unit 12... Error correction processing unit 13... De-interleaving unit 14... Interpolation processing unit 15... Audio reproduction processing unit 21... AND gate 22... Difference value Comparator 23...Bit adjustment circuit 3-way gear for the present invention B processing
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Claims (1)

[Claims] Sampling and analog-to-digital conversion of continuous analog data, receiving or reading a unit data string transmitted or recorded with an error correction code with a plurality of data as one unit, and sequentially transmitting this data. Pretreatment means (
11), and receives the unit data string sent from the preprocessing means, and when it is determined that there is no error in the unit data string based on the error correction code, sends it out as is, and if the error is determined to be within M bits. Error correction processing means (12) for correcting the error bits and transmitting the error bits, and for transmitting the error bits with information to that effect without correcting the errors when the error bits exceed M bits and are within N bits; )
and deinterleaving means (13) for decomposing the unit data string sent from the error correction processing means into its constituent data and sequentially outputting the data, and deinterleaving means (13) for decomposing the unit data string sent from the error correction processing means into its constituent data and sequentially outputting the unit data string. In addition to receiving the configuration data, for data with error bits added, interpolation data is calculated based on a predetermined number of data before and after the data, and for data where the difference value between the original data and interpolation data exceeds a specified value. is an interpolation processing means that inverts a certain error bit of the original data so that the difference value is within a specified value, and returns the unit data string to the error correction processing means for reprocessing. (14); and reproduction processing means (15) for reproducing original analog data based on the digital data that has passed through the interpolation processing means.