JPH04134691A - Memory device - Google Patents

Abstract

PURPOSE:To arrange a sense amplifier at the pitch of two bit lines, and to make a layout easy by providing the sense amplifiers to one side and the other side of each memory block at every bit line alternately. CONSTITUTION:Taking notice to the memory block equipped with a word line WL, bit lines BL1 - BL5 are provided in order in an X direction making a Y direction as a longitudinal direction, and memory cells MC1 - MC5 are formed respectively at the intersected points with the world line WL. Sense amplifiers SA1 - SA5 for a differential amplifying are equipped to the bit lines BL1 - BL5 respectively, and the sense amplifiers SA1, SA3 and SA5 are arranged in the right side of the memory block and the sense amplifiers SA3 and SA4 are arranged at the left side of the memory block. That is, the sense amplifiers SA1 - SA5 are arranged at the one side and the other side of the cell block at every bit line alternately, and the sense amplifier for the next bit line is not adjacent in the X direction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a DRAM type memory device, and particularly to an oven bit line type memory device in which a pair of bit lines are assigned to a sense amplifier.

[Summary of the invention]

The present invention provides a memory device using a so-called oven bit line system, in which sense amplifiers are arranged alternately at the ends of cell blocks for each bit line, or arranged so as to be shifted in the longitudinal direction of the bit lines. This simplifies the layout of the sense amplifier and reduces interference noise.

[Conventional technology]

There are two known DRAM bit line systems: the oven bit line system and the folded bit line system (for example, [Nikkei Electronics J NCL No. 399,
202 pages (published by Nikkei McGraw-Hill), or see Japanese Patent Publication No. 55-39073 6).

The folded bit line method has a structure in which paired bit lines extend adjacent to each other in the same direction, and because it is resistant to noise, it has become mainstream in DRAMs after 256 bits.

However, folded bit lines are disadvantageous in terms of degree of integration, and are a hindrance to increasing capacity. Therefore, it is necessary to review the oven bit line method again.

FIG. 3 is a schematic circuit diagram of a DRAM having a conventional oven bit line structure. In the figure, there are five bit line pairs BL, ■L, ~BLi, BL that are parallel to each other.

are shown, and each sense amplifier SA to SA is connected to each bit line pair for each bit line pair.
, are connected. Sense amplifiers SA to S A s are located between a pair of bit lines. The word line extends in a direction perpendicular to the bit line, and memory cells MC, .about.MC, are arranged at the intersections of the word line WL and each bit line. By adopting such an oven bit line structure, memory cells can be arranged at each intersection of a bit line and a word line, and high integration can be achieved.

[Problem to be solved by the invention]

However, in the oven bit line structure, the following problem occurs.

First of all, the pitch of the sense amplifiers SA, ~SA, must be kept within the size of one side of one memory cell due to the layout. Size is sacrificed, speed and sensitivity are degraded.

Second, interference noise between bit lines occurs. Here, the interference noise will be explained with reference to FIG. First, in the device of FIG. 3, memory cells MC, -MC,
It is assumed that each data "1, 1, 0.11" is stored in . Next, let us consider reading data from the memory cell MC2. In FIG. 4, at time t1, the word line W
When L is selected, the levels of bit lines BL and BL4 rise in accordance with the data, and the levels of bit lines BL and BL4 rise, respectively, in accordance with the data.

The level of will decrease depending on the data. But bit line B
L is a bit line BL adjacent to the bit line BL,
Due to the closed coupling capacitance of , BL, the level becomes higher than the original level by α. Next, when the sense amplifier starts operating at time t2, the sensitivity of the sense amplifier on bit line BL is poor by the amount of α, whereas on the adjacent bit lines BL, BL, the sense amplifier functions effectively.

Therefore, at the initial stage of the sense amplifier operation, the bit line BL receives interference to the extent that the operation of the sense amplifier SAI is delayed, and noise β in the figure is superimposed.

Furthermore, if we focus on the dummy side, we can see that similar interference occurs on the dummy side as well, when the bit line r, adjacent to the bit line ■,...
For example, noise corresponding to γ in the figure is superimposed on the dummy bit line 111fi, which further adversely affects the operation of the sense amplifier.

SUMMARY OF THE INVENTION In view of the above-mentioned technical problems, it is an object of the present invention to provide a memory device that facilitates the layout of sense amplifiers and reduces interference noise.

[Means to solve the problem]

In order to achieve the above object, the memory device of the first invention of the present application includes a pair of differentially amplified pitch signals in a sense amplifier.
are distributed and arranged in the longitudinal direction of the bit lines, and the sense amplifiers are arranged alternately for each bit line at one end and the other end of each memory block.

Further, the memory device of the second invention of the present application has a configuration in which a pair of bit lines to be differentially amplified by a sense amplifier are distributed and arranged in the longitudinal direction of the bit line, and the sense amplifier is arranged for each bit. The bit lines are characterized in that each line is shifted by a predetermined interval in the longitudinal direction of the bit lines. Here, as an example of the above-mentioned predetermined interval, the interval may be such that the bit line is shifted in the longitudinal direction of the bit line by, for example, half the length of one bit line.

[Effect]

In the memory device of the first invention of the present application, the sense amplifiers are arranged alternately for each bit line at one end and the other end of each memory block, so the sense amplifiers can be arranged at a pitch of two bit lines. This makes the layout easier. Further, when focusing on the bit lines on the dummy side, the dummy side of the memory block is alternately divided into one end side and the other end side for each bit line. Therefore, interference noise on the dummy side is reduced, allowing high-speed operation and high sensitivity.

In the memory device of the second invention of the present application, the sense amplifiers are arranged to be shifted from each other by a predetermined interval in the longitudinal direction of the bit lines for each bit line. Therefore, the sense amplifiers are no longer adjacent to each other in the direction perpendicular to the longitudinal direction of the bit line, making it possible to increase the pitch of the sense amplifiers.Also, it is possible to increase the pitch of the sense amplifiers. in,
- The actual bit line is also coupled to the dummy side of the adjacent bit line. Since the dummy side is always amplified to the opposite level, its interference noise is canceled out.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

First Embodiment This embodiment is an example of a DRAM, in which sense amplifiers are provided alternately for each bit line at one end and the other end of a cell block.

The main parts of the configuration are schematically shown in FIG. In the memory device of this embodiment, a pair of bit lines are extended so as to extend to both sides in the Y direction in the figure, with a sense amplifier in the middle. Here, if we pay attention to the memory block in which the word line WL is arranged, the bit lines BL, -BL are arranged side by side in the X direction in the figure with the Y direction as the longitudinal direction, and the memory block is located at which intersection of the word lines WL. Cell MC, ~MC
5 is formed. Each bit line BL, ~BL, has a sense amplifier S A + ~S A for differential amplification.
s are provided, and sense amplifiers SA, , SA3 .
SAG is arranged on the right side of the memory block in the figure, and sense amplifiers SA, , SA, are arranged on the left side of the memory block in the figure. That is, the sense amplifiers SA, ~SAs are arranged alternately at one end and the other end of the cell block for each bit line, so that sense amplifiers for adjacent bit lines are adjacent to each other in the X direction in the figure. It is said that the arrangement is such that there is no such thing. Therefore, each sense amplifier SA, ~SA, is arranged in the X direction in the figure (
(See FIG. 3), the sense amplifiers can be arranged at a pitch that is approximately twice as large as the cell size (see FIG. 3), and sense amplifiers can be arranged with a margin even when the cell is downsized.

The sense amplifiers S A + to S A s arranged alternately for each bit line at both ends of the memory block are the dummy bit lines BL, to BL, respectively.

However, this dummy side bit line BL~100T6
The bit lines also extend in different directions for each bit line. That is, the bit lines BL4, which are the dummy sides of the bit lines BL, BL, are connected to the sense amplifiers SA, BL4 in the figure.
, are extended to the left, respectively, but the bit lines BL, ,
The bit lines BL, BL, which are the dummy side of BL, are the sense amplifiers SA+, SAs, and SA in the figure.
s respectively extend to the right. Therefore, the bit line BL on the dummy side of the sense amplifier S A +, S A zS A s, π2. πT5 is a bit line πL1t extending from the sense amplifier 5A12.3A1t in the next column;
It will be made to constitute a memory block with B and 4. For example, when reading data from memory cells MC, ~MC6 connected to the word line WL, sense amplifiers S A + ~SA are activated, and sense amplifiers SAu, SA+4 connected to other memory blocks remain inactive. be done. Therefore, for example, the bit line BL on the dummy side,
, BL, , BL, are only adjacent to the bit line ■π131-dōdō, which is left inactive, so the inter-bit line interference noise on the dummy side is reduced.

In this way, in the memory device of this embodiment, the sense amplifiers are arranged alternately for each bit line at one end and the other end of the memory block, so the pitch of the sense amplifiers in the word line direction can be increased. Even when the cell size is reduced, it is advantageous in increasing sensitivity and speed. Further, on the dummy side of each bit line, adjacent bit lines become bit lines of other memory blocks. Therefore, when one is activated, the other is inactive, and inter-bit line interference noise is reduced on the dummy side.

Although word lines, memory cells, bit lines, etc. are shown in a simplified manner in FIG. 1, the memory device of this embodiment has the following features:
Memory cells are provided in a matrix at the intersections of each word line and bit line, and furthermore, bit lines and sense amplifiers are provided not only for five columns but also for a larger number.

Second Embodiment This embodiment is an example in which adjacent sense amplifiers are disposed offset by half the length of the bit line in each memory block.

The main parts of the configuration are schematically shown in FIG. In the memory device of this embodiment, a pair of bit lines are extended so as to extend to both sides in the Y direction in the figure, with a sense amplifier in the middle. Here, if we pay attention to the memory block in which word lines WL are arranged, the bit lines BL, ~BL, are arranged in parallel in the X direction in the figure, with the Y direction as the longitudinal direction, and at which intersection of the word lines WL, respectively. Memory cell MC, ~MC
5 is formed. Sense amplifiers SA, -SAS for differential amplification are connected to each bit line BL, -BL. The positions of these sense amplifiers SA, ~SA + are 1
The positions of the sense amplifiers SA, ~SAS are shifted from adjacent bit strings by approximately half the length of the bit lines in one memory block, and the sense amplifiers SA, ~SAS return to their original positions after advancing in the X direction by exactly four bit strings. For example, sense amplifier SA and sense amplifier SA s are arranged at the same position in the Y direction.

The bit lines BL+ to BLs are connected to each sense amplifier SA1.
~S As center, dummy bit line BL on the opposite side
, ~BL. Here, for example, bit line BL
, π-d,, the interference noise due to the coupling capacitance from the bit lines BL, , BL, is differentially amplified by the sense amplifier SA, the bit line BL, , π-d,
are superimposed on both at the same time. Therefore, level fluctuations due to noise are canceled out, and interference noise is reduced by that amount. Furthermore, the bit line B L s has a bit line ding.

are adjacent to each other, and the bit line BL is adjacent to the bit line R, but the distance between them is half the length of the bit line, and the distance between them is half the length of the bit line. Adjacent. Therefore, interference noise is significantly reduced compared to the conventional method.

Next, each sense amplifier SA, ~SAs, SA,.

Regarding the arrangement of S A ++ and S A +s,
Since each bit line is shifted by half the length of the bit line, four bit strings occupy the same position in the Y direction. Therefore, each sense amplifier can occupy the width of 4 bit strings, and even when the cell size is reduced, it is easy to improve the performance of the sense amplifier.

In this embodiment, the amount of positional deviation between the sense amplifiers is set to approximately half the length of the bit line for the cell block.
It is not limited to this, and it may be shifted by other lengths.

〔Effect of the invention〕

In the memory device of the present invention, the area occupied by the sense amplifiers can be expanded by arranging the sense amplifiers alternately with respect to the blocks or shifting them by a predetermined amount for each bit line. Even when scaling down, it is easy to increase speed and sensitivity. Also, due to the above structure,
Interference noise between bit lines can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a schematic layout of an example of a memory device of the present invention, FIG. 2 is a schematic layout of another example of a memory device of the present invention, and FIG. 3 is a schematic layout of an example of a conventional memory device. FIG. 4 is a waveform diagram for explaining interference noise in one example of the conventional layout. WL...Word line BL, ~BL5. π Ding, ~Ding π5 MC, ~MCs...Memory cell SA, ~SAs...Sense amplifier...Bit line patent applicant Akira Kowa, patent attorney representing Sony Corporation (2 others) No. Figure 3 No. 4

Claims (2)

[Claims] (1) In a memory device in which a pair of bit lines that are differentially amplified by a sense amplifier are distributed and arranged in the longitudinal direction of the bit lines, the sense amplifier is connected to the bit lines at one end and the other end of each memory block. A memory device characterized in that memory devices are arranged alternately. (2) In a memory device in which a pair of bit lines to be differentially amplified by a sense amplifier are distributed and arranged in the longitudinal direction of the bit line, the sense amplifier is arranged along the longitudinal direction of the bit line by a predetermined interval for each bit line. A memory device characterized in that the memory device is arranged offset in one direction.