JPH04132242A - Semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate fluctuation in the signal delivery delay time from signal supply cells to signal reception cells by placing multiple signal supply cells in separate spots within a row of cells that includes signal reception cells and supply signals from the multiple signal supply cells to the signal reception cells through the cell row interconnections. CONSTITUTION:On the LSI chip unit 1, multiple rows of cells 2, which contain multiple cells arranged in the lengthwise direction, are lined up in the up/down direction and a group of I/O cells 42 is placed along the perimeter. For each of the cell rows 2, cell signal amplifiers 3a-3c, 4a-4c, 5a-5c, and 6a-6c are placed in the middle and at either end of the row. Each column of signal amplifiers 3a-6a, 3b-6b, and 3c-6c is connected to the drive cell 8 for the I/O cell group 42 through the respective interconnections 7a, 7b, and 7c on the input side. The various signal amplifiers 3a-3c, 4a-4c, 5a-5c, and 6a-6c located in the same cell row 2 are mutually connected through the cell interconnection 9 on the output side.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor device constructed using a standard cell method.

(Prior Art) The standard cell method is a design method for realizing an LSI that satisfies a desired logic function by arranging and wiring cells having logic functions such as simple logic gates and flip-flops.

Figure 4 shows an LSI to which this standard cell method is applied.
FIG.

In FIG. 4, the chip main body 40 has a plurality of cell rows 41 each consisting of a plurality of cells arranged in the column direction, and a plurality of cell rows 41 arranged in the row direction, and an I1 which provides an interface with the outside around the cell rows 41.
A 0 cell group 42 is arranged and configured.

In each cell row 41, signal amplifiers 43 arranged into cells are arranged substantially in the center thereof so as to be in the same column. This signal amplifier 43 is driven by a drive cell 45 of an I10 cell group 42 connected to the input side via a cell row wiring 44 which is thicker than the normal wiring width, and the amplified output signal, which becomes a clock signal, for example, is connected to the cell Clock signal receiving cells such as flip-flops in row 41 (indicated by X in the diagram)
are applied to each cell row 41 via a cell row wiring 46 corresponding to each cell row 41.

In such a configuration, as the scale of LSI increases, the load capacitance increases and the distance of each cell row 41 in the column direction becomes longer, and the wiring length of each cell row wiring 46 increases. Furthermore, this increase in wiring length also increases wiring capacitance and wiring resistance.

Furthermore, an increase in the wiring length of the cell row wiring 46 also increases the variation in wiring length between the corresponding signal amplifier 43 and the clock signal receiving cell of the same cell row 41. Furthermore, the variation in wiring length between the cell row wirings 46 of the respective cell rows 41 also increases.

(Problem to be Solved by the Invention) In this way, each clock signal receiving cell receiving the clock signal output from the signal amplifier 43 is arranged at various positions within the cell row 41.
In the configuration in which is arranged approximately at the center of the cell row 41,
There was a large variation in the wiring length between the signal amplifier 43 and each clock signal receiving cell.

Therefore, the phase difference between the clock signals in the cell row wires 46 and the phase difference between the clock signals between the cell row wires 46 increases. That is, the variation in delay time until the clock signal is propagated from the signal amplifier 43 to each clock signal receiving cell arranged in the same cell row 41 increases.

Therefore, the skew of the clock signal of the entire LSI increases, which may lead to malfunction.

Therefore, the present invention has been made in view of the above, and an object of the invention is to suppress variations in wiring length in cell row wiring connecting signal supply cells and signal receiving cells, and to improve signal supply cells. An object of the present invention is to provide a semiconductor device in which variations in propagation delay time of signals supplied from a cell to a signal receiving cell are alleviated.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a cell row in which a plurality of cells including signal receiving cells are arranged in a column direction. a plurality of signal supply cells arranged discretely in each cell row of a cell row group; an output end of the plurality of signal supply cells arranged in each cell row; and a cell identical to the plurality of signal supply cells. A plurality of cell row wirings connecting the input ends of the signal receiving cells arranged in the rows, and a plurality of cell row wirings arranged corresponding to the row direction among the plurality of signal supplying cells arranged in the respective cell rows. It is composed of a plurality of inter-cell wiring lines that connect the input ends of the signal supply cells of the cell rows.

(Function) In the above configuration, the present invention arranges a plurality of signal supply cells in a scattered manner in a cell row including a signal reception cell, and connects the signal reception cell from these plurality of signal supply cells via cell row wiring. I am trying to supply a signal to.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a diagram showing the configuration of a semiconductor device according to an embodiment of the present invention. The embodiment shown in the same figure is similar to that shown in FIG. 4, in which a plurality of celled signal amplifiers are arranged in one cell row in a semiconductor device constructed by the standard cell method, and the signal amplifiers are The clock signal is supplied to the corresponding clock signal receiving cell.

In FIG. 1, in a chip body 1 of an LSI, a plurality of cell rows 2 each consisting of a plurality of cells arranged in a column direction are arranged in the row direction, and an I10 cell group 42 is arranged around them.

Each cell row 2 has signal amplifiers 3a to 3c and 4a to 4c formed into cells approximately at the center and at both ends.

5a to 5c and 6a to 6c are arranged. Therefore, the signal amplifiers 3a, 4a, 5a, 6a arranged at one end of each cell row 2 and the signal amplifiers 3b, 4b, 5b, 6b arranged approximately at the center of each cell row 2.
The signal amplifiers 3c, 4c, 5c, and 6c arranged at the other end of each cell row 2 are arranged in the same column.

Signal amplifiers 3a to 6a, 3 arranged in the same row, respectively.
b ~ 6b, 3c ~ 6c are connected to the I10 cell group 42 via the corresponding cell row wirings 7a, 7b, 7c on the solenoid input side.
The respective signal amplifiers 3B to 3c, 4a are connected to the drive cells 8 and arranged in the same cell row 2.
~4 c, 5 a~5 c, 6 a ~6
The output sides of cells c are connected to each other via corresponding cell row wirings 9.

Each cell row wiring 9 is connected to a clock input terminal of a clock signal receiving cell (indicated by an x mark in the figure) arranged in the corresponding cell row 2.

In such a configuration, each clock signal receiving cell arranged in the same cell row 2 receives the signal whose wiring distance is the shortest among the signal amplifiers arranged approximately at the center and at both ends of the same cell row 2. A clock signal output from the amplifier will be given. Therefore, the delay time until the clock signal is propagated to the clock receiving cell is as follows:
, 3c to 6c and the corresponding clock signal receiving cells depend on the wiring length of the cell row wiring 9. That is, signal amplifiers 33-5a for the arrangement of clock signal receiving cells.

It depends on the position where 3b to 6b and 3c to 6c are arranged.

In the configuration shown in FIG. 1, the positions where a plurality of signal amplifiers are arranged within one cell row 2 are determined according to the following procedure.

First, in the cell row wiring 9, the maximum wiring distance between the signal amplifier and the clock signal receiving cell arranged in the same cell row 2 in which this signal amplifier is arranged is determined by the preset tolerance value of the clock signal skew. The number and position of wiring between cell rows are determined so that the signal amplifier and clock signal receiving cell are connected and wired so as not to exceed the determined maximum wiring distance. A signal amplifier is placed in each cell row 2 at a position corresponding to the wiring.

The number N of interconnections between cell rows can be determined by the following equation once the maximum interconnection length from the output section of the signal amplifier to the clock signal receiving cell in the corresponding cell row and the length of the cell row are determined.

N-L/cross (1) Also, the maximum wiring length is determined by the following formula.

T-1″XrX Hl-XC+CF) ± 1(2)
Hi-n 1-
(3) Here, T: Allowable delay time (skew): Minimum interval between clock signal receiving cells: Wiring resistance per unit length C: Wiring capacitance per unit length GF: Input of clock signal receiving cells Capacity n: Allowable number of clock signal receiving cells within the maximum wiring length.

In the above formula, when the minimum interval between clock signal receiving cells in the cell row direction is determined from the automatic cell placement results, this value and the allowable delay time T set as the specification value are calculated.
and the process-specific wiring resistance value ", wiring capacitance C1 from the input capacitance CF of the clock signal receiving cell, the allowable delay time T
The number n of clock signal receiving cells within a range not exceeding n is calculated using the above equation (2).

Further, the maximum wiring length is calculated by the above equation (3) from the value of n calculated by the equation (2) and the minimum interval hair of the clock signal receiving cells.

Therefore, from the maximum wiring length l and the cell row length given as the specification value, the number N of latitude lines between cell rows is calculated as above (1
)Desired.

Therefore, according to the above procedure, the position of the signal amplifier in cell row 2 is determined by the maximum wiring distance between the signal amplifier and the clock signal receiving cell and the position of the clock signal receiving cell. are not necessarily arranged approximately at the center and at both ends of the cell row 2 as shown in FIG.

In this way, the position of the signal amplifier is determined relative to the position of the clock signal receiving cell, and the signal amplifier is placed, thereby suppressing variations in the wiring distance between the signal amplifier and the clock signal receiving cell. , variations in the propagation delay time of the clock signal are alleviated.

FIG. 2 is a diagram showing another embodiment of the invention.

The feature of the embodiment shown in FIG. 1 is that, in contrast to the structure shown in FIG.
Add 7c to any number of cells with any wiring width! 110, and the other configurations are the same.

In such a configuration, it is possible to reduce the wiring resistance from the drive cell 8 to each of the signal amplifiers 3a to 5a, 3b to 6b, and 3° to 6c. Variations in propagation delay times of clock signals between amplifiers can be alleviated, and the same effects as in the embodiments described above can be obtained.

FIG. 3 is a diagram showing still another embodiment of the present invention.

The feature of the embodiment shown in FIG.
The output sides of a, 3b to 6b, and 3c to 6c are connected by the inter-row wiring 11 of an appropriate wiring width, so that the output sides are connected to all the signal amplifiers.The other configuration is as shown in Fig. 1. It is similar to

With such a configuration, variations in the propagation delay time of clock signals between the cell row wirings 9 can be alleviated, and the same effects as in the above-described embodiment can be obtained.

Note that the present invention is not limited to the above-described embodiments, and for example, the propagated signal does not have to be a clock signal, but may be any signal whose propagation delay time variations affect circuit operation. Further, the three embodiments described above may be implemented in combination as appropriate.

[Effects of the Invention] As explained above, according to the present invention, a plurality of signal supply cells are discretely arranged in a cell row including a signal reception cell,
Since signals are supplied from these plurality of signal supply cells to the signal reception cells via the cell row wiring, it is possible to suppress variations in the wiring distance between the signal supply cells and the signal reception cells.

This makes it possible to alleviate variations in propagation delay time in signals supplied from signal supply cells to signal receiving cells, and to suppress "operations caused by variations in delay time in signal propagation." It becomes like this.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a semiconductor device according to one embodiment of the invention, FIGS. 2 and 3 are diagrams showing the configuration of a semiconductor device according to another embodiment of the invention, and FIG. 4 is a standard diagram. 1 is a diagram showing the configuration of a conventional semiconductor device constructed using a cell method. 1...Chip body 2...Cell row 3a to 6a, 3b to 6b 3cm6c...Signal amplifier 7a, 7b, 7c, 11-Cell inter-row wiring 8...Drive cell 9.10...Cell row wiring

Claims (3)

[Claims] (1) A plurality of signal supply cells discretely arranged in each cell row of a cell row group in which a plurality of cells including signal receiving cells are arranged in the column direction and cell rows are arranged in the row direction; a plurality of cell row wirings connecting output ends of the plurality of signal supply cells arranged in each cell row and input ends of the signal reception cells arranged in the same cell row as the plurality of signal supply cells; Among the plurality of signal supply cells arranged in each cell row, the cell row wiring includes a plurality of cell interrow wirings that connect the input ends of the signal supply cells of different cell rows arranged corresponding to the row direction. Characteristic semiconductor devices. (2) The semiconductor device according to claim 1, wherein the plurality of inter-cell interconnections are connected by a plurality of cell row interconnections different from the plurality of cell row interconnections. (3) The signal supply cell whose input end is connected and wired by the cell interrow wiring has an output end which is connected and wired by a cell interrow wiring different from the plurality of cell interrow wirings. Alternatively, the semiconductor device according to claim 2.