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JPH04132239A - wafer chuck - Google Patents

wafer chuck

Info

Publication number
JPH04132239A
JPH04132239A JP2253307A JP25330790A JPH04132239A JP H04132239 A JPH04132239 A JP H04132239A JP 2253307 A JP2253307 A JP 2253307A JP 25330790 A JP25330790 A JP 25330790A JP H04132239 A JPH04132239 A JP H04132239A
Authority
JP
Japan
Prior art keywords
wafer
electrodes
voltage
positive
alternating voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2253307A
Other languages
Japanese (ja)
Inventor
Masaya Kobayashi
雅哉 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2253307A priority Critical patent/JPH04132239A/en
Publication of JPH04132239A publication Critical patent/JPH04132239A/en
Pending legal-status Critical Current

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  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

PURPOSE:To be able to quickly attach and detach a wafer by imprinting positive and negative pulse alternating voltage at different phases into multiple electrodes placed in an insulation body and to attach the wafer by the static electricity produced. CONSTITUTION:For the electrodes A1, A2, A3, B1, B2 and B3, 12 wedge-shaped electrode boards are placed in a circular format, the insulation body 11 is a silicon resin, and when the platform 12 is an etching system, these are set up as conductive electrodes. With this structure, a reverse alternating voltage is applied on electrodes with the same code number during the same phase, the pulse voltage is divided into 3 phases, and reverse voltage is applied with same phase on A1 and B1, A2 and B2, and A3 and B3, respectively. For the time intervals between T1 to T2 and T3 to T4, positive and negative voltage is applied in 3 phases while shifting other electrodes. The pulse alternating voltage applied has a voltage strength of 1KV, pulse width of 5sec, and a frequency of about 0.33Hz. If positive and negative voltages are continuously applied on any pair of A and b electrodes, the attachment strength is not lost and since the applied voltage reverses positive and negative polarity in a short time period, it is possible to remove the wafer quickly without any residual polarization.

Description

【発明の詳細な説明】 〔概 要〕 ウェハープロセスにおけるウェハー搬送やウェハー処理
装置のステージに用いられるウェハーチャックに関し、 速やかにウェハーの着脱がおこなえるようにすることを
目的とし、 絶縁体に埋没された複数の電極に正負パルスの交番電圧
を印加して、該交番電圧によって誘起された静電力によ
ってウェハーを吸着するようにしたことを特徴とする。
[Detailed Description of the Invention] [Summary] Regarding wafer chucks used for wafer transport in wafer processes and stages of wafer processing equipment, the purpose of this invention is to enable quick attachment and detachment of wafers. It is characterized in that an alternating voltage of positive and negative pulses is applied to a plurality of electrodes, and the wafer is attracted by electrostatic force induced by the alternating voltage.

前記交番電圧を複数の電極に位相をずらせて印加するよ
うにしたことを特徴とする。
It is characterized in that the alternating voltage is applied to a plurality of electrodes with a phase shift.

前記絶縁体がシリコン樹脂またはセラミックスからなる
ことを特徴とする。
It is characterized in that the insulator is made of silicone resin or ceramics.

前記電極は楔形状板からなり、全体が円形に構成されて
いることを特徴とする。
The electrode is characterized in that it consists of a wedge-shaped plate and has a circular shape as a whole.

〔産業上の利用分野〕[Industrial application field]

本発明はウェハープロセスにおけるウェハー搬送やウェ
ハー処理装置のステージに用いられるつエバーチャック
に関する。
The present invention relates to an everchuck used for wafer transport in a wafer process or a stage of a wafer processing apparatus.

半導体製造のウェハープロセスにおいては、ウェハーが
自動搬送されており、また、エツチング装置や気相成長
装置などのウェハー処理装置ではウェハーをステージに
吸着(チャッキング)させており、本発明はそのウェハ
ーをチャッキングするウェハーチャックの改善に関して
いる。
In the wafer process of semiconductor manufacturing, wafers are automatically transported, and in wafer processing equipment such as etching equipment and vapor phase growth equipment, wafers are adsorbed (chucked) on a stage. This paper concerns the improvement of wafer chucks.

〔従来の技術と発明が解決しようとする課題〕従来より
ウェハープロセスにおいては静電吸着式のウェハーチャ
ックが重用されており、第4図は従来のウェハーチャッ
クの概要断面図を示している。記号1は直流電源、2は
ウェハーチャック。
[Prior Art and Problems to be Solved by the Invention] Conventionally, electrostatic adsorption type wafer chucks have been used extensively in wafer processes, and FIG. 4 shows a schematic cross-sectional view of a conventional wafer chuck. Symbol 1 is a DC power supply and 2 is a wafer chuck.

3はウェハーで、ウェハーチャック2は絶縁体内部にA
電極とB電極との二電極(例えば、半月形の二電極)が
埋没されている構造で、図のように画電極に正負の直流
電圧(約1〜1.5 KVの高圧)を印加すると絶縁体
が誘電分極をおこし、その絶縁体表面にそれぞれ正負の
電荷が誘起されて、その静電力によってウェハーがチャ
フキングされるものである。
3 is a wafer, and wafer chuck 2 has A inside the insulator.
It has a structure in which two electrodes, the electrode and the B electrode (for example, two half-moon-shaped electrodes) are buried, and when positive and negative DC voltages (high voltage of about 1 to 1.5 KV) are applied to the picture electrodes as shown in the figure, The insulator causes dielectric polarization, and positive and negative charges are induced on the surface of the insulator, and the wafer is chaffed by the electrostatic force.

ところが、ウェハーをチャッキングした後、これが容易
に剥がれ難いという問題があって、第5図(a)、 (
b)にその従来の問題点を説明する図を示している。即
ち、同図(a)に示すように、直流電源1をオン(on
)すると正電圧を印加したAI極側の絶縁体が誘電分極
をおこしてウェハーチャック2(絶縁体)表面に正電荷
を誘起する。そうすると、対向面のウェハーに負電荷が
誘起されて、そのためにウェハーが吸着される。同時に
、他方のBt極側に負電圧を印加すると、同様の誘電分
極のために対向したウェハー面に正電荷が誘起されてウ
ェハーが吸着される。このように、ウェハーチャック2
内の電極とは逆極性の電荷がウェハー面に誘起されて、
そのクーロン力(静電力)によってウェハーが吸着され
る。これが静電吸着の原理であり、この方式によるウェ
ハーチャックが静電吸着式チャックである。
However, after chucking the wafer, there is a problem that it is difficult to peel off easily.
b) shows a diagram illustrating the problems of the conventional method. That is, as shown in FIG.
) Then, the insulator on the AI pole side to which a positive voltage is applied causes dielectric polarization and induces a positive charge on the surface of the wafer chuck 2 (insulator). Then, negative charges are induced in the wafer on the opposing surface, which causes the wafer to be attracted. At the same time, when a negative voltage is applied to the other Bt pole side, positive charges are induced on the opposing wafer surface due to the similar dielectric polarization, and the wafer is attracted. In this way, wafer chuck 2
A charge with the opposite polarity to the inner electrode is induced on the wafer surface,
The wafer is attracted by the Coulomb force (electrostatic force). This is the principle of electrostatic chuck, and a wafer chuck based on this method is an electrostatic chuck.

しかし、次いで処理完了後にウェハーチャックからウェ
ハーを剥がすため、同図(b)に示すように、直流電源
lをオフ(off)するとウェハーチャック2内の絶縁
体の分極は直ぐに消滅せずに残留して、そのためウェハ
ーチャックの吸着力が消えず、ウェハー3が速やかに剥
離されないという問題がある。特に、シリコン樹脂やア
ルミナなどの絶縁体は分極の残留時間が長く、また、長
時間の吸着や連続的な使用をすれば電荷が蓄積してウェ
ハーが容易に剥離しなくなり易い。
However, since the wafer is then peeled off from the wafer chuck after the processing is completed, when the DC power supply 1 is turned off, as shown in FIG. Therefore, there is a problem that the adsorption force of the wafer chuck does not disappear and the wafer 3 is not peeled off quickly. In particular, insulators such as silicone resin and alumina have a long residual polarization time, and if they are adsorbed for a long time or used continuously, charges will accumulate and the wafer will not easily peel off.

次表はシリコン樹脂からなる絶縁体を用いたウェハーチ
ャックの吸着時間(分)と脱離状態との関係を示す表で
、Oは脱離良好、Δは脱離やや困難、×は脱離困難を示
している。
The following table shows the relationship between the adsorption time (minutes) of a wafer chuck using an insulator made of silicone resin and the desorption state, where O means good desorption, Δ means slightly difficult desorption, and × means difficult desorption. It shows.

本発明はこのような問題点を解消させて、速やかにウェ
ハーの着脱がおこなえるようにしたウェハーチャックを
提案するものである。
The present invention solves these problems and proposes a wafer chuck that allows quick loading and unloading of wafers.

〔課題を解決するための手段〕[Means to solve the problem]

その課題は、第1図の実施例に示すように、絶縁体11
 (例えば、シリコン樹脂、セラミックス)に埋没され
た複数の電極(例えば、円形に構成されに複数の模形状
電掻板”)A、、A、、A3B、、Bt、B2に位相を
ずらせた正負パルスの交番電圧(13は交番電圧電源)
を印加して、該交番電圧によって誘起された静電力によ
ってウェハーを吸着するようにしたウェハーチャックに
よれば解消される。
The problem is as shown in the embodiment of FIG.
(e.g., a plurality of electrodes embedded in silicone resin, ceramics) (e.g., a plurality of circularly configured electric scraping plates) A, , A, , A3B, , Bt, B2 with positive and negative phases shifted. Pulse alternating voltage (13 is alternating voltage power supply)
This problem can be solved by using a wafer chuck that applies an alternating voltage and attracts the wafer by the electrostatic force induced by the alternating voltage.

このように、ウェハーが速やかに着脱できないことは自
動搬送に支障をきたし、ウェハー処理装置のスルーブツ
ト向上を阻害することになる。
As described above, the inability to quickly attach and detach wafers impedes automatic transportation and impedes improvement in the throughput of wafer processing equipment.

〔作 用〕[For production]

即ち、本発明は、複数の電極にパルス交番電圧を印加し
て、且つ、要すれば、隣接電極毎に位相をずらせて印加
する。そうすると、短時間に印加電圧が正負逆転するた
めに絶縁体に誘電分極が残留せず、従って、オフ時に直
ぐにウェハーを離脱させることができる。
That is, in the present invention, a pulsed alternating voltage is applied to a plurality of electrodes, and if necessary, the voltage is applied with a phase shift for each adjacent electrode. In this case, since the applied voltage is reversed in a short period of time, no dielectric polarization remains in the insulator, and therefore, the wafer can be removed immediately when the insulator is turned off.

〔実 施 例〕〔Example〕

以下に図面を参照して実施例によって詳細に説明すると
、第1図(a)、 (b)は本発明にかかるウェハーチ
ャックの要部図を示しており、同図(a)は平面図、同
図ら)は同図(a)のCC断面図である。図中の記号1
1はシリコン樹脂からなる絶縁体、12はアルミニウム
の台座、 13は交番電圧電源、A、、A。
1(a) and 1(b) show main parts of a wafer chuck according to the present invention, and FIG. 1(a) is a plan view, FIG. 3) is a CC sectional view of FIG. Symbol 1 in the diagram
1 is an insulator made of silicone resin, 12 is an aluminum pedestal, 13 is an alternating voltage power source, A.

、As 、B+ 、Bz 、BIは電極(、タングステ
ン電極)で、電極数は合計12個、模形状の電極板を円
形に配置しである。絶縁体11はシリコン樹脂で、その
抵抗率は101s〜10”/Ω1程度であり、厚さは4
00μm程度にする。絶縁体はシリコン樹脂の他、セラ
ミックス、石英、ポリイミド、プラスチックなどを用い
てもよい、また、台座12はエツチング装置の場合に導
電電極として役立たせるものである。
, As , B+ , Bz , and BI are electrodes (tungsten electrodes), and the number of electrodes is 12 in total, and model-shaped electrode plates are arranged in a circle. The insulator 11 is made of silicone resin, has a resistivity of about 101s to 10"/Ω1, and a thickness of 4.
The thickness should be approximately 00 μm. In addition to silicone resin, ceramics, quartz, polyimide, plastic, etc. may be used as the insulator, and the pedestal 12 serves as a conductive electrode in the case of an etching device.

この第1図のように構成し、同一付加記号の電極には同
一相で逆電圧の交番電圧を印加して、例えば、第2図の
交番電圧印加タイムチャート図に示すように、パルス電
圧を3相にずらせて、A。
With the configuration shown in Fig. 1, an alternating voltage of the same phase and a reverse voltage is applied to the electrodes with the same additional symbol, and a pulse voltage is generated, for example, as shown in the alternating voltage application time chart of Fig. 2. Shift to 3 phases, A.

とB+ 、AtとBz 、AsとB、とを同相で相互に
逆電圧を印加する。即ち、時間0〜T、でAtに正電圧
、B、に負電圧を印加して、時間T2〜T3でA1に負
電圧、BIに正電圧を印加し、その間の時間T、〜T2
および時間T、〜T4に他の電極をずらせて3相で正負
の電圧を印加し、電圧強度はIKV、パルス幅5 se
cで、周波数0.33Hz程度のパルス交番電圧を印加
する。
and B+, At and Bz, and As and B are in phase and reverse voltages are applied to each other. That is, a positive voltage is applied to At and a negative voltage is applied to B from time 0 to T, and a negative voltage is applied to A1 and a positive voltage is applied to BI from time T2 to T3.
Then, at time T, ~T4, the other electrodes were shifted and positive and negative voltages were applied in three phases, the voltage intensity was IKV, and the pulse width was 5 se.
At c, a pulsed alternating voltage with a frequency of about 0.33 Hz is applied.

このように、電極を多極化して位相をずらせ、絶えずい
ずれか一対のA電極とB電極とに正負の電圧を印加して
おけば吸着力は消失しない、しかも、短時間に印加電圧
が正負逆転するために分極が残留せず、直ぐにウェハー
を離脱させることができる。第3図(a)〜(d)は本
発明にがかるウエノ\−チャックの分極状態を示す図で
、AI電極と81電極との部分を例示しており、3はウ
ェハー、 10は本発明にかかるウェハーチャックであ
る。同図(a)は時間0〜T、の状態、同図(b)は時
間T、〜T2、同図(C)は時間T2〜T3.同図(d
)は時間T。
In this way, if the electrodes are made multipolar and the phase is shifted, and positive and negative voltages are constantly applied to any pair of A and B electrodes, the adsorption force will not disappear, and moreover, the applied voltage can be reversed in a short period of time. Because of this, no polarization remains and the wafer can be removed immediately. FIGS. 3(a) to 3(d) are diagrams showing the polarization state of the wafer chuck according to the present invention, illustrating the portions of the AI electrode and the 81 electrode, where 3 is the wafer and 10 is the wafer according to the present invention. This is such a wafer chuck. The figure (a) shows the state from time 0 to T, the figure (b) shows the state from time T to T2, and the figure (C) shows the state from time T2 to T3. The same figure (d
) is time T.

〜T4の状態を図示しているが、このように前後の印加
時の電圧が逆になるために分極がすぐに消滅して、電圧
をオフした時には分極は残留しない。
-T4 is shown in the figure, but since the voltages applied before and after are reversed in this way, the polarization disappears immediately, and no polarization remains when the voltage is turned off.

次表は本発明にかかるウェハーチャックの吸着時間(分
)と脱離状態との関係を示しており、長時間に亙っても
脱離は良好(0)なことが判る。
The following table shows the relationship between the adsorption time (minutes) and the desorption state of the wafer chuck according to the present invention, and it can be seen that the desorption is good (0) even over a long period of time.

上記実施例は12個の電極を配置して、位相にずらせる
例で説明したが、位相をずらすことなく多電極を2つに
分類し、隣接電極に交互に正負のパルス交番電圧を印加
しても同様の効果が得られる。
The above embodiment was explained using an example in which 12 electrodes are arranged and shifted in phase, but the multiple electrodes are divided into two without shifting the phase, and positive and negative pulsed alternating voltages are applied alternately to adjacent electrodes. The same effect can be obtained.

また、位相をずらす場合にも、上記実施例にかかわらず
、電極数や位相を多少増減させても良い。
Furthermore, when shifting the phase, the number of electrodes and the phase may be increased or decreased to some extent, regardless of the above embodiments.

〔発明の効果〕〔Effect of the invention〕

以上の説明から明らかなように、本発明にかかるウェハ
ーチャックを用いると、ウエノ\−を速やかに着脱でき
て、ウェハープロセスの円滑な自動処理ができ、ウェハ
ープロセスの効率化、半導体デバイスの高品質化に大き
く寄与するものである。
As is clear from the above explanation, when the wafer chuck according to the present invention is used, the wafer can be quickly attached and detached, and the wafer process can be carried out smoothly and automatically, resulting in improved efficiency of the wafer process and high quality of semiconductor devices. This will greatly contribute to the

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)、 (b)は本発明にかかるウェハーチャ
ックの要部図、 第2図は交番電圧印加タイムチャート図、第3図(a)
〜(d)は本発明にかかるウエノ\−チャ・ンクの分極
状態を示す図、 第4図は従来のウェハーチャックの概要断面図、第5図
(a)、(b)は従来の問題点を説明する図である。 図において、 1は直流電源、     2はウェハーチャック、3は
ウェハー 10は本発明にかかるウェハーチャック、’tk 11は絶縁体、 12は台座、 13は交番電圧を源、 A。 B。 B。 B。 は 電極 を示している。
Figures 1 (a) and (b) are main parts of the wafer chuck according to the present invention, Figure 2 is an alternating voltage application time chart, and Figure 3 (a).
- (d) are diagrams showing the polarization state of the wafer chuck according to the present invention, Figure 4 is a schematic cross-sectional view of a conventional wafer chuck, and Figures 5 (a) and (b) are problems with the conventional wafer chuck. FIG. In the figure, 1 is a DC power supply, 2 is a wafer chuck, 3 is a wafer 10 is a wafer chuck according to the present invention, 11 is an insulator, 12 is a pedestal, 13 is an alternating voltage source, A. B. B. B. indicates an electrode.

Claims (4)

【特許請求の範囲】[Claims] (1)絶縁体に埋没された複数の電極に正負パルスの交
番電圧を印加して、該交番電圧によって誘起された静電
力によってウェハーを吸着するようにしたことを特徴と
するウェハーチャック。
(1) A wafer chuck characterized in that an alternating voltage of positive and negative pulses is applied to a plurality of electrodes buried in an insulator, and a wafer is attracted by electrostatic force induced by the alternating voltage.
(2)前記交番電圧を複数の電極に位相をずらせて印加
するようにしたことを特徴とする請求項(1)のウェハ
ーチャック。
(2) The wafer chuck according to claim 1, wherein the alternating voltage is applied to a plurality of electrodes with a phase shift.
(3)前記絶縁体がシリコン樹脂またはセラミックスか
らなることを特徴とする請求項(1)のウェハーチャッ
ク。
(3) The wafer chuck according to claim 1, wherein the insulator is made of silicone resin or ceramics.
(4)前記電極は楔形状板からなり、全体が円形に構成
されていることを特徴とする請求項(1)のウェハーチ
ャック。
(4) The wafer chuck according to claim (1), wherein the electrode is made of a wedge-shaped plate and has a circular shape as a whole.
JP2253307A 1990-09-21 1990-09-21 wafer chuck Pending JPH04132239A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2253307A JPH04132239A (en) 1990-09-21 1990-09-21 wafer chuck

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2253307A JPH04132239A (en) 1990-09-21 1990-09-21 wafer chuck

Publications (1)

Publication Number Publication Date
JPH04132239A true JPH04132239A (en) 1992-05-06

Family

ID=17249473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2253307A Pending JPH04132239A (en) 1990-09-21 1990-09-21 wafer chuck

Country Status (1)

Country Link
JP (1) JPH04132239A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0647642A (en) * 1992-01-21 1994-02-22 Applied Materials Inc Insulating type electrostatic chuck and its exciting method
US5452177A (en) * 1990-06-08 1995-09-19 Varian Associates, Inc. Electrostatic wafer clamp
JPH1027567A (en) * 1996-07-10 1998-01-27 Nissin Electric Co Ltd Substrate holding device
JPH11106916A (en) * 1997-10-01 1999-04-20 Anelva Corp Plasma treating device
US5969934A (en) * 1998-04-10 1999-10-19 Varian Semiconductor Equipment Associats, Inc. Electrostatic wafer clamp having low particulate contamination of wafers
US6362946B1 (en) 1999-11-02 2002-03-26 Varian Semiconductor Equipment Associates, Inc. Electrostatic wafer clamp having electrostatic seal for retaining gas
US6538873B1 (en) 1999-11-02 2003-03-25 Varian Semiconductor Equipment Associates, Inc. Active electrostatic seal and electrostatic vacuum pump
JP2003520416A (en) * 1998-11-10 2003-07-02 セムコ エンジニアリング エス.アー. Electrostatic holding device
JP2009141003A (en) * 2007-12-04 2009-06-25 Nhk Spring Co Ltd Electrostatic chuck
JP2014107382A (en) * 2012-11-27 2014-06-09 Fuji Electric Co Ltd Detachment method of semiconductor substrate
KR20190078439A (en) * 2017-12-26 2019-07-04 캐논 톡키 가부시키가이샤 Electrostatic chuck, film forming apparatus including electrostatic chuck, substrate holding and separating method, film forming method including the same, and manufacturing method of electronic device using the same
KR102085447B1 (en) * 2018-09-21 2020-03-05 캐논 톡키 가부시키가이샤 Electrostatic chuk system, apparatus for forming film, separation method of attracted body, method for forming film, and manufacturing method of electronic device

Cited By (15)

* Cited by examiner, † Cited by third party
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US6388861B1 (en) 1990-06-08 2002-05-14 Varian Semiconductor Equipment Associates, Inc. Electrostatic wafer clamp
US5452177A (en) * 1990-06-08 1995-09-19 Varian Associates, Inc. Electrostatic wafer clamp
JP2603417B2 (en) * 1992-01-21 1997-04-23 アプライド マテリアルズ インコーポレイテッド Insulation type electrostatic chuck and excitation method
JPH0647642A (en) * 1992-01-21 1994-02-22 Applied Materials Inc Insulating type electrostatic chuck and its exciting method
JPH1027567A (en) * 1996-07-10 1998-01-27 Nissin Electric Co Ltd Substrate holding device
JPH11106916A (en) * 1997-10-01 1999-04-20 Anelva Corp Plasma treating device
US5969934A (en) * 1998-04-10 1999-10-19 Varian Semiconductor Equipment Associats, Inc. Electrostatic wafer clamp having low particulate contamination of wafers
JP2003520416A (en) * 1998-11-10 2003-07-02 セムコ エンジニアリング エス.アー. Electrostatic holding device
JP4763890B2 (en) * 1998-11-10 2011-08-31 セムコ エンジニアリング エス.アー. Electrostatic holding device
US6538873B1 (en) 1999-11-02 2003-03-25 Varian Semiconductor Equipment Associates, Inc. Active electrostatic seal and electrostatic vacuum pump
US6362946B1 (en) 1999-11-02 2002-03-26 Varian Semiconductor Equipment Associates, Inc. Electrostatic wafer clamp having electrostatic seal for retaining gas
JP2009141003A (en) * 2007-12-04 2009-06-25 Nhk Spring Co Ltd Electrostatic chuck
JP2014107382A (en) * 2012-11-27 2014-06-09 Fuji Electric Co Ltd Detachment method of semiconductor substrate
KR20190078439A (en) * 2017-12-26 2019-07-04 캐논 톡키 가부시키가이샤 Electrostatic chuck, film forming apparatus including electrostatic chuck, substrate holding and separating method, film forming method including the same, and manufacturing method of electronic device using the same
KR102085447B1 (en) * 2018-09-21 2020-03-05 캐논 톡키 가부시키가이샤 Electrostatic chuk system, apparatus for forming film, separation method of attracted body, method for forming film, and manufacturing method of electronic device

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