JPH04132078A - Memory refresh system - Google Patents

Abstract

PURPOSE:To attain high-speed access at all times without contended with a refresh cycle from a CPU by providing a decision circuit knowing the refresh operation during the CPU performs the access of an I/O and a ROM other than a memory and a timer with clear function knowing the elapsed time from the former refresh request operation. CONSTITUTION:The refresh operation is performed when a CPU A performs access other than the DRAM such as the I/O or the ROM to eliminate the contention with memory access. On the other hand, as for the system without guarantee performing the access of the I/O and ROM in a constant cycle, the elapsed time is monitored from a refresh request signal 3 by means of a timer C with clear function, and the refresh request is transmitted each time it occurs. Thus, the high-speed access can be expected at all times from the CPU A without contented with the refresh cycle, and the throughput of the entire system can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to equipment that uses DRAM as a main memory element, such as computers and word processors, or as a CRT-controlled display memory (commonly known as VRAM).

(Prior Art) DRAMs have recently been widely used as main memory elements in computers and word processors because they have a low bit unit price and a large capacity per unit area. DRA
, M are characterized by read/write operations and random access, and similar to this is static RA, M (abbreviated as Fukishita SRAM). SRAM
Due to the structure of the flip-flop element, the storage capacity is one-fourth that of DRAM of the same technology, so it is not suitable for systems using large-capacity memories due to its cost and packaging density. On the other hand, since DRAM stores charge by storing it in a capacitor, it is necessary to recharge the capacitor at regular intervals. This is a refresh operation, and the DRAM is
It is difficult to control compared to M. Normal refresh operation is approximately 16μ for the same DRAM (same chip)
It is necessary to perform this every s. As a refresh method,
RAS only refresh, CAS before RAS refresh, hidden refresh, etc. are commonly used. If the refresh operation is not performed within a certain time,
Since data cannot be retained, a timer, counter, clock, etc. are usually used to request operation at regular intervals. At this time, memory access from CPtJ occurs (
When a conflict occurs between the two (hereinafter abbreviated as memory access), some kind of conflict circuit operates in the system to adjust the two.

(Problem to be Solved by the Invention) However, in a competitive circuit, if a refresh request takes priority over a memory access request, C
PU is (refresh cycle + precharge time)
You will have to wait for several minutes.

Alternatively, the CPU will be held and refreshed. These consume extra time in memory cycles that require fast access, reducing system performance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory refresh method that eliminates the conventional drawbacks and allows a CPU to always expect high-speed access without competing with refresh cycles.

(Means for Solving the Problems) The memory refresh method of the present invention includes a determination circuit that determines when a refresh operation is being performed by the CPU while accessing Ilo or ROM other than the memory, and a determination circuit that determines the elapsed time from the previous refresh request operation. It is equipped with a timer with a clear function.

(Function) In the above means, if the CPU is 170 or ROM etc.
A refresh operation is performed when an access other than AM is performed to eliminate conflict with memory access. However, Ilo.

For systems in which there is no guarantee that ROM access will be performed at a fixed period (within 16 μs), a timer is used to monitor the elapsed time since the previous refresh request signal, and a refresh request is issued each time.

(Embodiment) FIG. 1 is a block diagram of a memory refresh method in an embodiment of the present invention. In the figure, A is the CPU, B is a determination circuit that determines whether or not a device other than DRAM such as Ilo or ROM is being accessed based on command signal 1 output from CPUA, and 2 is a refresh signal output from determination circuit B. C is a timer with a clear function that monitors the elapsed time since refresh enable signal 2 was last enabled. 3 is a refresh request signal output by monitoring from refresh enable signal 2 or timer 〇. D is a refresh request signal from CPUA. A competition circuit performs competition between a memory access request and a refresh request signal 3, and 4 is an access signal for the DRAM after arbitration.

In the above configuration, timer 〇 is the maximum time (approximately 16 μs) that the DRAM must perform a refresh operation.
). When CPUA accesses Ilo, determination circuit B outputs refresh enable signal 2 based on command signal 1. Upon receiving the refresh enable signal 2, the clear function timer 〇 clears the refresh request signal 3 and outputs the refresh request signal 3 to the competition circuit. At this time, since the command signal 1 does not request memory access (because it accesses Ilo), the refresh operation can be performed on the DRAM without conflict in the conflict circuit. In general, I10 access takes longer than access to DRAM, so when the CPU finishes I10 access, the refresh operation is also finished, and even if a memory access request comes immediately after I10 access, there will be no conflict.

Next, as shown in FIG.
) will be explained below.

Due to the previous I10 access, refresh enable signal 2
is enabled, timer C is cleared once, and the elapsed time since the previous refresh request is measured. This timer is cleared every time the refresh enable signal 2 becomes valid, but if it is not cleared even after the maximum refresh interval time of the DRAM is reached, a refresh request signal 3 is output from timer 0 in addition to the refresh enable signal. Request a refresh operation. At this time, competition may occur due to competition circuits, but the probability of this is low. Further, even if the CPU does not access the memory for a long time, the refresh operation is performed normally.

(Effects of the Invention) According to the present invention, it is possible to always expect high-speed access from the CPU without competing with the refresh cycle, and the throughput of the entire system can be improved. The effect is great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory refresh method according to an embodiment of the present invention, FIG. 2 is a series of cycles when a refresh operation is prioritized in a competitive circuit, and FIG. 3 is a refreshable signal by the maximum refresh interval time. This is a timing chart when the output is not output. A...CPU% B...Judgment circuit, C...Timer with clear function D...Conflict circuit, 1.
...Command signal, 2.. Refresh enable signal, 3.. Refresh request signal, 4.. Access signal for DRAM after arbitration. Patent applicant Matsushita Electric Industrial Co., Ltd.

Claims (1)

[Claims] The central processing unit (hereinafter abbreviated as CPU) has I/O, ROM (
a determination circuit that can determine whether access is being made to a device other than DRAM (dynamic random access memory) such as a read-only memory; a refresh enable signal from the determination circuit that indicates that an access is in progress; It consists of a timer with a clear function that can monitor the elapsed time after the enabling signal becomes valid, and a competition circuit that competes and arbitrates between the DRAM access request from the CPU and the refresh request from the timer. A memory refresh method characterized by: