JPH04131947U - Package cage for storing semiconductor elements - Google Patents
Package cage for storing semiconductor elementsInfo
- Publication number
- JPH04131947U JPH04131947U JP3842291U JP3842291U JPH04131947U JP H04131947 U JPH04131947 U JP H04131947U JP 3842291 U JP3842291 U JP 3842291U JP 3842291 U JP3842291 U JP 3842291U JP H04131947 U JPH04131947 U JP H04131947U
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- semiconductor element
- recess
- insulating base
- weight
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Die Bonding (AREA)
Abstract
(57)【要約】
【目的】パッケージの絶縁基体に設けた凹部内に半導体
素子を安定、且つ強固に取着固定することができる半導
体素子収納用パッケージを提供することにある。
【構成】パッケージの容器を構成する絶縁基体１に設け
た凹部１ａ底面に銀に銅を0.3 乃至1.0 重量％、白金を
0.2 重量％以上含有させて成る金属層４を層着させた。
金属層４を絶縁基体１の凹部１ａ底面に層着させる際、
金属層４と絶縁基体１との界面に酸化銅とアルミナのス
ピネル構造の反応層が形成されて金属層４の層着強度が
強固となり、また金属層４表面に酸化物膜が形成される
のが皆無となって金属層４上に半導体素子３を強固に取
着することもできる。
(57) [Summary] [Objective] It is an object of the present invention to provide a package for storing a semiconductor element, in which a semiconductor element can be stably and firmly attached and fixed in a recess provided in an insulating base of the package. [Structure] 0.3 to 1.0% by weight of copper and platinum are added to the bottom of the recess 1a provided in the insulating base 1 constituting the container of the package.
A metal layer 4 containing 0.2% by weight or more was deposited.
When depositing the metal layer 4 on the bottom surface of the recess 1a of the insulating base 1,
A reaction layer with a spinel structure of copper oxide and alumina is formed at the interface between the metal layer 4 and the insulating substrate 1, thereby increasing the adhesion strength of the metal layer 4, and an oxide film is formed on the surface of the metal layer 4. It is also possible to firmly attach the semiconductor element 3 onto the metal layer 4 without any interference.
Description
【０００１】0001
本考案は半導体素子を収容するための半導体素子収納用パッケージの改良に関 するものである。 This invention relates to the improvement of a semiconductor device storage package for accommodating semiconductor devices. It is something to do.
【０００２】0002
従来、半導体素子、特にＬＳＩ等の半導体集積回路素子を収容するための半導 体素子収納用パッケージはアルミナセラミックス等の電気絶縁材料から成り、中 央部に半導体素子を収容する空所を形成するための凹部を有し、上面に封止用の 低融点ガラス層が被着された絶縁基体と、同じくアルミナセラミックス等の電気 絶縁材料から成り、中央部に半導体素子を収容する空所を形成するための凹部を 有し、下面に封止用の低融点ガラス層が被着された蓋体と、内部に収容する半導 体素子を外部の電気回路に電気的に接続するための外部リード端子とから構成さ れており、絶縁基体の上面に外部リード端子を載置させるとともに予め被着させ ておいた封止用の低融点ガラス層を溶融させることによって外部リード端子を絶 縁基体に仮止めし、次に前記絶縁基体の凹部底面に予め層着させておいた金属層 に接着材を介して半導体素子を取着するとともに該半導体素子の各電極をボンデ ィングワイヤを介して外部リード端子に接続し、しかる後、絶縁基体と蓋体とを その相対向する各々の主面に被着させておいた封止用の低融点ガラス層を溶融一 体化させ、絶縁基体と蓋体とから成る容器を気密に封止することによって製品と しての半導体装置となる。 Conventionally, semiconductors for accommodating semiconductor elements, especially semiconductor integrated circuit elements such as LSI The package for housing the body element is made of electrically insulating material such as alumina ceramics, and It has a recessed part in the center to form a cavity for accommodating the semiconductor element, and a sealing part on the top surface. An insulating substrate coated with a low melting point glass layer and an electrically conductive material such as alumina ceramics. It is made of insulating material and has a recess in the center to form a cavity for accommodating the semiconductor element. It has a lid body with a low melting point glass layer for sealing on the bottom surface, and a semiconductor housed inside. It consists of an external lead terminal for electrically connecting the body element to an external electrical circuit. The external lead terminals are placed on the top surface of the insulating base and are pre-attached. The external lead terminals are disconnected by melting the low melting point glass layer for sealing. A metal layer is temporarily attached to the edge base and then deposited on the bottom of the recess of the insulating base in advance. A semiconductor element is attached to the semiconductor element through an adhesive, and each electrode of the semiconductor element is bonded to the semiconductor element. Connect to the external lead terminal via the lead wire, and then connect the insulating base and the lid. A low melting point glass layer for sealing that has been applied to each of the opposing main surfaces is melted and unified. The product is sealed by airtightly sealing the container consisting of an insulating base and a lid. It becomes a semiconductor device.
【０００３】 尚、前記絶縁基体の凹部底面に層着させた金属層は平均粒径1.0 乃至3.0 μm の銀粉末に適当な有機溶剤、溶媒を添加混合して成る導電ペーストを絶縁基体の 凹部底面に滴下し、約10〜15μm の均一厚みに拡散させた後、約900 ℃の温度で 焼成することによって絶縁基体の凹部底面に層着される。0003 The metal layer deposited on the bottom of the recess of the insulating substrate has an average grain size of 1.0 to 3.0 μm. A conductive paste made by adding and mixing a suitable organic solvent and solvent to silver powder is applied to an insulating substrate. Drop it onto the bottom of the recess, spread it to a uniform thickness of about 10 to 15 μm, and then heat it at a temperature of about 900 °C. By firing, the layer is deposited on the bottom surface of the recess of the insulating substrate.
【０００４】 また前記半導体素子を金属層上に取着する接着材は金たは金 シリコン共晶半 田等の薄板から成り、該接着材を絶縁基体に設けた凹部底面の金属層と半導体素 子との間に介在させ、しかる後、これを加熱溶融させることによって半導体素子 を絶縁基体の凹部底面に取着する。0004 The adhesive for attaching the semiconductor element to the metal layer is gold, gold, silicon eutectic semi-conductor, etc. The metal layer on the bottom of the recess and the semiconductor element are The semiconductor element is then interposed between the semiconductor element and the semiconductor element, and then heated and melted. Attach it to the bottom of the recess of the insulating base.
【０００５】[0005]
しかしながら、この従来の半導体素子収納用パッケージにおいては、絶縁基体 の凹部底面に層着される金属層が銀から成り、該銀は酸化され易い金属であるこ とから絶縁基体の凹部底面に金属層を層着させた場合、該金属層にはその表面に 極めて短時間に酸化物膜が形成されてしまい、一旦、表面に酸化物膜が形成され ると金属層上に半導体素子を金たは金 シリコン共晶半田等から成る接着材を介 して取着する際、接着材の金属層に対する接合強度が金属層表面の酸化物膜によ って極めて弱いものとなり、その結果、半導体素子に外力が印加されると該外力 によって半導体素子が金属層より極めて容易に外れてしまうという欠点を有して いた。 However, in this conventional package for storing semiconductor elements, the insulating base The metal layer deposited on the bottom of the recess is made of silver, and silver is a metal that is easily oxidized. When a metal layer is deposited on the bottom of the recess of an insulating substrate, the metal layer has a An oxide film is formed in an extremely short period of time, and once an oxide film is formed on the surface. Then, the semiconductor element is placed on the metal layer using an adhesive made of gold or gold-silicon eutectic solder. When attaching the adhesive to the metal layer, the bonding strength of the adhesive to the metal layer is affected by the oxide film on the surface of the metal layer. As a result, when an external force is applied to a semiconductor element, the external force It has the disadvantage that the semiconductor element is extremely easily separated from the metal layer due to the there was.
【０００６】 また前記銀から成る金属層は絶縁基体の凹部底面に焼き付けによって層着され ているものの銀と絶縁基体とは反応性が弱いため両者の接合強度は極めて弱く、 その結果、金属層上に半導体素子を接着材を加熱溶融させることによって取着す る際、半導体素子の形状が大型化し、接着材の量が多くなると該接着材による引 っ張り力によって金属層が半導体素子とともに絶縁基体より剥離してしまうとい う欠点も有していた。[0006] Further, the metal layer made of silver is deposited on the bottom surface of the recess of the insulating substrate by baking. However, since the reactivity between silver and the insulating substrate is weak, the bonding strength between the two is extremely weak. As a result, the semiconductor element can be attached onto the metal layer by heating and melting the adhesive. As the size of the semiconductor element increases and the amount of adhesive increases, the stress caused by the adhesive increases. It is said that the metal layer peels off from the insulating substrate along with the semiconductor element due to tensile force. It also had some drawbacks.
【０００７】[0007]
本考案は半導体素子を収容するための凹部を有する絶縁基体と蓋体とから成る 半導体素子収納用パッケージにおいて、前記絶縁基体の凹部底面に、銀に銅を0. 3 乃至1.0 重量％、白金を0.2 重量％以上含有させて成る金属層を層着させたこ とを特徴とするものである。 The present invention consists of an insulating base having a recess for accommodating a semiconductor element and a lid. In the package for storing semiconductor elements, the bottom surface of the recess of the insulating substrate is coated with silver and copper. 3 to 1.0% by weight and a metal layer containing 0.2% by weight or more of platinum is deposited. It is characterized by the following.
【０００８】[0008]
【実施例】 次に本考案を添付図面に基づき詳細に説明する。 図1 は本考案の半導体素子収納用パッケージの一実施例を示し、1 はアルミナ セラミックス等の電気絶縁材料から成る絶縁基体、2 は同じく電気絶縁材料から 成る蓋体である。この絶縁基体1 と蓋体2 とで半導体素子3 を収容する容器が構 成される。【Example】 Next, the present invention will be explained in detail based on the accompanying drawings. Figure 1 shows an example of the semiconductor device storage package of the present invention. The insulating base is made of an electrically insulating material such as ceramics, and 2 is also made of an electrically insulating material. This is the lid body. The insulating base 1 and the lid 2 constitute a container that accommodates the semiconductor element 3. will be accomplished.
【０００９】 前記絶縁基体1 及び蓋体2 にはそれぞれの中央部に半導体素子3 を収容する空 所を形成するための凹部が設けてあり、絶縁基体1 の凹部1a底面には金属層4 が 層着されている。[0009] The insulating base body 1 and the lid body 2 each have a cavity in the center thereof for accommodating a semiconductor element 3. A metal layer 4 is provided on the bottom surface of the recess 1a of the insulating substrate 1. Layered.
【００１０】 前記絶縁基体1 及び蓋体2 は従来周知のプレス成形法を採用することによって 形成され、例えば絶縁基体1 及び蓋体2 がアルミナセラミックスから成る場合に は図1 に示すような絶縁基体1 または蓋体2 に対応した形状を有するプス型内に アルミナセラミックスの原料粉末を充填させるとともに一定圧力を印加して成形 し、しかる後、成形品を約1500℃の温度で焼成することによって製作される。0010 The insulating base 1 and the lid 2 are formed by employing a conventionally well-known press molding method. For example, when the insulating base 1 and the lid 2 are made of alumina ceramics, is placed in a pushpiece mold having a shape corresponding to the insulating base 1 or lid 2 as shown in Figure 1. Filling with raw material powder of alumina ceramics and applying constant pressure to form. After that, the molded product is fired at a temperature of about 1500°C.
【００１１】 また前記絶縁基体1 の凹部1a底面に層着させた金属層4 は、銀に銅を0.3 乃至 1.0 重量％、白金を0.2 重量％以上含有させた金属から成り、該金属層4 は半導 体素子3 を絶縁基体1 の凹部1a底面に取着する際の下地金属として作用し、金属 層4 上には半導体素子3 が金、金 シリコン共晶半田等の接着材5 を介し取着さ れる。[0011] Further, the metal layer 4 deposited on the bottom surface of the recess 1a of the insulating substrate 1 has a thickness of 0.3 to 0.3 to 0.3 mm. The metal layer 4 is made of a metal containing 1.0% by weight of platinum and 0.2% by weight or more of platinum. Acts as a base metal when attaching the body element 3 to the bottom surface of the recess 1a of the insulating base 1. A semiconductor element 3 is attached onto the layer 4 via an adhesive 5 such as gold, gold-silicon eutectic solder, etc. It will be done.
【００１２】 前記金属層4 は銀粉末に銅粉末を0.3 乃至1.0 重量％、白金を0.2 重量％以上 添加し、更にこれらに有機溶剤、溶媒を添加混合して導電ペーストを得るととも に該導電ペーストを絶縁基体1 の凹部1a底面に滴下させ、約25μm 以上の均一厚 みに拡散させた後、約950 ℃の高い温度で焼成することよって絶縁基体1 の凹部 1a底面に被着される。0012 The metal layer 4 contains silver powder, 0.3 to 1.0% by weight of copper powder, and 0.2% by weight or more of platinum. and then add and mix organic solvents and solvents to obtain conductive paste. Then, drop the conductive paste onto the bottom surface of the recess 1a of the insulating substrate 1 to a uniform thickness of about 25 μm or more. After the insulating substrate 1 is diffused, it is baked at a high temperature of approximately 950°C to form the recesses in the insulating substrate 1. It is attached to the bottom of 1a.
【００１３】 前記金属層4 はその内部に銅が0.3 乃至1.0 重量％含有されていることから絶 縁基体1 の凹部1a底面に導電ペーストを滴下するとともに高温で焼成して金属層 4 を層着させる際、絶縁基体1 の凹部1a底面と金属層4 の界面には酸化銅とアル ミナのスピネル構造の反応層が形成されることとなって金属層4 の絶縁基体1 に 対する層着強度が極めて強固なものとなる。そのため金属層4 上に半導体素子3 を接着材5 を加熱溶融させることによって取着する場合、半導体素子3 の形状が 大型化し、接着材5 の量が多くなって該接着材5 による金属層4 の引っ張り力が 大きなものになったとしても金属層4 は半導体素子3 とともに絶縁基体1 より剥 離することは皆無となり、半導体素子3 を絶縁基体1 の凹部1a底面に強固に取着 させておくことが可能となる。[0013] The metal layer 4 contains 0.3 to 1.0% by weight of copper, so it is completely A conductive paste is dropped onto the bottom of the recess 1a of the edge base 1 and fired at a high temperature to form a metal layer. 4, copper oxide and aluminum are added to the interface between the bottom surface of the recess 1a of the insulating substrate 1 and the metal layer 4. A reaction layer with a spinel structure of Mina is formed on the insulating substrate 1 of the metal layer 4. The adhesion strength of the layers is extremely strong. Therefore, the semiconductor element 3 is placed on the metal layer 4. When attaching by heating and melting the adhesive 5, the shape of the semiconductor element 3 is As the size increases, the amount of adhesive 5 increases, and the tensile force of the metal layer 4 due to the adhesive 5 increases. Even if the metal layer 4 becomes large, the metal layer 4 can be peeled off from the insulating substrate 1 together with the semiconductor element 3. There is no separation, and the semiconductor element 3 is firmly attached to the bottom of the recess 1a of the insulating substrate 1. It becomes possible to leave it as is.
【００１４】 尚、前記金属層4 に含有させる銅はその含有量が0.3 重量％未満であると金属 層4 と絶縁基体1 の凹部1a底面との界面に形成される反応層( 酸化銅とアルミナ のスピネル構造の反応層) の量が少なくなって金属層4 を絶縁基体1 の凹部1a底 面に強固に層着することができなくなり、また銅の含有量が1.0 重量％を越える と金属層4 の表面に銅が析出して金属層4 上に半導体素子3 を強固に取着できな くなる。従って、金属層4 に含有させる銅はその含有量が0.3 乃至1.0 重量％の 範囲に特定される。[0014] It should be noted that if the content of copper contained in the metal layer 4 is less than 0.3% by weight, it will become a metal. A reaction layer (copper oxide and alumina) formed at the interface between layer 4 and the bottom of recess 1a of insulating substrate 1 The amount of the spinel-structured reaction layer) is reduced and the metal layer 4 is deposited on the bottom of the recess 1a of the insulating substrate 1. It becomes impossible to firmly adhere to the surface, and the copper content exceeds 1.0% by weight. When copper is deposited on the surface of the metal layer 4, the semiconductor element 3 cannot be firmly attached on the metal layer 4. It becomes. Therefore, the copper contained in the metal layer 4 has a content of 0.3 to 1.0% by weight. Specific to a range.
【００１５】 また前記金属層4 には白金が0.2 重量％以上含有されており、該白金は金属層 4 の表面が酸化されるのを有効に防止する作用を為す。[0015] Further, the metal layer 4 contains platinum in an amount of 0.2% by weight or more. It acts to effectively prevent the surface of No. 4 from being oxidized.
【００１６】 前記白金を含有する金属層4 はその白金の作用によって表面に酸化物膜が形成 されることは殆どなく、その結果、金属層4 上に半導体素子3 を接着材5 を加熱 溶融させることによって取着する際、金属層4 と接着層5 とを接合強度を大とし て接合させることができ、半導体素子3 を金属層4 上に強固に取着することが可 能となる。[0016] An oxide film is formed on the surface of the metal layer 4 containing platinum due to the action of the platinum. As a result, the semiconductor element 3 is placed on the metal layer 4 and the adhesive 5 is heated. When attaching by melting, the bonding strength between the metal layer 4 and the adhesive layer 5 is increased. The semiconductor element 3 can be firmly attached to the metal layer 4. Becomes Noh.
【００１７】 尚、前記金属層4 に含有させる白金はその含有量が0.2 重量％未満であると金 属層4 の表面に短時間に酸化物膜が形成されて金属層4 上に半導体素子3 を強固 に取着できなくなる。従って、前記金属層4 に含有される白金はその含有量が0. 2 重量％以上に特定され、製品のコストを考慮すると0.2 〜2.0 重量％の範囲と するのが良い。[0017] It should be noted that if the platinum content in the metal layer 4 is less than 0.2% by weight, the metal layer 4 will contain platinum. An oxide film is formed on the surface of the metal layer 4 in a short time, solidifying the semiconductor element 3 on the metal layer 4. It will not be possible to attach it to the Therefore, the content of platinum contained in the metal layer 4 is 0. 2% by weight or more, and considering the cost of the product, it should be in the range of 0.2 to 2.0% by weight. It's good to do that.
【００１８】 また前記金属層4 に含有される銅及び白金はその粒径を銀の粒径に対し10〜30 % 程度としておくと、銅及び白金が銀の粉末粒子間に均等に分散し、その結果、 金属層4 を絶縁基体1 の凹部1a底面により強固に層着させることができるととも に金属層4 表面に酸化物膜が形成されるのをより有効に防止することができる。[0018] Further, the particle size of copper and platinum contained in the metal layer 4 is 10 to 30 times larger than that of silver. %, copper and platinum are evenly dispersed between the silver powder particles, and as a result, The metal layer 4 can be more firmly attached to the bottom surface of the recess 1a of the insulating base 1. The formation of an oxide film on the surface of the metal layer 4 can be more effectively prevented.
【００１９】 更に前記金属層4 は取着する半導体素子3 の寸法が6.0mm ×8.0mm 程度の大き なものと成って絶縁基体1 に設けた凹部1aの底面積が80mm2 以上となったときそ の厚みを25μm 以上の厚いものとしておくと半導体素子3 を絶縁基体1 の凹部1a 底面に被着させた金属層4 上に接着材5 を介して取着する際、金属層4 が半導体 素子3 と絶縁基体1 との熱膨張係数の相違に起因して発生する熱応力を該金属層 4 が変形することによって吸収し、半導体素子3 に半導体素子3 と絶縁基体1 と の間に発生する熱応力によってクラックや割れ等が生じるのを有効に防止するこ ともできる。従って、金属層4 は取着する半導体素子3 の寸法が6.0mm ×8.0mm 程度の大きなものと成って絶縁基体1 に設けた凹部1aの底面積が80mm2 以上とな ったときその厚みを25μm 以上の厚いものとしておくことが好ましい。Furthermore, the metal layer 4 is used when the semiconductor element 3 to be attached has a large dimension of about 6.0 mm x 8.0 mm and the bottom area of the recess 1a provided in the insulating substrate 1 is 80 mm 2 or more. If the thickness is set to be 25 μm or more, when the semiconductor element 3 is attached via the adhesive 5 onto the metal layer 4 adhered to the bottom surface of the recess 1a of the insulating substrate 1, the metal layer 4 will be attached to the semiconductor element 3. The metal layer 4 deforms and absorbs the thermal stress generated due to the difference in thermal expansion coefficient with the insulating substrate 1, and the thermal stress generated between the semiconductor element 3 and the insulating substrate 1 is absorbed in the semiconductor element 3. It is also possible to effectively prevent cracks, cracks, etc. from occurring. Therefore, when the semiconductor element 3 to be attached has a large dimension of about 6.0 mm x 8.0 mm and the bottom area of the recess 1a provided in the insulating base 1 is 80 mm 2 or more, the metal layer 4 has a thickness of 25 μm. It is preferable to use a thicker one.
【００２０】 また更に前記金属層4 はそれを構成する銀の結晶粒径を焼成温度を約950 ℃の 若干高めとすることによって7.0 乃至14.0μm の大きさとすると銀結晶間の間隙 が少なくなるとともに金属層4 の表面粗さが中心線平均粗さRaでRa=0.55 μm 程 度の滑らかなものとなり、その結果、金属層4 上に接着材5 を介して半導体素子 3 を取着する際、接着材5 の金属層4 上での拡がりが極めて良くなり、半導体素 子3 を金属層4 に極めて強固に取着することが可能となる。従って、金属層4 は それを構成する銀の結晶粒径を7.0 乃至14.0μm の大きさとしておくことが好ま しい。[0020] Furthermore, the metal layer 4 is heated at a firing temperature of about 950°C to change the crystal grain size of the silver constituting it. If the size is set to 7.0 to 14.0μm by making it slightly higher, the gap between silver crystals will increase. As the surface roughness of the metal layer 4 decreases, the center line average roughness Ra becomes approximately 0.55 μm. As a result, the semiconductor element is placed on the metal layer 4 through the adhesive 5. 3, the adhesive 5 spreads extremely well on the metal layer 4, and the semiconductor element It becomes possible to attach the element 3 to the metal layer 4 extremely firmly. Therefore, metal layer 4 is It is preferable that the crystal grain size of the silver constituting it is 7.0 to 14.0 μm. Yes.
【００２１】 前記絶縁基体1 及び蓋体2 にはまたその相対向する各々の主面に封止用の低融 点ガラス層6a、6bが予め被着形成されており、該絶縁基体1 及び蓋体2 の各々に 被着されている封止用の低融点ガラス層6a、6bを加熱溶融させ、一体化させるこ とにより絶縁基体1 と蓋体2 とから成る容器内部に半導体素子3 を気密に封止す る。 前記絶縁基体1 及び蓋体2 の相対向する主面に被着される封止用の低融点ガラ ス層6a、6bは、例えば酸化鉛75.0重量％、酸化チタン9.0 重量％、酸化ホウ素7. 5 重量％、酸化亜鉛2.0 重量％等のガラスから成り、該ガラス粉末に適当な有機 溶剤、溶媒を添加混合して得たガラスペーストを従来周知のスクリーン印刷等の 厚膜手法を採用することにより絶縁基体1 及び蓋体2 の相対向する各々の主面に 被着される。[0021] The insulating base 1 and the lid 2 also have a low melting temperature for sealing on their respective opposing main surfaces. Point glass layers 6a and 6b are formed in advance on each of the insulating base 1 and the lid 2. The applied low melting point glass layers 6a and 6b for sealing are heated and melted to integrate them. The semiconductor element 3 is hermetically sealed inside the container consisting of the insulating substrate 1 and the lid 2. Ru. A low melting point glass for sealing is adhered to the opposing main surfaces of the insulating base 1 and the lid 2. The base layers 6a and 6b contain, for example, 75.0% by weight of lead oxide, 9.0% by weight of titanium oxide, and 7.0% by weight of boron oxide. 5% by weight of glass, 2.0% by weight of zinc oxide, etc., and the glass powder contains a suitable organic material. The glass paste obtained by adding and mixing solvents and solvents is processed using conventional methods such as screen printing. By adopting a thick film method, the main surfaces of the insulating base 1 and the lid 2 are coated on each opposing main surface. be coated.
【００２２】 尚、前記封止用の低融点ガラス層6a、6bはその熱膨張係数を絶縁基体1 及び蓋 体2 の熱膨張係数に近似した値にしておくと絶縁基体1 と蓋体2 とを封止用低融 点ガラス層6a、6bを介して接合し、容器を気密に封止する際、絶縁基体1 及び蓋 体2 と封止用低融点ガラス層6a、6bとの間には両者の熱膨張係数の相違に起因す る熱応力が発生することは殆どなく、絶縁基体1 と蓋体2 とを封止用低融点ガラ ス層6a、6bを介し強固に接合することが可能となる。従って、封止用低融点ガラ ス層6a、6bはその熱膨張係数を絶縁基体1 及び蓋体2 の熱膨張係数に合わせてお くことが好ましい。[0022] Note that the low melting point glass layers 6a and 6b for sealing have their thermal expansion coefficients equal to those of the insulating base 1 and the lid. By setting the thermal expansion coefficient to a value close to that of the body 2, it is possible to seal the insulating base 1 and the lid body 2 with a low melting temperature. The insulating substrate 1 and the lid are bonded together via the point glass layers 6a and 6b to airtightly seal the container. There is a gap between the body 2 and the low melting point glass layers 6a and 6b for sealing due to the difference in their thermal expansion coefficients. Almost no thermal stress is generated, and the insulating base 1 and lid 2 are sealed using low melting point glass. This makes it possible to firmly bond them through the base layers 6a and 6b. Therefore, low melting point glass for sealing The thermal expansion coefficients of the base layers 6a and 6b are adjusted to match those of the insulating base 1 and the lid 2. It is preferable that
【００２３】 また前記絶縁基体1 と蓋体2 との間には導電性材料、例えばコバール(Fe-Ni-C 合金) や42アロイ(Fe-Ni合金) 等の金属から成る外部リード端子7 が配されてお り、該外部リード端子7 は半導体素子3 の各電極がボンディングワイヤ8 を介し て電気的に接続され、外部リード端子7 を外部電気回路に接続することによって 半導体素子3 は外部電気回路と接続されることとなる。[0023] Further, a conductive material such as Kovar (Fe-Ni-C An external lead terminal 7 made of metal such as alloy) or 42 alloy (Fe-Ni alloy) is arranged. The external lead terminals 7 are connected to each electrode of the semiconductor element 3 via bonding wires 8. by connecting the external lead terminal 7 to the external electrical circuit. The semiconductor element 3 will be connected to an external electric circuit.
【００２４】 前記外部リード端子7 は、絶縁基体1 と蓋体2 とから成る容器を封止用の低融 点ガラス層6a、6bを溶融一体化させて気密封止する際に同時に絶縁基体1 と蓋体 2 の間に取着固定される。[0024] The external lead terminal 7 is a low melting point for sealing a container consisting of an insulating base 1 and a lid 2. When melting and integrating the point glass layers 6a and 6b and hermetically sealing, the insulating base 1 and the lid are simultaneously melted and sealed. It is fixed between the two.
【００２５】 尚、前記外部リード端子7 は外部電気回路との電気的導通を良好とするために 、また酸化腐食するのを有効に防止するためにその外表面にニッケル、金等の良 導電性で、且つ耐蝕性に優れた金属を1.0 乃至20.0μm の厚みにメッキにより層 着させておくことが好ましい。[0025] Note that the external lead terminal 7 is designed to ensure good electrical continuity with the external electrical circuit. Also, in order to effectively prevent oxidation corrosion, the outer surface is coated with a good material such as nickel or gold. A layer of conductive and corrosion-resistant metal is plated to a thickness of 1.0 to 20.0 μm. It is preferable to wear them.
【００２６】 かくしてこの半導体素子収納用パッケージによれば、絶縁基体1 に設けた凹部 1a底面の金属層4 上に金、金 シリコン共晶半田等から成る接着材5 を介して半 導体素子3 を取着固定するとともに該半導体素子3 の各電極をボンディングワイ ヤ8 により外部リード端子7 に接続させ、しかる後、絶縁基体1 と蓋体2 とをそ の両者の相対向する主面に予め被着させておいた封止用低融点ガラス層6a、6bを 溶融一体化させることによって接合すると絶縁基体と蓋体とから成る容器内部に 半導体素子3 が気密に封止されて最終製品としての半導体装置となる。[0026] Thus, according to this package for storing semiconductor elements, the recess provided in the insulating base 1 The metal layer 4 on the bottom of 1a is covered with an adhesive 5 made of gold, gold silicon eutectic solder, etc. Attach and fix the conductive element 3 and connect each electrode of the semiconductor element 3 with bonding wires. Connect the insulating base 1 and the lid 2 to the external lead terminal 7 using the wire 8. The low melting point glass layers 6a and 6b for sealing are applied in advance to the opposing main surfaces of the two. When joined by melting and integrating, the inside of the container consisting of an insulating base and a lid is The semiconductor element 3 is hermetically sealed to form a semiconductor device as a final product.
【００２７】 尚、本考案は上述の実施例に限定されるものではなく、本考案の要旨を逸脱し ない範囲であれば種々の変更は可能であり、例えば低融点ガラスによって絶縁基 体と蓋体とから成る容器を気密封止するガラス封止型の半導体素子収納用パッケ ージの他に複数枚の未焼成セラミックシートを積層し、焼結一体化させて成るマ ルチレイヤーの半導体素子収納用パッケージにも適用可能である。[0027] The present invention is not limited to the above-mentioned embodiments, and there may be no deviation from the gist of the present invention. Various changes are possible as long as the A glass-sealed package for storing semiconductor devices that hermetically seals a container consisting of a body and a lid. This product is made by laminating multiple unfired ceramic sheets in addition to the ceramic sheet and sintering them into one piece. It is also applicable to multi-layer semiconductor element storage packages.
【００２８】[0028]
本考案の半導体素子収納用パッケージによれば、パッケージの容器を構成する 絶縁基体の凹部底面に銀に銅を0.3 乃至1.0 重量％、白金を0.2 重量％以上含有 させて成る金属層を層着させたことから金属層を絶縁基体の凹部底面に層着させ る際その層着の強度を極めて強固とするとともに金属層表面に酸化物膜が形成さ れるのを有効に防止して金属層上に半導体素子を極めて強固に取着することが可 能となる。 According to the semiconductor device storage package of the present invention, the container of the package Silver contains 0.3 to 1.0% by weight of copper and 0.2% by weight or more of platinum on the bottom of the recess of the insulating substrate. The metal layer is deposited on the bottom of the recess of the insulating substrate. When bonding, the strength of the layer is extremely strong and an oxide film is formed on the surface of the metal layer. It is possible to attach semiconductor elements extremely firmly to metal layers by effectively preventing Becomes Noh.
【図１】本考案の半導体素子収納用パッケージの一実施
例を示す断面図である。FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor device storage package of the present invention.
１・・・絶縁基体 １ａ・・凹部 ２・・・蓋体 ３・・・半導体素子 ４・・・金属層 ５・・・接着材 ７・・・外部リード端子 1... Insulating base 1a... recessed part 2... Lid body 3...Semiconductor element 4...metal layer 5...Adhesive material 7...External lead terminal
Claims (1)
絶縁基体と蓋体とから成る半導体素子収納用パッケージ
において、前記絶縁基体の凹部底面に、銀に銅を0.3 乃
至1.0 重量％、白金を0.2 重量％以上含有させて成る金
属層を層着させたことを特徴とする半導体素子収納用パ
ッケージ。1. A semiconductor device storage package comprising an insulating base and a lid having a recess for accommodating a semiconductor device, wherein the bottom of the recess of the insulating base is coated with silver, 0.3 to 1.0% by weight of copper, and platinum. A package for storing semiconductor elements, characterized by having a metal layer containing 0.2% by weight or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1991038422U JP2538845Y2 (en) | 1991-05-28 | 1991-05-28 | Package for storing semiconductor elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1991038422U JP2538845Y2 (en) | 1991-05-28 | 1991-05-28 | Package for storing semiconductor elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04131947U true JPH04131947U (en) | 1992-12-04 |
| JP2538845Y2 JP2538845Y2 (en) | 1997-06-18 |
Family
ID=31919931
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1991038422U Expired - Fee Related JP2538845Y2 (en) | 1991-05-28 | 1991-05-28 | Package for storing semiconductor elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2538845Y2 (en) |
-
1991
- 1991-05-28 JP JP1991038422U patent/JP2538845Y2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2538845Y2 (en) | 1997-06-18 |
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