JPH04129091A - Non-volatile semiconductor memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] Industrial Application Field] The present invention relates to a non-volatile semiconductor memory device, particularly an electrically erasable EEPROM. 1 is a circuit diagram showing the basic configuration of a semiconductor memory device. One memory cell is composed of one transistor and one memory transistor. In the figure, (1) is a transistor, (2) is a memory transistor, (3) is a word line in the row direction, (4) is a bit line in the column direction, (5) is a control gate line, and (6) is a diode line.
0f+Il, (7) is a current sense amplifier, and (8) is a Y gate line. The drain of transistor (1) Ql is connected to the bit line (4) BLIK, the gate is connected to the word line (3) WL, and the north is connected to the drain of memory transistor 7 (23M1).Transistor ( 1) The drain of Q2 is the bit line (4) B L 2
The gate is connected to the word line (3) WL, and the north is connected to the drain of the memory transistor (21M2).
The control gates are commonly control gates 1-M.
(5) CGLK is connected, and the sources are commonly connected to transistor H (
1) Connected to the drain of Q3. Transistor (
1) The gate of Q3 is connected to the north line selection signal BLK, and the north terminal is grounded. Transistor (11Q 4C)
1' line is connected to the 10 line (6), connected to the 1' line (6), connected to the 1' line (8), and the source is connected to the bit line (4).
) Connected to BL1. Transistor <1) Q
The drain of 5 is connected to Ilo M (6), the gate is connected to Y gate line (8) Y 2, and the source is connected to Pi)m(41BL2., T/○i$ (6)
5 is connected to the current sense amplifier (7). The current sense amplifier (7) detects the Deinutarp (electrons accumulated in the floating gate are slightly removed due to the potential of the bit line (4)) during readout. To suppress this, the potential of bit M (4) is kept at IV or 1.5V, and it is detected whether or not current flows through the bit line (4) and I10 line (6).The operation will be explained first. I will explain about it. Memory transistor (
2) Consider the case of writing '1' to M1 and writing '0' to M2 (in the memory transistor) There are two types of writing: erasing and programming. First, erasing is performed. In erasing, the source line selection signal SL is becomes 'R' and the north of memory transistor (2) M1, V2 is grounded. Word line (3) WL and control gate line (5) CG L become high voltage, bit line (4) BL
I, BL2 becomes ++ L ++. As a result, electrons are injected into the 70-channel gates of memory transistors (2) M1 and M2, and the threshold voltage increases. This state corresponds to '1'.

Next, the program is performed. In the program, the source line selection signal SL becomes "L" and the memory transistor (2)
The sources of M1 and M2 are left floating. Word line (:3) W L and bit line (4) B I, 2 become high voltage, control gate line (5) CG L
and bit line (4) B x, 1 ? becomes i″L″.

As a result, electrons are extracted from the floating gate of the memory transistor (2) M2, and the threshold value is lowered.

This state corresponds to "0".

Next, reading will be explained. Memory transistor (
2) Consider the case of reading from M1. In reading, the source line selection signal SL becomes 1H', and the booths of the memory transistors (2) M1 and M2 are grounded. Y gate line (8) Y 1 becomes H'', Y gate line (8) Y 2 becomes s L 11. Word line (3)
WL becomes “H” and control gate line (5) CG
L is a potential intermediate between the threshold value when the data written in the memory transistor (2) is "1" and 0°. If "1" is written in the memory transistor (2) Ml, it remains off and the bit line (4) BLII1
No current flows through the 0 wire (6). Memory transistor (
2) When "0" is written in Ml, it turns on and current flows through the bit line (4) and the B L 1 and I10 lines (6).

Reading is performed by sensing these with a current sense amplifier (7).

"Problems to be Solved by the Invention" Conventional non-volatile semiconductor memory devices are configured as described above, so when cell current decreases as the degree of integration increases, a current sense amplifier is used to increase the cell current, resulting in readout. In addition, the current sense amplifier has a power supply voltage margin of about 3V to 77V, making it difficult to perform low voltage operation (for example, 1.5V).'\ Considering installation in a belt device, 1.5V operation is required.

This invention was made in order to solve the above-mentioned problems, and provides a non-volatile semiconductor memory device that operates at 1.5"(91' battery voltage) and can perform high-speed reading. With the goal.

[Means for Solving the Problems J] In the nonvolatile semiconductor memory device according to the present invention, bit lines are paired and sense amplifiers are provided at both ends of the bit lines.

[Operation] The nonvolatile semiconductor memory device according to the present invention performs differential sensing using the potential of one bit line of a bit line pair as a reference level.

(Example) Hereinafter, an example of the present invention will be explained with reference to the drawings.
The figure is a circuit diagram showing the basic configuration of a nonvolatile semiconductor memory device.
2 and 3 are timing diagrams showing signal waveforms at various parts during reading of the nonvolatile semiconductor memory device of FIG. 1. FIG.

One memory cell is composed of one transistor and one memory transistor, as in the prior art. In the figure, (1) to (5) are the same as those shown in the conventional example of FIG. 4, and therefore their explanation will be omitted. (9) is the sense node, the transistor (1) Q 1 -V in is connected to the bit line (4) B L 1, the gate is connected to the word line (3) W L, and the north is the memory transistor (2) Connected to the drain of Ml. The drain of transistor (1) Q2 is bit line (4) B L 2
The memory transistor (2'l M
1. The control gate of M2 is common control gate J11! (5) connected to CGL, and the sheaths are commonly connected to the drains of transistors (1) Q and 3; The gate of transistor (1) Q3 is connected to source line selection signal SL, and the source is grounded. Transistor (
1) The drain of Q, 6 is the sense node (9) S
N11, the gate is connected to bit line selection signal BLT
Connected to 11.

The sheath is connected to bit line (4) BL1. The drain of transistor <1) Q, 7 is connected to the sense node (9) SN12, the gate is connected to the bit line selection signal BLT12, and the source is connected to the bit line (4) B
Usense node (9) connected to L2 S N 1
1 is commonly connected to the drains of transistors (1) Q8 and Q9, and transistors (1) Q, 10
, can be commonly connected to the gates of Qll. Sense node (
9) SN 12 is a transistor (1) 010,
It is commonly connected to the drain of transistors Qll, and also commonly connected to the gates of transistors (1) Q8 and Q9. The sheath of transistor (1) Q8QIO is the transistor (
1) Connected to the drain of Q12 and connected to the transistor (
1) The gate of Q12 is connected to the sense amplifier activation signal port, and the sheath is connected to the power supply voltage. Transistors (11Q, 9Q14 (7)
1) Connected to the drain of transistor (1) Q, 13, and the gate of transistor (1) Q, 13 is connected to the sense amplifier activation signal S.
1 and the sheath is grounded. Transistor (1
) Q8 to Q13 constitute a sense amplifier. Also,
Sense node (9'l S N 11 is a transistor (
1) Q14, Q16 1-nut transistor (1)
Q, connected to the drain of 17, sense node (9
) S N 12 is connected to the source of transistor (1) Q15 and the drain of transistor (1) Q 16. The gates of transistors (11Q 14 to Q16 are commonly connected to the equalize signal BLEQ, 1, and the drains of transistors (1) Q14 and Q15 are connected to the power supply voltage. The gates of transistors (1>Q17 are connected to the charge signal PRI, the sheath is connected to the power supply voltage - the drain of the transistor (1) Q18 is connected to the sense node (9) SN21, the gate is connected to the bit line selection signal BLT21,
The sheath is connected to the bit line (4) B L 1, the drain of the transistor (1) Q 19 is connected to the sense node (
9) 8 N 22, the gate is connected to the bit line selection signal BLT22, and the sheath is connected to the bit line (4) B
Sense node (9) connected to L2
21 is a transistor (1) commonly connected to the drains of Q20 and Q21, and a transistor (1)
Commonly connected to the gates of Q22 and Q23. Sense node (9) S N 22 is transistor (1) Q
It is commonly connected to the drains of transistors 22, Q, and 23, and also commonly connected to the gates of transistors (1) Q, 20, and Q21.
The source of transistor (1) Q22 is connected to the drain of transistor (1) Q24, the gate of transistor (1) Q24 is connected to sense amplifier activation signal S2, and the source of transistor (11Q) is connected to the power supply voltage. 21
, Q23 are connected to the drain of the transistor (1) Q25, the gate of the transistor (1) Q25 is connected to the sense amplifier activation signal S2, and the source is grounded. Transistor (1) Q 20 to Q,
25 constitutes a sense amplifier, and sense node (9) S N 21 Hatransinuta (1) Q26, Q
28 connected sense nodes (9) S N
22 is connected to the sheath of transistor (1) Q27 and the drains of transistors (1) Q28 and Q29.

The gates of the transistors (1) Q, 26 LQ28 are commonly connected to the equalization signal BLEQ2, and the drains of the transistors (1) Q, 26, Q, and 27 are connected to the power supply voltage. Transistor (1) Q 29
The gate of is connected to the precharge signal PR2, and the north thereof is connected to the power supply voltage.

Next, I will explain the operation.For writing, see the 4th section.
Since it is the same as that shown in the conventional example in the figure, the explanation will be omitted.Hereinafter, it will be explained with reference to FIG. The data of !il 1 is read by the upper sense amplifier composed of transistors (1) Q8 to Q13.When reading, the source line selection signal SL\i becomes “H” and the booth of memory transistors (2) Ml and N2 is read out. is grounded.

First, the equalize signal BLEQ, 1 and the bit line selection signals BLT 11, BLT 12 become H", and the bit lines (4) BLl, BL2 become (Vcc - Vth
is equalized. Next, equalize signal BLEQI
(! Nib recharge signal cylinder) becomes "L", and the bit line (41B L l is recharged by 1 to VQC. As a result, the potential of the sense node (9) S N 11 becomes V
cc, and the potential of the sense node (9) S N 12 becomes (Vcc - Vth). Next is the precharge signal port].

B", and the bit line selection signal BLT12 becomes "L". Word line (3I W L becomes "H", control gate line <5) CG L is a memory transistor (
2) The memory transistor (2) has an intermediate potential between threshold 1 when the data written in is “1” and “0°”.
) If "1" is written in Ml, it remains off and the potential of the sense node (9) S el 11 is 'QC
It remains C. If “0” is written in the memory transistor (2) Ml, it turns on and the bit line (4)
The charge accumulated in B L1 is discharged, and the potential of the sense node (9) S N1 falls to (Vcc -
After becoming lower than Vth), the bit line selection signal BLTII and the sense amplifier activation signal "T" become low, and the sense amplifier is activated. Reading is thereby performed. Here, bit line selection signal BLT11
By setting the value to 1", the capacitance of the sense node (9) S N 11.3N12 becomes uniform when the sense block is activated, and stable reading can be performed.

Similarly, memory transistor (2) M 2 G
The D y'-ta is read out by the lower sense amplifier composed of transistors (1) Q, 20 to Q25. Above, we have explained an example in which transistors (1) Q, 17 are used as a precharge transistor. , it can also be used as a load transistor. The timing diagram in that case will be as shown in FIG. 3. Hereinafter, explanation will be given with reference to FIG. 3. Consider the case where reading is performed from memory transistor (2) vl.

The data of the memory transistor (2) M1 is read by the upper sense amplifier composed of transistors (1) Q8 to Q13. In reading, the source line selection signal SL becomes "H" and the memory transistor (2)
It! 1, the north of w12 is grounded.

Then, the equalize signal B L FJQ, 1 and the pin line selection signal ELTII, BLT 12 become "H", and the bit lines (4) B L 1, BL2 become (Vcc - Vt
h). As a result, the potential of the sense node (9) S N11.5N12 becomes (Vcc -
Vtn).

Next, the equalize signal BLEQ, 1 and the precharge signal ["1 and the bit line selection signal BLT12 are "L"]
become. The word line (3) WL becomes "H", and the control gate line f5) CGL is the potential between the thresholds when the data written in the memory transistor (2) is "L" and "O". memory transistor (
2) When "1" is written in Vl, it remains off and the potential of the sense node (9) S N 11 is charged to VCC by the transistor (1) Q 17.

When 0'' is written in transistor (2) M1, it turns on and current flows to bit M(4) BLI, and the potential of sense node (9) SN11 decreases (Vcc - V
th ), then the bit line selection signal B
LTII and sense amplifier activation signal port become “L”,
When the sense amplifier is activated, reading is performed.By setting the 5-bit 1a selection signal BLTll to "L", the capacitance of the sense node (9) S N 11.5N12 is reduced when the sense amplifier is activated. becomes uniform, and stable reading can be performed. Also,
Similarly, the data of the memory transistor (2) M2 is read out by the lower sense amplifier composed of the transistors (1) Q20 to Q25. For example, by pairing bit lines and providing sense amplifiers at both ends, it is possible to simultaneously read from memory cells connected to the same word line, and the output buffer is used for the read data. By simply transferring the data to the output buffer, high-speed reading is possible.In addition, serial access is possible by sequentially transferring the read data to the output buffer.Also, the bit line and sense amplifier are one-to-one. Since it is compatible, it can be shared as a column latch for temporarily latching write data. Also, since it operates at 1.5V, there is no need for a circuit to maintain the bit line potential at IV or 1.5V, which simplifies the five-circuit configuration. moreover,
Since it operates at 1.5V, it has the effect of providing low power consumption.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the basic configuration of a nonvolatile semiconductor memory device that is an embodiment of the present invention, and FIGS. 2 and 3 show signals of various parts in reading of the nonvolatile semiconductor memory device of FIG. FIG. 4, a timing diagram showing waveforms, is a circuit diagram showing the basic configuration of a conventional nonvolatile semiconductor memory device. In the figure, (1) is a transistor, (2) is a memory transistor, (3) is a word line, (4) is a bit line, (
5) is a control gate line, and (9) is a Senne node. In addition, in FIG. 1, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a non-volatile semiconductor memory device in which a plurality of memory transistors each having a floating gate are arranged along a word line direction and a bit line direction, the bit lines are paired and a sense amplifier is connected to both ends of the bit line pair. A nonvolatile semiconductor memory device comprising: means for equalizing the bit line pair to a first potential; and means for precharging each of the bit line pairs to a second potential.