JPH0412613B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to the formation of a wiring layer in an electrode extraction window of a semiconductor device.

As integrated circuits become more highly integrated, multilayer doped polycrystalline silicon layers are increasingly used for wiring. In particular, in memory integrated circuits made of MIS elements, a polycrystalline silicon layer is often used for the gate, and therefore a polycrystalline silicon layer is also used for the word line connected to the gate.

However, since the resistance of the polycrystalline silicon layer is higher than that of metal, a delay time due to the product of wiring resistance and capacitance becomes a problem, which is disadvantageous for increasing the speed of integrated circuits. Therefore, high-melting point metals are being considered as wiring materials, but they have drawbacks such as poor masking properties for ion implantation, easy oxidation, poor chemical resistance, and high contact resistance with semiconductor substrates.

Therefore, high melting point metal silicides have come to be used. For example, tungsten silicide, molybdenum silicide, titanium silicide, tantalum silicide, etc. are used. The resistivity of these silicides is 10 to 100 .mu..OMEGA.cm, which is one to two orders of magnitude lower than the minimum value of 1000 .mu..OMEGA.cm for polycrystalline silicon, and furthermore, it is easy to form an ohmic junction with silicon.

When silicide is used to form elements, there are cases where it is used as a single silicide layer, and cases where it is used as a so-called polycide layer in which a polycrystalline silicon layer is laid under the silicide layer. Since the polycide layer is a composite layer,
Although it has drawbacks such as difficulty in setting etching conditions for forming fine patterns, it is easy to form ohmic junctions with silicon, and the use of polycrystalline silicon is a proven process that improves device characteristics such as threshold voltage and rise. The voltage, etc. remains the same as before, and there is no concern that new problems will arise regarding the interface, which is often problematic in device manufacturing.

(b) Conventional technology Figures 2 and 3 show highly integrated semiconductor devices;
1 is a sectional view of a conventional semiconductor substrate showing an electrode extraction window of, for example, a 256K or 1000 Mbit dynamic random access memory (DRAM).

In FIG. 2a, 1 is a semiconductor substrate and is an n-type silicon layer grown on a p-type silicon substrate. On top of this, an insulating layer 2 with a thickness of 1μ was deposited by vapor phase growth.
An electrode extraction window 3 is formed in this layer using phosphosilicate glass (PSG). With higher integration, the electrode extraction window 3 becomes less than 1.5 μm square.

In FIG. 2b, if the wiring layer 4 is formed by depositing aluminum containing 1 to 2% silicon to cover this window, if the area is as small as this, the contact resistance will increase and there will be a risk of wire breakage. The reason why the contact resistance becomes large is that a p-type blocking layer is formed locally within the contact area due to the suction of silicon from the substrate at the aluminum substrate interface or the movement of silicon contained in aluminum to the interface. This seems to be because this effect cannot be ignored in the electrode extraction window.

In FIG. 3a, the electrode extraction window 3 is filled with doped polycrystalline silicon 5 in order to eliminate the above-mentioned drawback of increased contact resistance. The embedding method is to deposit a polycrystalline silicon layer 5 on the entire surface of the semiconductor substrate using a low pressure vapor deposition (CVD) method, and then polish it.
or by reactive ion etching.
This is done by removing the polycrystalline silicon layer deposited on the PSG.

In FIG. 3b, an aluminum layer 4 is deposited over the polycrystalline silicon layer 5 on the planarized semiconductor substrate. In this way, the step coverage will be improved,
Although it is possible to prevent the increase in contact resistance peculiar to the above-mentioned small-area electrode extraction window, there is a problem that the resistance of the electrode wiring also increases because the electrical resistance of the polycrystalline silicon 5 itself is higher than that of metal.

Further, as described in Japanese Patent Application Laid-Open No. 50-75769, it has been proposed to use epitaxially grown single crystal silicon instead of the above-mentioned polycrystalline silicon. Although this method can certainly lower the resistance than polycrystalline silicon, since the material is a semiconductor, there is a limit to how low the resistance can be made.

Furthermore, as described in Japanese Patent Application Laid-open No. 50-50881, tungsten hexafluoride is applied to polycrystalline silicon once embedded in the electrode extraction window at a temperature of about 500°C or higher, and the polycrystalline silicon is converted into tungsten. It has also been proposed to embed tungsten in the electrode extraction window by replacing it. However, with this method, if the reaction progresses excessively, the underlying silicon substrate that makes up the semiconductor element will be eroded, and even worse, the silicon substrate that makes up the semiconductor element will be eroded.
There were inconveniences such as destruction of the PN junction.

(c) Problems to be Solved by the Invention As mentioned above, in the conventional configuration shown in FIG. 2, as the electrode extraction window becomes smaller, the step coverage of the wiring layer 4 made of aluminum or the like deteriorates, and furthermore, the contact resistance with the substrate increases. There is a problem that the area becomes large, and the method of burying polycrystalline silicon or epitaxially grown single crystal silicon in the electrode extraction window as shown in FIG. 3 improves the step coverage of the wiring layer 4, but on the other hand, Since the material to be buried is a semiconductor, there is a limit to how low its resistance can be made. In addition, in the method of replacing polycrystalline silicon with tungsten,
When a silicon substrate is used as the substrate, there is a problem in that the portion of the substrate that constitutes the semiconductor element is eroded, and even the PN junction that constitutes the semiconductor element is destroyed.

The object of the present invention is to eliminate the drawbacks of such conventional methods, to form a flattened electrode wiring structure that has low resistance of the electrode wiring itself and low contact resistance with the semiconductor substrate, and has excellent step coverage. The purpose is to provide a method.

(d) Means for Solving the Problem This problem involves opening an electrode take-out window in an insulating layer deposited on a semiconductor substrate to expose the semiconductor substrate, and then inserting polycrystalline silicon into the electrode take-out window. Or a process of embedding amorphous silicon and heating at 300℃ to 450℃.
By reacting the polycrystalline silicon or amorphous silicon with a compound of a high melting point metal at a temperature of This problem is solved by the method for manufacturing a semiconductor device of the present invention, which includes a step of converting into silicide.

(e) Effect The inventor of the present invention conducted an experiment in which non-single crystal silicon and tungsten hexafluoride were reacted by changing the temperature. As described in Publication No. 50881, metallic tungsten precipitates to replace non-single-crystal silicon, but when tungsten hexafluoride is applied to non-single-crystal silicon at a temperature of 300 to 450°C,
It was experimentally discovered that tungsten silicides such as W ₅ Si ₃ are mainly formed, and the present invention was created based on this new knowledge. According to the present invention, by reacting a part or all of the polycrystalline silicon or amorphous silicon buried in the electrode extraction window with a compound of a high melting point metal and converting it into a high melting point metal silicide, its own resistance can be increased. In addition, by interposing a high melting point metal silicide layer between the aluminum and the semiconductor substrate, an increase in contact resistance due to the above reasons is prevented. Furthermore, since the electrode extraction window is filled with high melting point metal silicide, the semiconductor substrate The flatness of the surface is good, so step coverage of aluminum is not a problem.

Although the mechanism by which silicide is formed is not yet well understood, first a compound of a high melting point metal is reduced by polycrystalline or amorphous silicon to form a high melting point metal, and then this high melting point metal and the remaining silicon are reduced. It is thought that these react with each other to form high melting point metal silicide. When, for example, tungsten hexafluoride is used as the high melting point metal compound, the reaction formula for the above reaction is as follows.

3Si + 2WF ₆ → 2W + 3SiF ₄ xW + ySi → WxSiy In the case of polycrystalline silicon, multiple reactions occur not only on the surface but also along its grain boundaries, and in the case of amorphous silicon, in easily reactive areas such as hydrogen-containing parts. It is presumed that a substitution reaction occurs, in which the precipitated high-melting point metal such as W reacts with the remaining silicon around it, and the entire surface becomes silicided.

Furthermore, if the reaction is carried out excessively to the point where even the Si constituting the silicide is replaced with the high melting point metal, there will be a problem in that even the silicon constituting the underlying semiconductor substrate will be locally eroded. However, in the present invention, such inconvenience does not occur because the reaction is stopped at the time of silicidation.

(f) Embodiment FIG. 1 is a sectional view of a semiconductor substrate according to the present invention showing an electrode extraction window of a highly integrated DRAM.

In FIG. 1a, 1 is a semiconductor substrate and is an n-type silicon layer deposited on a p-type silicon substrate. On top of this, an insulating layer 2 with a thickness of 1μ was deposited by vapor phase growth.
An electrode extraction window 3 is formed in this layer using phosphosilicate glass of m.

In FIG. 1b, the electrode extraction window 3 is filled with doped polycrystalline silicon or amorphous silicon 5. In FIG.

The embedding method is 620℃ in the case of polycrystalline silicon layer.
A polycrystalline silicon layer is deposited on the entire surface of the semiconductor substrate by a low pressure vapor phase growth method using thermal decomposition of silane SiH ₄ at 0.2 to 0.3 Torr, and then coated on the PSG using means such as polishing and reactive ion etching. This is done by removing the deposited polycrystalline silicon layer.
In the case of amorphous silicon, the 13.56MHz RF power is
100W plus 0.1 to 1.0 Torr of argon for a few%
Plasma vapor phase epitaxy with silane _SiH4 diluted to 100% is used.

Next, the polycrystalline silicon layer or amorphous silicon 5 is reacted with tungsten hexafluoride WF ₆ to convert part or all of it into tungsten silicide.

This reaction is carried out at 300% using a normal vapor phase growth apparatus.
Tungsten hexafluoride at ~450℃, 0.2~0.3Torr
This is done with a flow of 30 c.c./min and nitrogen or argon at 400 c.c./min. Furthermore, as described in Japanese Patent Application Laid-open No. 50-50881, when the temperature is increased to 500°C or higher,
Even the Si that should constitute the silicide is replaced with the high melting point metal, and the high melting point metal itself is directly precipitated, and even the underlying Si substrate is locally eroded and the replaced high melting point metal bites into the substrate. Therefore, in order to avoid such inconvenience, it is preferable to keep the reaction temperature at 450° C. or lower as described above. On the other hand, lowering the temperature also slows down the reaction rate and reduces the throughput, so from the viewpoint of ensuring a practical throughput, it is preferable to set the reaction temperature to 300° C. or higher.

The presence or absence of silicidation and its degree can be easily determined by applying X-ray diffraction, for example. When we performed X-ray diffraction measurements on a sample of polycrystalline silicon treated with tungsten hexafluoride at a temperature of 350°C, we observed a strong X-ray diffraction peak due to the silicide W ₅ Si ₃ , and its intensity was ,
It was more than 10 times the X-ray diffraction peak caused by W. By measuring the relationship between the reaction time and the degree of silicidation in advance under predetermined reaction conditions, silicidation can be easily controlled, for example, by changing the reaction time.

In this way, at least a portion of the non-single crystal silicon embedded in the electrode extraction window is converted into high melting point metal silicide with lower electrical resistance, and then an aluminum layer is deposited on this flattened substrate. When the wiring layer 4 is formed by patterning using a known method, an electrode wiring structure as shown in FIG. 1c is completed.

(g) Effects of the Invention As explained in detail above, according to the present invention, the resistance of the electrode wiring itself and the contact resistance with the semiconductor substrate are both small, and furthermore, the flattened electrode wiring has excellent step coverage. structure can be formed.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor substrate according to the present invention showing an electrode extraction window of a highly integrated DRAM. FIGS. 2 and 3 are cross-sectional views of a conventional semiconductor substrate showing an electrode extraction window of a highly integrated DRAM. In the figure, 1 is a semiconductor substrate, 2 is an insulating layer, and 3 is a semiconductor substrate.
4 indicates an electrode extraction window, 4 indicates a wiring layer, and 5 indicates a polycrystalline silicon layer or an amorphous silicon layer.

Claims (1)

[Claims] 1. After opening an electrode extraction window in the insulating layer deposited on the semiconductor substrate to expose the semiconductor substrate,
The electrode is formed by embedding polycrystalline silicon or amorphous silicon in the electrode extraction window and reacting the polycrystalline silicon or amorphous silicon with a high melting point metal compound at a temperature of 300°C to 450°C. A method for manufacturing a semiconductor device, comprising the step of converting at least a portion of the polycrystalline silicon or amorphous silicon in the extraction window into silicide of the high melting point metal.