JPH04123438A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a MOS transistor having high reliability, high driving performance and a strong channel effect by forming sidewalls of a conductive material and putting a high dielectric material having higher relative permittivity than that of a gate insulating film between a sidewall conductive material and a substrate. CONSTITUTION:Element regions 10 are formed on an Si substrate 1, and an n-channel or p-channel MOS transistor are formed inside the element regions 10. Insulating films 21, 22 for isolation are formed in a field region, gate electrodes 6 of a polycrystalline silicon film are formed through the respective region gate insulating films 17. Conductive materials 71, 72 to become sidewalls are formed on both sides of the electrodes 6. Polycrystalline or the like are considered as the conductive materials 71 and 72. A double layer construction of an insulating film 5 (51, 52) having higher relative permittivity than that of the insulating films 4 under the sidewalls to become gate insulating films and the gate insulating films 17 between the sidewalls 71, 72 and the substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention (Industrial Field of Application) The present invention is directed to the microstructured MO5 used in high-density integrated circuits.
The present invention relates to a type semiconductor device and its manufacturing method.

(Prior Art) As MoS transistors become smaller, hot carriers are generated due to the application of a high electric field to the source-drain junction, which causes deterioration of the device. A transistor with an LDD structure is well known as a transistor that alleviates a high electric field at a source-drain junction.

However, as the miniaturization of MOS transistors continues without changing the power supply voltage, the electric field concentration in the channel direction will further increase, and by providing an n-layer, which is a lightly doped impurity layer, as in an LDD structure transistor, the electric field concentration in the channel direction will increase. It will no longer be possible to keep up with the effects of mitigating the situation.

Therefore, among LDD structure transistors, a transistor with a structure in which the n+ region goes under the gate (that is, the entire n- region goes under the gate) (gate overlap LD
D transistor) has been proposed.

The manufacturing process of the gate overlap LDD transistor is shown in FIG. First, a gate oxide film 21 is grown on a P-type silicon substrate 20, and a first polycrystalline silicon 22 having a thickness of about 500λ is deposited thereon. A natural oxide film 23 with a thickness of about 5-10λ is grown on the first polycrystalline silicon 22, and a second polycrystalline silicon 24 with a thickness of about 1000λ is deposited thereon (FIG. 11(a)). Furthermore, CVD
5iO2 25 is deposited and patterned with a gate electrode pattern, and the second polycrystalline silicon 24 is etched using highly selective dry etching using 25 as a mask. This etching is stopped at the natural oxide film 23.

Thereafter, using 25 as a mask, n-type impurity ions are implanted to form an n- diffusion layer 27. At this time, the n-type impurity is 2
Ions are implanted at an acceleration voltage high enough to pass through 1 and 22. Furthermore, CVD 5i0226 which becomes the side wall
was deposited on the entire surface and etched using highly selective ion etching.
to have sex back. After patterning Ml polycrystalline silicon and post-oxidizing it to a thin layer to prevent channeling,
When n+ impurities are ion-implanted from the outside of the CVD S i 02 sidewall 26 and a thermal process is applied, a gate overlap structure is formed.

However, firstly, as mentioned in the previous section, the electric field in the channel direction can be relaxed by making the transistor have an overlapping LDD structure, but as elements become further miniaturized, the electric field in the channel direction becomes concentrated. It is necessary to alleviate the electric field in the channel direction by changing the structure of the transistor. Second, when etching the second polycrystalline Si in the manufacturing process, it is difficult to stop the etching at a natural oxide film. If the etching proceeds without stopping at the native oxide film, the thickness of the first polysilicon will change and the profile of the n- impurity will vary, making it impossible to obtain desired transistor characteristics.

Furthermore, if the etching of the second polycrystalline St does not proceed much and the natural oxide film remains thick, a problem of insulation within the gate will arise.

Thirdly, CVDSiO serves as a mask in the manufacturing process.
2, the aspect ratio of the gate is increased. Fourthly, in the manufacturing process, post-oxidation is performed before n + ion implantation, which causes a gate bird's beak, which increases mechanical stress in that area, resulting in a decrease in reliability. Fifth, if the first polycrystalline silicon is oxidized by the final thermal step in the manufacturing process, a complete overlapping structure may not be realized. Sixthly, there are problems such as the overall manufacturing structure being complicated.

(Problems to be Solved by the Invention) As described above, conventional LDD structure transistors have a limit in relaxing the electric field in the channel direction, and in order to compensate for this, the conventional gate-overlap LDI:
The manufacturing process of Lancista is unstable and the reproducibility (MO
No S transistor is formed. Furthermore, as elements become more miniaturized, even more reliable transistors will be required.

Finally, it is necessary to form transistors that are not only reliable but also have high drive capability and are resistant to short channel effects.

[Configuration of the Invention (Means for Solving the Problems) A semiconductor device according to the present invention has a MOS transistor configured as follows. First, the sidewalls used to manufacture the conventional LDD structure are formed of a conductive material to establish electrical conductivity with the gate. As a result, the low-concentration impurity diffusion layer completely overlaps the gate electrode (included in the sidewalls), making it possible to form a MOS transistor with high reliability, high driving ability, and resistance to short channel effects.

Furthermore, in the present invention, a high dielectric material having a dielectric constant higher than that of the gate insulating film under the gate electrode is inserted between the sidewall conductive material and the substrate. As a result, the vertical electric field is further strengthened at the sidewall portion, and the channel direction electric field is further relaxed. In other words, it is an MO with higher reliability, higher driving ability, and stronger resistance to short channel effects than conventional gate-overlapping DD transistors.
Creates an S transistor.

The method of the present invention for obtaining such a MOS structure is based on Si
A step of forming an element isolation region on the substrate, and then forming a gate insulating film and a high dielectric constant insulating film, and then SiO□
Using the resist as a mask, the CVD 5in2 high dielectric film and gate insulating film are removed by highly selective anisotropic etching to form a gate electrode using highly selective anisotropic etching. Therefore, ion implantation is performed (this is not necessary), a gate insulating film is formed on the exposed substrate, an electrode material is deposited on the entire surface, and a resist with a low viscosity coefficient is coated on the entire surface to make the entire surface flat. The process of removing the resist by anisotropic etching, and the process of removing the electrode material by anisotropic etching (CVD5 is not necessarily necessary), NH
Step of removing CV D Si O2 by JF isotropic etching and implanting low concentration impurity ions, step of implanting conductive material or high concentration impurity ions on the entire surface Depositing an insulating film on the entire surface and contacting the source/drain region The method includes a step of forming a hole and forming an electrode.

(Function) In the present invention, since a conductive material is used for the sidewalls and no insulating film is used between the gate electrode and the conductive material on the sidewalls, the low concentration impurity region completely overlaps under the gate (including the sidewalls). This makes it possible to realize transistors with high reliability, high drive capability, and resistance to short channel effects. Furthermore, in the present invention, a high dielectric constant insulating film is attached between the sidewall, which is a conductive material, and the substrate, so that the vertical electric field under the sidewall is strengthened, and the electric field in the channel direction is relaxed. A MOS transistor with even higher reliability, higher driving ability, and resistance to short channel effects can be realized.

According to the method of the present invention, a MOS transistor is manufactured by making a hole in CVD5 i 02 deposited on the entire surface and filling it with an electrode material using a resist etching back method.
The process of removing i02 by isotropic etching, depositing a conductive material on the entire surface, and then etching back the entire surface to leave the sidewalls intact prevents natural oxidation as seen in conventional gate-overlap LDD transistors. Since it does not include an unstable process such as stopping etching with a film, gate-overlap LDD transistors can be manufactured with good reproducibility.

(Example) The present invention will be explained in detail below.

FIGS. 1(a) and (b) respectively show the MO of the first embodiment.
FIG. 1 is a plan view showing an S-type transistor and a cross-sectional view thereof taken along line AA'. In this embodiment, an element region 1O is formed in a Si substrate 1, and an n-channel or P-channel MOS transistor is formed in the element region 10. The conductivity type of the substrate may be either P or n. Note that this substrate structure can be modified in various ways.

For example, an n-type Si substrate may be used to form a P-channel MOS transistor, or an n- or P-type Si substrate may be used to form a P-channel MOS transistor.
A substrate in which a high concentration n-type well is formed may also be used. Similarly, a P-type Si substrate may be used to form an n-channel MOS transistor. A structure in which a highly concentrated P-type well is formed in an n- or P-type Si substrate may also be used. An isolation insulating film 21 is provided in the field region.
2□ is formed. In this embodiment, the isolation insulating film 21.2° is formed by a selective oxidation method (LOCO5 method). Regarding these isolation techniques, in addition to the embodiments, it is also possible to use an oxide film filling method (BOX method), a BOX method of digging deep trenches (so-called trench isolation method), and the like.

Gate insulating film 1 in each area of the substrate separated into elements in this way
A gate electrode 6 made of a polycrystalline silicon film is formed through the gate electrode 7 . Note that a conductive layer 3 is introduced in advance on the substrate or well surface of the MOS transistor region for threshold mirror control. Of course, this conductive layer may not be formed. Conductive material 71.7□ serving as side walls is formed on both sides of the gate electrode 6. The insulating film 4 and the gate insulating film 17 under the sidewalls are made of materials 71 and 72 and become an insulating film.
A two-layer structure of an insulating film 5 (51, 52) having a higher dielectric constant than that of the insulating film 5 (51, 52) is formed. For example, if 5i02 is selected as the gate insulating film 4 under the side wall of the gate insulating film 17, the material of the high dielectric constant insulating film 5 (5+, 52) is Si3N4.
, Ta2O, etc. can be considered. In addition, the gate insulating film 17
are 5i02 and Si3N.

You may also combine these to create a two-layer or three-layer structure.
The side wall then? +, between 72 and the substrate are SiO□ and Si3
It has a three-layer or four-layer structure combining N4 and Ta206. Is the sidewall more important than the dielectric constant of the gate insulating film 17? +, 72. If this is achieved by increasing the dielectric constant of the film between the substrates 1, then the sidewalls 71.
The film between the substrate 72 and the substrate may be a single layer of a high dielectric constant material. In addition, the source/drain regions include the first lightly doped impurity ion-implanted n-type layer or P-type layer 81, 82 and the high-concentration impurity layer n+-type layer or P+-type layer 9I, 9.
It is composed of z. For the n-type layer or P-type layer 81,82, which is a low concentration impurity layer ion implantation, using the gate electrode 6 as a mask, arsenic or phosphorus is used for the n'' type layer, and boron or boron fluoride is used for the P-type layer. It is formed by ion implantation of n.
The ゝ type layer or P+ type layer 9+, 9z is a conductive material 7+, ? that is selectively formed on the gate electrode and its sidewalls. 2 as a mask, phosphorus or arsenic is ion-implanted for n+ type, and boron or boron fluoride is ion-implanted for p+ type. The n-type layer or the p-type layer is configured to be inside the n+-type layer or the p+-type layer, respectively, to form a so-called LDD.
form a structure. Note that the conductive materials 71 and 72 are left on the side walls of the gate electrode 6 using a side wall leaving technique.

To give concrete numerical values, if the gate length is 0.5 μm, the side wall width is 0.1 μm, and the effective channel length is 0.4 μm, the gate length including the side walls is 0.7 Im. (including) is 0.3 μm.

The substrate on which the elements are formed is covered with a CVD insulating film 11, and a contact hole is opened in this to form a metal wiring 1 such as an L film.
21.12□ is formed.

FIGS. 2(a) and (b) are MOSs of the second embodiment, respectively.
FIG. 2 is a plan view showing a type transistor and a sectional view thereof taken along line B-B'. In this embodiment, two or more MOS transistors (transistor 1 and transistor 2) of the first embodiment are formed with different gate lengths, and they are connected with a gate polysilicon and a contact hole is formed in the gate polysilicon and an Al film is formed. Metal wiring 13 such as the like is formed.

A contact hole is made on the gate polysilicon layer, and Al1
There are two methods for forming the metal wiring 13, such as a film, other than the method of forming it on the element isolation region (on the field) as shown in FIG. 2(a). This is shown in the third embodiment (Fig. 3).

FIG. 3(a) shows a method of making a contact on the gate polysilicon layer on the element region (on the SDG). At this time, it is better to make contact on the gate polysilicon of the transistor with the longer gate length; for example, it is easier to make contact from the point of view of the transistor with the shorter gate length.

If it is long, contact can be made on the short side of the gate face.

Another method for forming contacts is to form contacts not only on the gate polysilicon but also on the sidewall conductive material 7, as shown in FIG. 3(b). This method may be performed on the element region or on the element isolation region. If the contact is made not only with the gate polysilicon but also with the sidewall conductive material 7, the conduction between them will be good, and the gate overlap effect of the transistor will work well, so that a highly reliable transistor can be expected.

FIGS. 4(a) to 4(j) are cross-sectional views for explaining the manufacturing process of the MOS transistor of the second embodiment. Moreover, FIGS. 5(a) to 5(e) are plan views of the main steps.

Next, specific manufacturing steps will be explained using these figures.

First, a well is formed in the region of the Si substrate 1 where the MOS transistor is to be formed, so that the impurity concentration near the surfaces of the element regions 10+ and 102 is approximately 10''/an3.After this, the element isolation insulating film 2+ 2223 is formed. 5(a) shows the separated device regions 101 and 102. After that, each region is coated with S of about 100λ, which becomes an insulating film under the sidewall.
iO□4 and 5i3N45 of about 100λ are formed by thermal oxidation and CVD, respectively. After that 4000000
A λ in2 film 15 is formed using the CVD method, and the densification is 9.
CVD 5iC (CVD 5iC) exposed from the resist 16 using patterning (RIE) at 00° C. for 60 minutes so that the resist remains in areas other than the portion where the gate is to be formed.
2 Sara 1. : Below lt+ (7) After heating Si3N4, ion implantation is performed to prevent punch-through and control the threshold value to form a channel region 38.3□. For this ion implantation, normal 7° ion implantation to prevent channeling may be used, but rotational ion implantation is more effective since offset of the channel region under the gate is eliminated. Thereafter, a thermal oxide film 17 of about 100 λ is further formed on the exposed Si substrate. Furthermore, about 6,000,000 λ of polycrystalline silicon 6 containing phosphorus is applied thereon. (Fig. 4 (C)) After this, this polycrystalline silicon 6 is filled into the hole formed by CVD5iO□, and two transistors with different gate lengths (transistor l and transistor 2 in Fig.
) at the same time, a low viscosity resist 17 (so-called etch pack resist) is applied on the polycrystalline silicon 6.
Apply to make the whole surface flat. (Figure 4(a)) After that, highly selective anisotropic etching RIE is used, resist 1
The polycrystalline silicon 6 is completely buried between the CVD 5i02 films by etching the polycrystalline silicon 7 (FIG. 4(e)).
f)) Furthermore, CVD5iO21 on both sides of polycrystalline silicon 6
5 is removed using NH and F.

NHd F that eliminates board damage done in this special sale
Thread processing Niyori CV D Si O2 membrane 15 is CVD
Since it has receded somewhat from the time immediately after RIE (FIG. 4(b) post-RIE), polycrystalline silicon 6.
There is no need to worry about the NH4F liquid entering the thermal oxide film 17 under 61 and 62 (because SisN45 blocks it).
In order to form the impurity layers 8 and 84, P (phosphorous) is ion-implanted at a dose of 4 x 10"cm-3 and an acceleration voltage of 40 KeV (Fig. 4 (g)) (Fig. 5 c)). This polycrystalline silicon 7 may or may not contain phosphorus (FIG. 4(h)).Then, highly selective anisotropic etching is performed to form a gate polysilicon layer. Side walls 71 on both sides of 62
72.1s, 74 is formed. Furthermore, in order to form n+ impurity layers 91 to 94, As (arsenic) ions are implanted at a dose of 5×10 15 Cal −3 and an acceleration voltage of 40 KeV.

(FIGS. 4(i) and 5(d)) This ion implantation increases the conductivity of the polycrystalline silicon in the sidewall portion.

Finally, a CVD insulating film 11 is deposited on the entire surface at 850°C.
Electrode wiring 121, 122, 123 is formed by densifying the CVD insulating film 11 with high selective anisotropy etching to form contact holes to form A and 9 films.
, form. (FIG. 4(j) and a contact on the gate polysilicon are formed. FIG. 5(e)), and the present transistor is completed.

According to this embodiment, since a conductive material is used for the sidewall portion to form the gate including the sidewall portion, the LDD low impurity layer can be completely overlapped under the gate.

Why does gate-overlap structure transistor have high reliability?
Here are the results of a Moto 6 simulation that explains the concept of "becoming a star." (a) shows a conventional LDD structure transistor (b) is an example. It can be seen that by completely overlapping the impurity diffusion layer under the gate, the vertical electric field is strengthened, thereby weakening the l-channel electric field that causes impact ionization and hot carrier generation.

Furthermore, in this embodiment, a high dielectric film is provided between the sidewall of the conductive material and the substrate, unlike the conventional gate overlap LD.
D This is different from a transistor.

The effect will be explained using FIG. 7. FIG. 7 is a simulation of the electric field intensity distribution in the channel direction near the drain when the dielectric constant of the insulating film between the sidewall and the substrate is changed. That is, as an insulating film, 5i02(εr −3,
9) is used as a conventional gate-overlap structure transistor, and the insulating film is Si 3 Na (εr −
7,5) and T *20 B (εr ˜30) are used in this embodiment. The simulation results show that when a high dielectric material (Ta205 or 5i3N4) is used, the vertical electric field in that part becomes stronger, the channel direction electric field that causes hot carrier generation is relaxed, and reliability is improved.

To summarize the above, conventional LDD transistors relax the lateral electric field by providing a low concentration impurity layer, and conventional gate overlap DD transistors further strengthen the vertical electric field and relax the lateral electric field. In this embodiment, a high dielectric material is provided under the sidewalls to further alleviate the lateral electric field. FIG. 8 shows the difference in reliability of the above three transistors. The vertical axis represents the amount of gm deterioration, and the horizontal axis represents the stress time. The transistor of this example has the above three
It can be seen that this is the most reliable transistor among the transistors.

The effects obtained in this embodiment are not limited to reliability but also appear in initial characteristics. By completely overlapping the gate with the low concentration impurity layer and further providing a high dielectric material under the sidewalls, the vertical electric field is strengthened, and the control of the potential under the gate by the gate is strengthened. This effect appears prominently in the short channel effect, and FIG. 9 shows a diagram of the short channel effect. Thus, it can be seen that this example is a transistor that is resistant to short channel effects.

By increasing the vertical magnetic field, current flowing through the channel and the impurity diffusion layer is caused to flow from the bulk of the high resistance region to the substrate surface of the low resistance region. This results in a greater driving capacity than in the past. This situation is shown in FIG.

[Effects of the Invention] As described above, according to the present invention, a conductive material is used for the side wall portion, and a high dielectric material is used for the side wall and the substrate, thereby achieving a gate overlap effect and achieving high reliability and high drive. It is possible to realize a MOS type transistor with high performance and strong resistance to short channel effects. Furthermore, the transistor can be manufactured stably without using an unstable process unlike the conventional gate-overlap LDD transistor manufacturing process.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a diagram showing a MOS transistor according to a first embodiment of the present invention, FIG. 2 is a diagram showing a MOS transistor according to a second embodiment of the present invention, and FIG. 3 is a diagram showing a MOS transistor according to a second embodiment of the present invention. is a diagram showing how to make a contact on the gate of a MOS transistor according to the third embodiment of the present invention, FIG. 4 is a cross-sectional view showing the transistor manufacturing process of FIG. 2, and FIG. 5 is a plan view of the main process. Figure 6 shows simulation results showing the electric field strength distribution in the channel direction near the drain of the conventional LDD transistor and the example, respectively, and Figure 7 shows the conventional gate-overlapping DD transistor and the drain of the example. Figure 8 is a diagram showing the simulation results showing the electric field strength distribution in the channel direction near the inn, Figure 8 is a diagram showing the stress time dependence of the amount of gm deterioration for comparing the reliability of the conventional example and the example, Figure 9 10 is a diagram for comparing the short channel effect of the conventional example and the example, FIG. 10 is a diagram for comparing the driving ability of the conventional example and the example, and FIG. 11 is the manufacturing process of a conventional gate-over-tube transistor. FIG. 1...Si substrate, 21.22.23...Isolation insulating film, 31.3:! , 33... Channel region of transistor, 4... Gate insulating film 5.5+ 52, Ss 54... High dielectric constant film, 6.
6. 62...Gate electrode, 7.71.72,"I3.74...Conductive material serving as sidewall, 81.82.83.84...Low concentration impurity diffusion layer, 91.92.93.94.・・High concentration impurity diffusion layer,
1O1IL -102...Element region 11...Insulating film, 121.122.123...Electrode wiring, 13-...
Electrode wiring, 15・”CVD Si 02.16...
・Resist, 17.17+, 172... Gate insulating film, 18... Resist, 20... P-type semiconductor substrate,
21... Gate oxide film, 22. 24... Polycrystalline silicon, 23... Natural oxide film, 27... High concentration n-type impurity diffusion layer, 28, Low concentration n-type impurity diffusion layer, 29.・
・SiO□

Claims (8)

[Claims] (1) A MOS transistor is integrated and formed on a semiconductor substrate, and the source and drain regions of the MOS transistor are formed from a first high-concentration impurity ion-implanted layer, and the end portion of the channel region is from the first high-concentration impurity ion-implanted layer. 1. A semiconductor device comprising a first low concentration impurity ion-implanted layer protruding outward. (2) The semiconductor device according to claim 1, wherein a conductive material is used for the side walls of the gate electrode of the MOS transistor. (3) The semiconductor device according to claim 1, characterized in that an insulating film having a higher dielectric constant than the gate insulating film is used between the side wall of the gate electrode of the MOS transistor and the semiconductor substrate. (4) The semiconductor device according to claim 1, wherein the MOS transistors are integrally formed on a semiconductor substrate, and each gate length is the same or different. (5) The semiconductor device according to claim 1, wherein in forming the contact on the gate of the MOS transistor, the contact is made on an element isolation region or an element region. (6) The semiconductor device according to claim 1, wherein in forming the contact on the gate of the MOS transistor, the contact is made including the sidewall. (7) When forming an integrated MOS transistor on a semiconductor substrate, the manufacturing process consists of forming a high dielectric constant insulating film on the substrate via the first gate insulating film, and forming a high dielectric constant insulating film on the high dielectric constant insulating film. A step of depositing a first film and patterning a resist thereon, and removing the high dielectric constant insulating film and the first gate insulating film using highly selective anisotropic etching as the resist mask, and removing the channel portion. ion implantation is performed to form the semiconductor substrate, a second gate insulating film is formed on the exposed semiconductor substrate, a first conductive material is deposited on the entire surface, and a film with a small viscosity coefficient is coated on the entire surface. a step of flattening the surface, a step of performing highly selective anisotropic etching on the entire surface and burying the first conductive material in the hole of the first film, and removing the first film using isotropic etching. A process of ion-implanting impurities at a low concentration, a process of depositing a second conductive material on the entire surface, and a highly selective anisotropic etching process on the entire surface to form side walls of the first conductive material and impurities at a high concentration. 1. A method for manufacturing a semiconductor device, comprising the steps of implanting ions, depositing an insulating film over the entire surface, forming contact holes in source/drain parts, and forming electrode wiring. (8) After the step of depositing the first conductive material on the entire surface, a step of embedding the first conductive material by performing highly selective anisotropic etching on the entire surface without coating the entire surface with a film with a small viscosity coefficient. 8. The method of manufacturing a semiconductor device according to claim 7, further comprising: a.