JPH04123235A - Microprogram debugging method and method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figs. 7 and 8) Problems to be solved by the invention (Figs. 7 and 8) Means for solving the problems (Fig. 1) , 2) Effects (Figs. 1 and 2) Embodiments (Figs. 3.4 and 5.6) Effects of the invention (Summary) A memory that stores a microprogram and a microprocessor that operates according to the microprogram. The purpose of the present invention is to provide a microprogram debugging method and method that has high processing speed, high workability, and high safety, regarding a microprogram debugging method and method for discovering and correcting errors in a microprogram in a system that has a microprogram. A tester that can access the memory after instructing to put the microprocessor into a hibernation state according to instructions from an operator; This configuration includes a switching circuit that cuts off the connection between the microprocessor and the memory and switches the connection between the memory and the tester.

(Industrial Application Field) The present invention relates to a microprogram debugging system and method, and particularly relates to a memory for storing a microprogram,
The present invention relates to a microprogram debugging system and method for discovering and correcting errors in the microprogram in a system having a microprocessor that operates according to the microprogram.

[Conventional technology]

Conventionally, there has been a microprogram debugging method according to a first conventional example in which the microprogram is debugged (investigated) when a failure occurs in the microprogram.

As shown in FIG. 7, this system includes a memory 54 that stores a microprogram to be debugged and a debugging program, a microprocessor (MPU) 51 that operates according to the microprogram, and a tester 52 which is worn by an operator and instructs debugging when a debugging process occurs;
A group of control registers (address register, data register,
and R/W register, etc.) 53.

"Debugging" as used herein means detecting, tracking, and removing errors in a program.

The microprogram debugging method according to this example operates as follows.

If there is a failure in the microprogram stored in the I10 area of the memory 54 that is being executed by the MPU 51,
When the tester 52 is attached by the operator and the operator gives an instruction to the tester 52, the tester 52 outputs an interrupt signal to the external interrupt terminal of the MPU 51.

When an interrupt occurs, the MPU 51 reads an area of the memory 54 in which a debug processing program is stored, and executes the interrupt processing according to the program.

Here, the debugging process is performed by M
This is executed by the PU 51, and the MPU 51 reads necessary data instructed by the operator according to a debugging program without stopping, and displays the read data.

The operator compares the displayed data with the expected value that would be expected if the microprogram is operating correctly, and by looking for matches or discrepancies, he can discover errors in the microprogram, or even check other data. Debugging processing is performed by instructing the reading of .

On the other hand, as a second conventional example, there is a method of debugging a microprogram using an emulator.

Here, an "emulator" is a device by which one system imitates another system, so that the imitating system accepts the same data, executes the same computer program, and obtains the same results as the imitated system. means.

In this method, as shown in FIG. 8, M
By physically removing the PU 82 from the board 81, the MP
It is used with an emulator 83 attached to the board 81 in place of U82, and each terminal connected to each terminal of the removed MPU 82 is connected to each corresponding terminal of the emulator 83. The emulator 83 performs the function of the extracted MPU 82, and debugs the microprogram stored in the memory.

(Problem to be Solved by the Invention) By the way, as explained above, in the first conventional example, the debugging process of the microprogram is performed by the MPU 51 operating according to the debugging program using an interrupt. The tester only indirectly performs debugging by instructing the MPU to read and display necessary data, and it is the MPU 51 that operates according to the instructions. Therefore, MPU
51 is operating, it is impossible to read out the contents of the registers and memory used, and not only is the range of reading limited, but the control register 53 for issuing commands and instructions from the tester is However, compared to the case where the tester 52 directly performs debugging processing, the problem is that the response time is longer and the processing is slower.

In addition, in the microprogram debugging method according to the second conventional example, the MPU 82 that operates according to the microprogram is replaced with an emulator 83 that acts on behalf of the MPU 82, which improves workability and safety. The problem was that it could not be said to be very good.

Therefore, the purpose of this project was to provide a method for debugging microprograms that performs high-speed debugging processing, has a simple structure, is fast, safe, and has good workability, without requiring work such as replacing the MPU. be.

[Means to solve the problem]

In order to solve the above technical problems, the first invention is a system having a memory 4 for storing a microprogram and a microprocessor 1 for operating according to the microprogram, as shown in FIG. In a microprogram debugging method for discovering and correcting errors, the tester 2 becomes accessible to the memory 4 after instructing the microprocessor 1 to go into a hibernation state according to an operator's instructions. , a switching circuit that puts the microprocessor 1 into a hibernation state, cuts off the connection between the microprocessor 1 and the memory 4, and switches the connection between the memory 4 and the tester 2 according to an instruction from the tester 2; 3.

On the other hand, as shown in FIG. 2, the second invention puts the microprocessor that operates according to the microprogram targeted for debugging into a hibernation state (S2) when there is an instruction from the operator (S1). ), the connection between the memory in which the microprogram is stored and the microprocessor is cut off, and the connection is switched between the memory and the tester (S3), and after the connection between the memory and the tester is switched, the connection between the memory and the tester is switched off. Accordingly, the memory is accessed (S4).

[Effect]

Next, the operation of the system and method according to the present invention will be explained.

As shown in Figure 1, a microprocessor (MPU) 1
If a failure occurs in the microprogram while it is operating according to the microprogram stored in the memory 4, the operator will perform debugging processing.

When the operator instructs the reading of data necessary for debugging in step S1, the tester 2 instructs the switching circuit 3 in step S2, and the switching circuit 3
Put the PU (microprocessor) 1 into hibernation mode.

When MPUI is in hibernation state, tester 2 is activated in step S3.
In this case, the connection such as the bus line between the memory 4 in which the faulty microprogram is stored and the MPUI is cut off, and the connection between the memory 4 and the tester 2 is switched.

This allows the tester 2 to access the memory 4 in step S4. Therefore, for example, the operator instructs the tester 2 to access and read data deemed necessary for debugging the microprogram from the memory 4 and display it.

In that case, the operator can, for example, compare the displayed data with the expected value that the microprogram would be expected to take if it is correct, and according to the agreement or discrepancy of the results of the comparison, discover errors or further Instructs to read data.

Furthermore, as shown in claim 2.4, by interrupting the microprocessor 1 before performing the depacking process,
For example, by saving the internal state held in each register in advance, it is possible to smoothly return to the original process.

Note that the tester 2 according to the present invention is different from the tester 52 according to the first conventional example in that it completely stops the MPU 1 and performs debug processing.

〔Example〕

Next, a microprogram debugging method according to an embodiment of the present invention will be described.

FIG. 3 shows a system according to this embodiment.

In this system, as shown in the figure, a microprocessor (MPU) 1 operates according to a microprogram.
1, a tester 12 that operates according to instructions from an operator in order to perform interrupt processing for the MPUII and debug processing of the microprogram, a memory area for storing the microprogram, and an I10.
The MP
A switching circuit 13 that issues a halt command to the UII, cuts off the connection of the bus line etc. between the memory 14 and the MPU II, and switches to the connection of the bus line etc. between the memory 14 and the tester 12, and an operator; The apparatus includes an operator console 20 for instructing access processing to the memory 14, such as reading data necessary for debugging, and instructions for display.

Further, the tester 12 is connected to the tester 1 as shown in the figure.
MPU 12a, which controls the operation of step 2, Mt<MP
It has a tester program storage section 12b, which is used by the U12a to operate, and a connector 12c.

Note that the tester block of the tester 12 according to the present embodiment has a break point function (Break Point function), unlike the tester according to the conventional example.

P) and single step function (Sigle 5te
p).

Here, the B-2 function means that the previous MPUII is suspended and
This is a function that allows the tester to freely set an address (point) at which to stop (break) program execution when the access right to the memory 14 is transferred to the tester.

The program area of the memory 14 is accessed from the tester 12 side, a soft interrupt code is written in place of the program code at a certain program address, and the MPU
Run J11. (The original program code is stored at a certain memory address.) When the MPU II starts executing and executes the set address of B-P, a soft interrupt occurs and the MPU DEBUG process starts.

After that, install MPU DEBIJG circuit 1 as explained earlier.
5 is activated and puts the MPU II in the HOLD state.

To cancel B and P, change the original program code to B.
-P is returned to the set address again and B/P is released.

On the other hand, the single step function is similar to the B.2 function mentioned above, and the single step function is similar to the above-mentioned B.2 function.
It is one.

The major difference from the B-2 function is that B-P@Noh uses the program code area, but the single step function uses the M
The method is to use each control flag register of the PU. M
Each control flag register of the PU is a set of control flags necessary for the MPU itself to operate, and a single step bit exists in the control flag register.

The single step bit has a function of generating a soft interrupt every time the MPU executes one step of the program.

That is, from the tester 12 side, the control flag register stored in a special memory address by MPU DEBUG processing is accessed, and the single step bit is manipulated. Then, when the MPU is run again, a soft interrupt occurs when the 1-step program is executed. After that, the MPU DEBUG process is executed and the MPU enters the hibernation state.

Unlike before, these functions can only be used with the MPU.
This is because it becomes completely dormant.

Furthermore, as shown in the figure, the switching circuit 13 has M
It has a P U DEBUG circuit 15 and a multiplexer 16, and the M P U DEBUG circuit 1
5 is shown in detail in FIG.

As shown in FIG. 4, the circuit 15 includes an AND element 15□
, 153 , 154 , 156.157.

15□2, FF 152, 15to, Dv (driver) 15, OR element 15! , , 159 , and NOT
It has an element 15□.

Next, the operation of the microprogram debugging method and method according to this embodiment will be explained based on FIG. 4.5.6.

In step SJI, if the MPU II operating according to the microprogram malfunctions and it is determined that there is a fault in the microprogram, the operator uses the operation console 20 to read and display information on the tester 12. give instructions.

Then, the tester 12 sends an STP signal to the MPU II to interrupt, as shown in Figures 4 and 5. The STP signal is input to the external interrupt INT terminal of the MPU II, as shown in FIGS. 4 and 5. At the same time, the STP signal is sent to the MPU DEBUG circuit 15 in order to bring the MPU II into the HDLD state.
It is also sent to

When there is an STP signal, as shown in step SJ2, the MPU II activates the MPU DEBt]G process corresponding to the interrupt level of the signal and executes the interrupt process. .

In the interrupt processing, the program where the interrupt occurred
Addresses, MPU internal registers, MPU control flag registers, etc. are saved and stored in special memory addresses.

Here, the "internal registers" include address registers, data registers, R/W registers, and B.

There are P, (break point) point registers, etc. The purpose of saving is to continue the original processing when returning to the original processing after the interrupt processing is completed.

In step SJ3 shown in FIG. 6, when the processing such as saving is completed, the MPU II itself is put into a hibernation state (HOLD) via the I10 register, as shown in FIG.
In order to do this, the HOLD signal (■) is set to the N state.

The HOLD signal is input to the MPU DEBUG circuit 15.

In this way, when the STP signal and the HOLD signal are input to the circuit 15 in step SJ4, the MPU f(OL
Execute D SEQ[, 1ENCE. MPUI(OL)
DSEQUEN (1:H has REQ to MPUII
The LIEST signal ■ is generated, and the MPU II receives the corresponding REQU.
The device enters by receiving the EST signal ■.

When the MPUII itself enters the HOLD state,
In response to the REQtJEST signal ■, GRANT
The signal ■ is sent back to the MPU DEBUG circuit 15.

When the MPU DEBUG circuit 15 receives the GRANT signal from the MPU II, the MPU DEBUG circuit 15 sets the MPU II to HOLD.
Recognizing that the state has been entered, the TESTERUSE signal (2) is enabled and the MPU II is activated to the memory 1.
4 and the cutoff state, and ADDRE to the memory 14.
SS/DASTA Bus is from MPU II to tester 12
can be switched to the side.

In this way, the memory 14 can be freely accessed from the tester 12 side.

In step SJ4, the tester 12 reads necessary data from the memory 14 in accordance with the operator's instructions.

The read data is displayed in step SJ5, and in step SJ6, the data is compared with the expected value that would be taken if the microprogram operates normally.The operator looks at the comparison result, and then A decision will be made as to what action should be taken.

As shown in FIG. 6, the next process to take is to return to step SJI and instruct reading of another address, or to proceed to step SJ7 and use the break point function described above. , the address may be set, or the process may immediately proceed to step SJ8.

The processing when proceeding to step SJ8 will be described below.

Proceeding to step SJ8, the MPU
A RUN signal is sent to the MPU DEBUG circuit 15.

The MPU DEBUG circuit 15 is connected to the MPU from the tester 12 side.
When the RUN signal is received, *Te5ter of MPX16
By disabling the Use signal, the Ac1dress/Data Bus of the memory 14 is switched to the MPUII side again.

Then, the MPU DEBtJG circuit 15 sends RES (RELESE) in order to start up the inactive MPU II.
) send out a signal ■. When the MPU II receives the RES signal ■, the HOLD signal is turned off.

When the HOLD signal is turned off, the MPU II restores the internal register saved in the memory 14 in step SJ4 in step SJ9, and the MPU II restores the program address (program address at the time of HOLD). counter).

In step 5J10, start again from the address. The MPUII will now resume normal operation.

Next, the operation of the MPU DEBUG circuit 15 will be explained based on FIG. 5 and the like.

As mentioned above, in step SJ3, when the STP signal and the HOLD signal are input to the MPU DEBLIGH circuit 15, as shown in the circuit diagram of FIG.
The signal shown in FIG. 5 is output through the D element 151.

This signal causes the FF 15° to operate, outputting the signal shown in (2) in the same figure, and the signal shown in (2) in the same figure being output by this signal.

Therefore, the output signal of the AND element 153 is as shown in the figure.
The signal will be as shown in .

The signal passes through the OR element 155 and outputs the signal (2), which is input to the driver 158 and is driven to output the signal shown in (3) in the figure.
The REQ signal is output to PUII, and the signal shown in [phase] in the figure is output to the negative element 15□1 of the circuit 15.

When the MPU II receives the REQ signal, the MPU II
II itself is put in the HOLD state, and in response to the REQ signal, a CRT signal for one clock is generated as shown in FIG.

As a result, the MPU II becomes in a HOLD state and does not operate.

In addition, the CRT signal is
When received by the circuit 15 and input to the OR element 159, when all the conditions are met (STP signal, HOLD signal, CRT signal), the FF 15. o, and AND element 15□
2, from the circuit 15 to the multiplexer 16 as shown in FIGS.
Use) signal is sent, and the MPU interface is switched to the tester interface bus.

In addition, in order to start MPUII again, the tester 12
As shown in FIGS. 4 and 5, the RUN signal ■ is generated and inputted to the MPU DEBUGH circuit 15,
The MPU DEBUGH circuit 15 operates, and the O
The RES signal ■ will be sent from the R element 159 to the MPU II, and upon receiving the RES signal ■, the MPU 11 will be activated again and proceed to step SJ9 in FIG.

As explained above, in this embodiment, since the tester 12 has a break point function or a single step function, the operator can pause the MPU at a desired address, so that it is possible to investigate errors in the microprogram. This means that errors can be investigated reliably and quickly.

〔Effect of the invention〕

As explained above, in the microprogram debugging method according to the present invention, by providing a switching circuit, MP
In addition to switching between the U interface and the tester interface, the MPU is put into a hibernation state so that the tester can directly perform debugging.

Therefore, the present invention provides a microprogram debugging method that is faster in processing speed than conventional debugging methods, and has high workability and safety since it is not necessary to replace the MPU when using an emulator. You will be able to do that.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of the first invention, FIG. 2 is a principle flowchart of the second invention, FIG. 3 is a block diagram of the embodiment, and FIG. 4 is the MPU HOLD bus according to the embodiment. A diagram showing a switching circuit, FIG. 5 is an MPU DE according to an embodiment.
FIG. 6 is a timing chart of the BUG circuit, FIG. 6 is a processing flowchart according to the embodiment, FIG. 7 is a block diagram according to the first conventional example, and FIG. 8 is a block diagram according to the second conventional example. 1.11... Microprocessor (MPU) 2.12
...Tester 3.13...Switching circuit 4, Engineering 4...Memory patent applicant Fujitsu Ltd. Invention t > 141 ri flowchart @ 2 Kubrotsu 2 Figure 3 Figure 9 related to Zujishi Liu! Give it! Flowchart diagram for reaching 1.

Claims (1)

[Claims] (1) A memory (4) for storing a microprogram;
In a system having a microprocessor (1) that operates according to a microprogram, in a microprogram debugging method performed to discover and correct errors in the microprogram, the microprocessor (1) a tester (2) that becomes able to access the memory (4) after issuing an instruction to put the microprocessor (1) into a hibernation state; A switching circuit (3) is provided that cuts off the connection between the microprocessor (1) and the memory (4) and switches the connection between the memory (4) and the tester (2). A method for debugging microprograms. (2) a memory (4) for storing a microprogram;
In a system having a microprocessor (1) that operates according to a microprogram, in a microprogram debugging method performed to discover and correct errors in the microprogram, the microprocessor (1) is The memory (4)
a tester (12) that can access the microprocessor (12);
) and memory (4), and memory (4)
A switching circuit (3) for switching the connection between the terminal and the tester (12). (3) When the operator instructs (S1), the microprocessor that operates according to the microprogram targeted for debugging is put into a hibernation state (S2), and the memory in which the microprogram is stored and the microprocessor are The connection with the processor is cut off, the connection is switched between the memory and the tester (S3), and after the connection is switched between the memory and the tester, the tester accesses the memory (S4). A method for debugging microprograms characterized by the following. (4) If there is an instruction from the operator (S1), an interrupt is made to the microprocessor that operates according to the microprogram targeted for debugging (S1).
0), after the interrupt processing is completed, the microprocessor is put into a hibernation state according to an instruction (S2), the connection between the memory in which the microprogram is stored and the microprocessor is cut off, and the connection between the memory and the tester is cut off. A method for debugging a microprogram, characterized in that the connection is switched to a connection between the memory and the tester (S3), and after the connection is switched to a connection between the memory and the tester, the tester becomes able to access the memory (S4).