JPH04123151A - system bus - Google Patents

Abstract

PURPOSE:To suppress the deterioration of performance of the whole system without dissipating the part rewritten in a cache memory by providing an information transfer means for showing a store-through system or a copy-back system on each cache memory at the time when each cache memory accesses a shared memory. CONSTITUTION:When each cache memory M1,M2 accesses a shared memory CM, each cache memory concerned M1,M2 is provided with an information transfer means 41, BAo for showing a store-through system or a copy-back system. In this case, it is dsirable that a level of an exclusive signal line 4 being the information transfer means 41,BAo is set to a high level '1' and a low level 'O', in the case of the cache memory M2 of the store-through system, and in the case of the cache memory M1 of the copy-back system, respectively. In such a state, in the case a disconnection, etc., are generated in the signal line 4, all the cache memories M1,M2 are decided to be those of the store-through system and controlled. In such a way, deterioration of performance of the whole system is suppressed without dissipating the part rewritten in the cache memories M1,M2.

Description

[Detailed Description of the Invention] [Summary] Regarding a system bus in a system in which a plurality of store-through type cache memories and copy-back type cache memories coexist, a plurality of copy-back type cache memories and store-through type cache memories are provided. The purpose of the present invention is to provide a system bus that can suppress performance degradation of the entire system without erasing the rewritten portion of the cache memory in a system in which cache memories of different types are mixed. a system bus that connects at least one copy-back type cache memory, at least one store-through type cache memory, and a shared memory; The cache memory is configured to include information transmission means indicating whether the cache memory is a store-through method or a copy-back method.

[Industrial application field]

The present invention relates to a system bus used in a multiprocessor system that includes a plurality of cache memories and at least one shared memory, and in particular, a system bus that is used in a multiprocessor system that includes a plurality of cache memories that use a store-through method and a cache memory that uses a copy-back method. Regarding the system bus in the system.

[Conventional technology]

A store-through method and a copy-back method are known as methods for maintaining data consistency (coherency) between cache memories.

In the store-through method, each time cache data is rewritten, the shared memory is also rewritten, and data in other cache memories is invalidated. Therefore, in this method, the cache data always matches the data in the shared memory, and the control method is simple, so it has the advantage of being easy to design. However, since a bus access occurs every time one of the processors performs write processing to the corresponding cache memory, there is a drawback that bus traffic increases.

On the other hand, in the copy-back method, even if cache data is "hit" when written, bus access is not performed unless there is another cache memory that shares the data. In other words, there is an advantage that the frequency of bus access is reduced compared to the store-through method, and the performance of the entire system is improved. However, on the other hand, it has the disadvantage that cache control becomes complicated.

Incidentally, in recent years, there has been a tendency to mainly use copy-back type cache memories that can improve the performance of the entire system. Therefore, if a new copy-back cache memory is connected via the system bus to a system that uses an existing store-through cache memory, the copy-back cache memory and the store-through cache memory There may be cases where cache memory reads are mixed.

When controlling between each cache memory in a system where such copy-back type cache memory and store-through type cache memory are mixed,
There is a need for a system bus that can take full advantage of the advantages of each system.

FIG. 7 is a diagram for explaining the problems of the conventional cache memory control method using a system bus. In the cache memory control method shown in the figure, it is assumed that the cache memory A is a copy-back type cache memory.

(2) Another cache memory B accesses shared memory C and starts fetching one block of data.

■ Cache memory A owns the area to be accessed in cache memory B, detects that the area has already been rewritten but has not been reflected in shared memory C, and updates cache memory B. sends a signal to temporarily suspend the access.

■ Cache memory A replaces shared memory C.
The block data of the area to be accessed is transferred to cache memory B. At this time, the block data is not written to shared memory C. After that, cache memory A purges the block in the area.
do.

[Problem to be solved by the invention]

In the conventional system shown in FIG. 7 described above, no problem occurs if cache memory B uses the same copy-back system as cache memory A.

However, if cache memory B is a store-through type cache memory, the program rewritten in cache memory A will be stored in cache memory B.
After that, the block will be cleared by block replacement in cache memory B. In this case, the rewritten portion in cache memory A will be lost.

In order to eliminate this inconvenience, a method can be considered in which the block is simultaneously written into the shared memory C at the step (2) above. However, with this method, the advantages of the copy-back method (
Therefore, the problem arises that the performance of the entire system is degraded.

In view of the problems in the prior art, the present invention provides a system in which a copy-back type cache memory and a store-through type cache memory coexist.
Without erasing the rewritten part in the cache memory,
Another object of the present invention is to provide a system bus that can suppress performance degradation of the entire system.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of a cache memory control method using a system bus according to the present invention.

As shown in FIG. 1(a), according to the present invention, at least one copy-back type cache memory tag, at least one store-through type cache memory tag, and a shared memory side are connected. system bus (4)
And each cache memory mentioned above? When the ILM2 accesses the shared memory CM, information transmission means 41. indicates whether each of the cache memories Ml, M2 is a store-through type or a copy-back type. A system bus is provided that includes a BAa.

Further, the system bus of the present invention can be applied to a cache memory control method as shown in FIG. 1(b). In this cache memory control method, the copy-back method cache memory operates in a replace method,
and means (P1) for temporarily suspending access to the shared memory from another cache memory to an area owned by the cache memory that has already been rewritten and has not yet been reflected in the shared memory; ), and a means (P
2), and based on the result of the determination, if the accessed cache memory is a copy-back type cache memory, the data in the accessed area is not written to the shared memory. Means for transferring to cache memory using copy-back method (P3
), and means (P4) for writing back data in the accessed area to the shared memory if the accessed cache memory is a store-through type cache memory.

[Operation] According to the system bus of the present invention described above, when each of the cache memories Ml and M2 accesses the shared memory CM, it is determined whether each of the cache memories Ml and M2 uses the store-through method or the copy-back method. Information transmission means 41.
It is equipped with BA.

Here, the information transmission means can be constituted by a dedicated signal line 41. The level of this signal line 41 is preferably set to a high level "1" in the case of the store-through type cache memory M2, and set to a low level "0" in the case of the old copy-back type cache memory. In other words, if a disconnection or the like occurs in the signal line 41, all cache memories are determined to be of the store-through type and are controlled. Although this will reduce the performance of the system, there will be differences between each cache memory. Data can be prevented from being retained.

Further, the information transmission means can be configured by predetermined pins (BA, ) of the command bus CB.

The level of this predetermined bit BAo is set to high level "1" in the case of store-through type cache memory M2,
In the case of an old copy-back type cache memory, it is preferable to set the low level to "0". In this case as well, even if some kind of accident occurs, it is possible to determine that all cache memories are of the store-through type and prevent different data from being held between the cache memories.

Further, according to the cache memory control method to which the system bus of the present invention is applied, when a cache memory consisting of a shared memory is accessed, the cache memory is of a store-through method or a copy-back method. Since the information is transmitted by the above-mentioned information transmission means, the processing of the data in the area to be accessed is changed as appropriate depending on the information.

In other words, when the access is performed using a copy-back type cache memory, the data in the area targeted for the access is transferred to the copy-back type cache memory without writing it to the shared memory. . This eliminates the need for unnecessary access to the shared memory on the system bus, making it possible to suppress performance degradation of the entire system.

On the other hand, when the access is performed using a store-through type cache memory, the data in the area targeted for the access is written back to the shared memory. As a result, the portion rewritten in the copy-back type cache memory can be safely saved in the shared memory without being lost.

[Embodiments] Hereinafter, embodiments of the system bus according to the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of a tightly coupled multiprocessor system using the system bus of the present invention.

As shown in FIG. 2, this system uses a plurality of cache memories (in this embodiment, the cache memory shown in the figure is At least one shared memory 3 (CM: only one for each method is shown for simplicity) is connected via a system bus 4 to at least one shared memory 3 (CM:
Similarly, for simplicity, only one is shown).

Furthermore, central processing units (CPU) 2A and 2B are connected to each cache memory IA and IB, respectively, for supplying address information to the corresponding cache memory and controlling data reading and writing.

FIG. 3 is a diagram showing a specific example of the configuration of the system bus of the present invention in the system of FIG. 2.

FIG. 3(a) shows an embodiment of the system bus of the present invention in which a cache memory that accesses shared memory 3 (CM) uses a command bus CB to indicate whether the cache memory is a store-through type or a copy-back type. This shows that the signal is transmitted based on the level of the most significant bit BAo. Specifically, the system bus 4 includes, for example, eight command buses CB (BAo to BA?) and 16
1 (or 32) address/data bus ADH
(BB0 to BB+s). Then, by setting the most significant bit BA of the bits BA, ~BA, corresponding to the eight command buses CB to a high level "1", the cache memory (the cache memory accessing the shared memory 3) is stored.・Through-type cache memory I
By setting the most significant bit BAD to a low level "0", it is indicated that the cache memory is a copy-back type cache memory memory IA.

Here, the most significant bit BA of the command bus CB.

The reason why the level is set to high level in case of store-through type cache memory 1B and low level in case of copy-back type cache memory IA is that if some kind of accident occurs, bits for information transmission are set to high level. Since BA becomes a high level "l" and the cache memory is determined to be a store-through type cache memory IB and is controlled, the shared memory is rewritten every time the cache data is rewritten, and the performance of the system is reduced. This is to prevent different data from being held in each cache memory, although this reduces the amount of data. Also, shared memory 3
The bit indicating whether the cache memory to be accessed is a store-through method or a copy-back method is not limited to the most significant bit BA6 of the command bus CB.

FIG. 3(b) shows, as an embodiment of the system bus of the present invention, that the cache memory accessing the shared memory 3 is
The figure shows one in which the level of a dedicated signal line 41 is used to communicate whether it is a store-through method or a copy-back method. Specifically, in addition to a command bus CB and an address/data bus ADB, the system bus 4 further includes a dedicated signal line 41, and by setting the signal line 41 to a high level "1", the cache is Memory (cache memory that accesses shared memory 3) is stored and
This indicates that the cache memory is a through-type cache memory IB, and by setting the signal line 41 to a low level "0", it indicates that the cache memory is a copy-back type cache memory IA. .

Here, the level of the dedicated signal line 41 added to the system bus 4 is set to a high level in the case of the store-through type cash memory January B, and is set to a low level in the case of the copy-back type cache memory IA. The reason for this is that, as in the case described above, even if an accident such as a disconnection occurs, all cache memories are determined to be of the store-through type and different data is retained between each cache memory. This is to prevent Further, as shown in FIG. 3(b), each of the copy-back type and store-through type cache memories IA and IB is configured as an internal cache memory provided in the central processing unit CPU, respectively.

FIG. 4 is a diagram showing the internal configuration of the copy-back type cache memory IA in FIG. 2.

In the figure, reference numeral 31 is a tag section (tag memory), which includes an address section that stores the physical address of access data, and two status flags that indicate whether the pair of address and data is valid or not. It has a valid indication flag (V) indicating whether the data has been rewritten or not, and a changed indication flag (M) indicating whether the data has been rewritten or not. Furthermore, 32 is a decoder (DEC) that decodes the address on the system bus 4.
, 33 is a comparison circuit that detects the match/mismatch between the address registered in the tag unit 31 and the address ADD on the system bus 4, and 34 is a comparison circuit that responds to the output of the comparison circuit, the valid instruction flag, and the changed instruction flag. An AND gate 35 generates a temporary interruption signal INT, an inverter 35 responds to a method instruction signal INO sent via the system bus 4 and instructs whether to use the store-through method or the copy-back method, and 36 an inverter of the inverter. 37 is an AND gate responsive to the output and the time interrupt signal INT; 37 is an AND gate responsive to the mode instruction signal IND and the temporary interrupt signal INT; and 38
shows a circuit that forms a transfer cycle in response to the outputs of AND gates 36 and 37.

Note that the comparison circuit 33 sets its output to "1" when the address of the tag section 31 and the external access address ADD match.
As a result, the AND gate 34 is set to "valid J." Also, the method instruction signal IND (information transmission means 41.BA
(corresponding to o) takes "1" when instructing the store-through method, and takes "0" when instructing the copy-back method. Further, the output of the AND gate 36 is used as a signal for starting inter-cache transfer,
On the other hand, the output of the AND gate 37 is used as a signal to start copying back to the shared memory 3.

FIG. 5 is a diagram chronologically showing the cache memory control form in the system of FIG. 2. Figures (a) to (c)
Cache memory control will be explained with reference to .

[See FIG. 5(a)] (1) The cache memory IB accesses the shared memory 3 by instructing that it uses the store-through method (see method instruction signal IND in FIG. 4).

That is, the level of the most significant bit BA of the command bus CB is set to a high level "1" (see FIG. 3(a)), or
Alternatively, by setting the dedicated signal line 41 to a high level "1", the shared memory 3 is accessed indicating that it is a store-through system.

■ Cache memory IA identifies that cache memory IB uses the store-through method, and requests temporary suspension of access to cache memory IB (
(See temporary interruption signal INT in FIG. 4).

■ Cache memory IA is for shared memory 3.
Cancels access from cache memory IB.

[See Figure 5(b)] ■ The cache memory LA receives the above method instruction signal IND.
(BA, 41), the cache memory accessed above is stored-through type cache memory I.
B, and writes back the data (indicated by hunting) in the area targeted for access to the shared memory 3.

[See FIG. 5(c)] (cache memo IJIB accesses the shared memory 3 and fetches the necessary portion).

Although not shown in FIGS. 5(a) to 5(c), the cache memory that accesses the shared memory 3 performs copying and
If the cache memory is a back type cache memory, the data in the area to be accessed is transferred to the copy back type cache memory without being written to the shared memory 3, as in the conventional case.

FIG. 6 is a flowchart showing an example of processing performed by the copy-back type cache memory in FIG. The processing performed by the copy-back type cache memory IA will be described below with reference to the flowchart shown in FIG.

First, in step 51, it is determined whether the area accessed from the outside matches the block owned by the self (YES) or does not match (N0), and if the determination result is YES, the process proceeds to step 52, where the determination result is If NO, step 51 is repeated. In step 52, it is determined whether the block has been rewritten (YES) or not (N0). If the determination result is YES, the process advances to step 53, and the determination result is If this is NO, this flow becomes "end". In step 53, a signal (-time interrupt signal INT) for interrupting the external access is sent to the system bus 4.

In step 54, it is determined whether the external access was performed by the copy-back cache memory (YES) or not (N0). If the determination result is YES, the process proceeds to step 55; if the determination result is NO, the process proceeds to step 55. (That is, if the external access is performed by a store-through type cache memory), the process advances to step 56. In step 55, block data of the area to be accessed is sent to the system bus 4 instead of the shared memory 3. After this, the process proceeds to step 57, and after the blocks in the area are purged, this flow becomes "end".

On the other hand, in step 56, the block in the area is written back to the shared memory 3, since the external access is performed by the store-through type cache memory. After this,
Proceeding to step 57, the same processing as above is performed.

In this way, according to the cache memory control method to which the system bus of this embodiment is applied, an area that is owned by the copy-back type cache memory IA and that has already been rewritten but has not yet been reflected in the shared memory 3. If there is an access from another cache memory, the access is temporarily suspended, and depending on whether the accessed cache memory is a store-through method or a copy-back method, the access is The processing of data in the target area is changed as appropriate as described above.

By applying the system bus of this embodiment, data in the area to be accessed is transferred to the cache memo of the copy-back method, thereby eliminating the advantages of the copy-back method (wasteful This makes it possible to make the most of the access (eliminating access) and improve the performance of the entire system. On the other hand,
The data in the area targeted for access is stored in the shared memory 3.
By writing back to , the part that has been rewritten in the copy-back cache memo month i can be safely stored in the shared memory 3 without being lost.

〔Effect of the invention〕

As explained above, according to the present invention, in a system in which a copy-back type cache memory and a store-through type cache memory are mixed, the rewritten portion of the cache memory is not lost, and the system It is possible to provide a system bus that can suppress overall performance deterioration, and it is possible to improve the overall system performance.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of a cache memory control method using the system bus according to the present invention, FIG. 2 is a block diagram showing the configuration of a tightly coupled multiprocessor system using the system bus according to the present invention, and FIG. 2 is a diagram showing a specific configuration example of the system bus of the present invention in the system of FIG. 2, FIG. 4 is a diagram showing the internal configuration of the copy-back type cache memory in FIG. Figure 6 is a flowchart showing an example of the processing performed by the copy-back cache memory in Figure 2. Figure 7 uses the conventional system bus. FIG. 2 is a diagram for explaining problems with the cache memory control method. (Explanation of symbols) Ml, IA...Copy-back cache memory, M2. IB...store-through cache memory, 2A, 2B...CPU, CM, 3...shared memory, 4...system bus, 41...signal line for information transmission, CB...・Command bus, ADH...Address/data bus, BA,...Command bus via for information transmission), PI...Processing that temporarily interrupts access, P2...Cache memory that was accessed P3: Processing to transfer the corresponding data to the cache memory of the copy-back method; P4: Processing to write the corresponding data back to the shared memory. (b) Flock diagram showing the configuration of a tightly coupled multi-brosenothanostem using the nostem hash of the present invention. (a) (b) Figure IA: Cache memory (copy-back method) % formula % (Store-through method) 3...Shared memory Figure 2 shows the control form of cache memory in Nostem in chronological order To explain the problems of the Canon Yu memory control method using the conventional 7-stem hash same number

Claims (1)

[Claims] 1. A system bus that connects at least one copy-back type cache memory (M1), at least one store-through type cache memory (M2), and a shared memory (CM). The cache memory is characterized in that, when each cache memory accesses the shared memory, each cache memory is provided with an information transmission means (41, BA_0) indicating whether it is a store-through method or a copy-back method. system bus. 2. The system bus according to claim 1, wherein said information transmission means is constituted by a dedicated signal line (41). 3. The dedicated signal line (41) is set to a high level "1" in the case of a store-through type cache memory, and to a low level "0" in the case of a copy-back type cache memory. 3. The system bus according to claim 2, wherein the system bus comprises: 4. The system bus according to claim 1, wherein the information transmission means is constituted by a predetermined bit (BA_0) of a command bus (CB). 5. The predetermined bit (BA_0) of the command bus is set to a high level "1" in the case of a store-through type cache memory, and a low level "0" in the case of a copy-back type cache memory. 5. The system bus according to claim 4, wherein the system bus is configured as follows. 6. The copy-back type cache memory (M1)
and the store-through cache memory (M2
2. The system bus according to claim 1, wherein each of the buss is configured as an internal cache memory provided in a central processing unit (CPU). 7. The system bus operates in a replacement manner in the copy-back type cache memory (M1), and other information is provided to an area owned by the cache memory that has already been rewritten and has not yet been reflected in the shared memory. means (P1) for temporarily interrupting the access when detecting an access to the shared memory from the cache memory of means (P2) for determining whether the access was made by any of M1); and based on the result of the determination, if the accessed cache memory is a copy-back type cache memory, the target of the access; means (P3) for transferring data in an area to the copy-back cache memory without writing it to the shared memory; and when the accessed cache memory is a store-through cache memory; 2. The system bus according to claim 1, wherein the system bus is adapted to be applied to a cache memory control method comprising means (P4) for writing back data in the area to be accessed to the shared memory.