JPH0412286A - Waveform observing method for tester - Google Patents

Abstract

PURPOSE:To detect the output abnormality by switching a test signal generated by a tester main body and a pulse generated by a pulse generating circuit in a device for calibration and operating two loop-back signals. CONSTITUTION:A device 70 for calibration is provided with input leads 71 and 72 connected to the input lead 63a of an IC receptacle 63, a power lead 73 for which power is supplied from a tester main body 40 by an independent system, and an earth lead 74. The lead 71 is connected to not only the input side of a pulse generating circuit 75 but also the input side of a switching circuit 76, and the output side of the circuit 75 is connected to the input side of the circuit 76. Power is supplied to the circuit 75 from leads 73 and 74, and a pulse S75 for calibration or the signal of the lead 71 is selected in accordance with the active or inactive state of the lead 72 and is outputted, and the circuit 76 consists of a switching transistor, a gate circuit, etc. An output lead 77 which can be connected to the output lead 63b of the IC receptacle 3 is connected to the output side of the circuit 76.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a device tester that uses a tester to determine the quality of a device such as a semiconductor integrated circuit B (IC, LSI, VLSI, etc., hereinafter simply referred to as rIC). In the system,
The present invention relates to a tester waveform observation method for observing signal distortion that a test signal generated by the tester undergoes while reaching a device under test via a transmission path.

(Prior art) In general, testing methods for devices such as ICs include:
There are DC parameter tests, function tests, and AC parameter tests. The DC parameter test measures DC parameters such as input current, output current/voltage, and power supply current. AC parameter tests also include set-up time, hold time,
It measures access time, operation delay time, waveform rise/fall time, etc. An example of such a device tester system is shown in FIG.

FIG. 2 is a block diagram showing an example of the configuration of a conventional device tester system.

This device tester system includes a tester main body 10 having a test signal generation function, a pass/fail determination function, and the like. The tester main body 1-0 includes a central processing unit (hereinafter referred to as CPU) 1-1- and an input/output controller (hereinafter referred to as I1).
0 controller) 12, and a driver/receiver circuit 13 consisting of a driver 13a and a receiver 13b. The driver/receiver circuit 13 includes
The input terminals 2 of the test board 20 are
0a and output terminal 20b are connected.

The test board 20 has an input terminal 20a and an output terminal 20.
Leads (legs) 30a and 30b of a device under test, for example an IC under test 30, are connected to its input terminal 20a and output terminal 20b.

Next, a method for testing the IC under test 30 using such a device tester system will be described.

First, the CPU II generates test signals of various timings and amplitudes. The generated test l~ signal is I10
Driver/receiver circuit 1 via controller 12
3 is sent to the driver 13a. The driver 13a is
The signal sent from the CPU II is driven, and the signal is sent to the outgoing transmission line 14. a Input terminal 20a of test board 20
, and is supplied to the IC 30 to be tested via the lead 30a of the IC 30 to be tested.

The IC under test 30 performs a predetermined operation in response to a test signal from the CPU II, and outputs the result to the lid 30b. This output signal is transmitted to the output terminal 20 on the test board 20.
b, and is transmitted to the receiver 1.3b in the driver/receiver circuit 13 via the return transmission path 14b. The receiver 1-3b receives the signal from the transmission line 14b, and transmits the received signal to the controller 1-2.
Send to PU1l.

In CPU II, the internal verification function allows the CPU
The expected value corresponding to the test signal output by the test signal (this value can be predicted in advance in one-to-one correspondence with the test signal) is compared with the transmitted output signal of the IC under test 30, and if the two match, The IC30 under test is determined to be normal,
If they do not match, it is determined that there is a malfunction. As a result, the operation test of the IC 30 for the test target 1 is completed.

Here, if the test board 20 and the IC3tJ to be tested are configured to be electrically connectable, for example, by an IC socket (not shown), the C30 to be tested can be attached and detached by manual operation or automatic mounting. , it is possible to sequentially replace and test the ICs 30 to be tested.

Since the types of ICs under test 30 tested by this type of device tester system are enormous in terms of the number of leads, lead shapes, package sizes, and their functions, a dedicated tester system is required for each IC. It is difficult to create, and it is also not a good idea from a cost standpoint.

Therefore, in conventional testing methods, for example, a device tester system is divided into a main part that is common to each IC and a dedicated part that is not common, and the dedicated part is created for each IC using a hierarchical structure. .

In the example shown in FIG. 2, a tester main body 10 consisting of a CPU II, an I10 controller 12, and a driver/receiver circuit
is the main part, and the transmission line 14 and test board 20 are connected to each I
It is conceivable to make it a C-only section.

The device C is tested and selected using the device tester system as described above. In this test method, the tester operates correctly and the specified test signals are correctly transmitted to the IC under test.
It is assumed that the signal is transmitted up to 30 leads 30a.

Therefore, in the past, to confirm the normality of the tester function,
The device tester system was equipped with a self-diagnosis function to periodically perform self-diagnosis, calibrate the tester, confirm the normal operation of the tester, and ensure normal operation.

(Problems to be Solved by the Invention) However, when performing self-diagnosis and calibration of the tester in the above-mentioned device tester system, there are the following problems.

In the device tester system shown in FIG. 2, the scope of self-diagnosis is currently limited to the main part, that is, the tester main body 10, but when it comes to comprehensive diagnosis including the dedicated parts specific to each IC, There was no effective method. In other words, in the tester body which is the source of the test signal, it is easy to check by self-diagnosis to make sure that the correct signal is generated. It is difficult to check whether the received signal is correct or not.

When checking the dedicated section consisting of the transmission line 14a and the test board 20, there is also a method of performing self-diagnosis by, for example, using an oscilloscope to touch the lead 30a of the IC under test 30 with a probe and observing the signal waveform.

However, having multiple testers and calibrating all of them to the same level requires engineers with specialized knowledge to spend a great deal of time, which is not a practical solution to the problem.

Therefore, as an alternative method, the following two methods (1) are available.
, (2> are possible.

(1) Calibration method using standard samples Insert the IC type that has been confirmed to be operating normally using a separate method into the IC socket (not shown) provided in Figure 2, and if CPU II determines that its operation is normal, perform a device test. This is a way to make the system correct.

This method is effective in that it can test all the main parts and dedicated parts, but the timing and amplitude of the intended test signal are correct.
It is not possible to check whether or not it has been supplied to. This is because, in general, an IC has a certain margin (operating margin) for variations in the timing and amplitude of a test signal, and it operates correctly with variations within this margin.

(2) Calibration method by returning test signals
Lead 30 to which the test signal output from the 0 side is supplied
In this method, the test signal outputted from the tester main body 10 is looped back and sent back to the desk main body 10 by electrically connecting the terminal a and the output lead 30b of the IC 30 under test.

This method does not require the addition of a new transmission path, and
There is an advantage in that the signal output by the UII can be directly observed by the CPU 1l.

However, when sending back signals, the transmission line 1 for the return route
4b, the signal is distorted in this part, and the CP
The return signal received at UII is different from the actual signal on lead 30a.

That is, an IC is an active device and has its own input impedance and output impedance. Therefore, in the above method, the impedance differs, resulting in a state different from the operating state in which the IC 30 under test is actually inserted and tested, and the signal distortion due to signal reflection also differs from the operating state. To deal with this, it is possible to simulate the input/output impedance of the IC under test 30 by combining passive elements such as resistors, capacitors, and reactances, but distortion in the transmission line 14b due to folding cannot be avoided. do not have.

Furthermore, in the case of a general-purpose device tester system configured by dividing the main part and the dedicated part, the distortion caused by the transmission line 14b can be easily checked by expanding the check range of the main part as much as possible and expanding the versatility. If an attempt is made to achieve this, redundancy increases and the transmission path 14 tends to become longer in terms of implementation. For this reason, there is a tendency for distortion in the transmission line 14 to become even larger.

The present invention solves the problem that the conventional technology had, in that the waveform of the test signal generated by the tester and supplied to the leads of the device under test through the transmission line cannot be easily and accurately observed on the tester side. This provides a tester waveform observation method.

(Means for Solving the Problems) In order to solve the above problems, the present invention outputs a test signal corresponding to an expected value, and matches/disagrees the expected value with a response signal from a device under test. a tester body that compares and verifies the match; and a transmission device that has one end connected to the tester body and the other end connected to the device under test via an input terminal and an output terminal, and that transmits the test signal and response signal. In the device tester system equipped with the following tester waveform observation method,

That is, the tester main body is provided with a calculation means, and a calibration device having a pulse generation circuit that generates a calibration pulse and a switching circuit that switches and outputs either the calibration pulse or the test signal is connected to the input. Connect to the terminal and output terminal.

At the time of calibration, the test signal generated by the tester main body and the calibration pulse generated from the pulse generation circuit based on the test signal are switched by the switching circuit according to the test signal, and the return signal is output as the return signal. The test signal is sent back to the tester main body, and the two returned signals are calculated by the calculation means, thereby indirectly observing the test signal applied to the input terminal.

(Function) According to the present invention, since the tester waveform observation method is configured as described above, a calibration device having a pulse generation circuit and a switching circuit is prepared in advance, and when calibrating the device tester system, The calibration device is connected to the input terminal and output terminal on the other end of the transmission line.When calibrating the device tester system, a test signal is output from the tester body, and the test signal is connected to the transmission line and input terminal. Then, the pulse generation circuit in the calibration device outputs a calibration pulse, and the switching circuit performs a switching operation.In other words, this switching circuit The signal is returned as a folded signal to the tester body via the output terminal and the transmission line, and the calibration pulse generated from the pulse generation circuit is sent back as the folded signal to the tester body via the output terminal and the transmission line.

The calculation means on the tester main body inputs the two folded signals, performs calculations such as a difference calculation between the two folded signals, and works to indirectly observe the test signal applied to the input terminal. As a result, output abnormalities in the tester main body can be easily discovered, efficient calibration can be performed, and appropriate test signals can always be supplied to the device under test. Therefore,
The above problem can be solved.

(Embodiment) FIG. 1 shows an embodiment of the present invention, and is a block diagram of a device tester system for explaining a waveform observation method of a tester.

This device tester system includes a tester main body 40 that performs test signal generation, pass/fail determination, calibration, and the like. This tester main body 40 has a CPU 41 that programmably generates various signals and performs various calculations and verifications.
A calculation means 42 is connected to the CPU 41, and a driver/receiver circuit 44 is also connected via an I10 controller 43.

The calculation means 42 includes, for example, a difference calculation circuit H42a controlled by CPtJ41. The I10 controller 43 has the function of switching the buses of various signals output from the CPU 41 and distributing them to predetermined signal lines, and vice versa.
Outputs the signal to be input to 41 onto the bus and sends it to the CPU 4.
1. The driver/receiver circuit 44 includes a driver 44a that drives a test signal from the CPU 41 and outputs an analog test signal;
It is configured with a receiver 44b that receives a signal from a transmission line 50, which will be described later, and supplies it to the I10 controller 43. The output of this receiver 44b is supplied to the I10 controller 43, and is wired as a signal to be input to the CPU 41.

A test board 60 is connected to the driver/receiver circuit 44 via a transmission path 50 . The transmission line 50 includes an outbound transmission line 50a connected to the driver 44a and a return transmission line 50b connected to the receiver 44b, and is constructed using a coaxial cable or the like to reduce noise, signal reflection, etc. It is configured. The test board 60 has an input terminal 61 connected to the outgoing transmission line 50a and an output terminal 62 connected to the incoming transmission line 50b, and further has an IC under test mounted on the test board 60. An IC socket 63 is attached thereto.

This IC socket 63 has an input lead 63a and an output lead 63b, the input retro 3a is connected to the input terminal 61, and the output lead 63b is connected to the output terminal 62, respectively. When an IC to be tested (not shown) is attached to this IC socket 63, the input lead of the IC to be tested is electrically connected to the retrofit 3a, and the output lead of the IC to be tested is electrically connected to the lead 13b.

FIG. 3 is a block diagram showing an example of the configuration of a calibration device inserted into the IC socket 63 when calibrating the device tester system of FIG. 1.

This calibration device (hereinafter simply referred to as "calibration supplies")
70 includes an input door 1.72 that is connected to the input lead 63a of the IC socket 63, and a power lead 73 and a ground lead 74 that are supplied with power from the tester main body 40 through a separate system. The entrance door 1 has a pulse generation circuit 75.
, and is also connected to the input side of the switching circuit 76 , and the output side of the pulse generating circuit 75 is further connected to the input side of the switching circuit 76 .

The pulse generation circuit 75 is supplied with power from the power supply lead 73 and the ground lead 74, is triggered by a pulse signal from the entrance door 1, and outputs one calibration pulse S75 whose amplitude, rise time, etc. are accurately defined, for example. It is a circuit and consists of a multi-vibrator lighter, etc.

The switching circuit 76 is supplied with power from the power supply lead 73 and the ground lead 74, and determines whether the entrance door 2 is active or not.
Alternatively, it is a circuit that selects and outputs either the calibration pulse S75 or the signal of the input door 1 depending on whether it is inactive or not, and is composed of switching transistors, gate circuits, and the like.

An output lead 77 connectable to the output lead 63b of the IC socket 63 is connected to the output side of the switching circuit 76.

A method of observing waveforms on a desk using the device tester system configured as described above will be explained.

When calibrating the device tester system of FIG. 1, the CPU 41 is set to calibration mode using an input device such as a keyboard (not shown), and the calibration article 70 of FIG. 3 is inserted into the IC socket 63.

The test signal supplied from the CPU 41 to the entry door 2 of the calibration product 70 is activated. As a result, the switching circuit 76 enters a mode in which the output of the pulse generating circuit 75 is supplied to the exit door 7.

Next, a test signal is generated from the CPU 41 to be supplied to the entrance door 1. This test signal is composed of, for example, one pulse and serves as a trigger signal for the pulse generation circuit 75. Accordingly, this signal causes the pulse generation port n75 to output, for example, one calibration pulse 875 via the switching circuit 76. Supply to Curry Door 7. The signal supplied to the output door 7 is sent to the receiver 44b through the output terminal 62 on the test board 60 and the return transmission, Fl@50b.

The receiver 44b receives a signal from the return transmission path 50b, and stores one pulse of the received signal in the CPU 41 via the work/○ controller 43. As a method for storing this, for example, an analog/
There is a method of providing a digital converter (hereinafter referred to as an A/D converter) and a memory circuit, converting the output of the receiver 44b into a digital quantity by the A/D converter, and then storing it in the memory circuit. Accordingly, the return transmission line 50
This means that the pulse data from the pulse generation circuit 75 that has passed only b has been collected by the difference calculation circuit 42a.

Next, the test signal supplied from the CPU 4 to the entrance door 2 of the calibration product 70 is made inactive. This allows the switching circuit 76 to directly output the signal from the input door 1 to the output door 7. Again, the CPU 41 generates a test signal to be supplied to the entry door 1.

This test signal is sent to the I10 controller 43, the driver 44a, the forward transmission E@50a, and the test board 60.
Upper input terminal 61. The signal is supplied to the input door 1 via the input lead 63a of the IC socket 63, and further sent to the output lead door 7 as it is via the switching circuit 76.

The output signal of the output door 7 is sent to the output lead 63b of the C socket 63 and the test board 6 in the same manner as described above.
Output terminal 62 on 0, return transmission line 50b, receiver 4
4b, the I10 controller 43, and the CPU 41 to be stored in the differential amplification circuit 42a. The signal stored in the differential amplification circuit 42a is a signal that has passed through the outgoing transmission line 50a, the calibration product 70, and the incoming transmission line 50b.

Next, a command is issued to the 3-difference calculation circuit 42a on the CPU 41 side to calculate the difference between the pulse data that has passed only through the 1'X transmission line 50b and the pulse data that has passed through both the outbound transmission line 50a and the inbound transmission line 50b. is calculated by the difference calculation circuit 42a.

As a result, pulse data that has passed only through the outward transmission line 50a is obtained. As a result, from the tester main body 40 to the IC
This means that the pulse data at the input lead 63a of the test signal that is not output to the input lead 63a of the socket 63 can be indirectly observed by the CPU 41.

This data is collected using a memory circuit or the like when the device test system is installed, and then data is collected in the above-described calibration mode as needed and compared with each other.

That is, the stored waveform is compared with the currently measured waveform to determine whether there is an abnormality in the waveform, such as whether the amplitude has become small. Thereby, the dedicated section consisting of the transmission path 50 and the test board 60 in the device tester system can also be constantly monitored on the CPU 41 side.

Furthermore, if necessary, for example, a correction circuit for correcting the above-mentioned mutual comparison difference is provided in the arithmetic means 42 or the CPU 41, and a so-called automatic calibration is performed in which the mutual comparison difference is automatically eliminated by a command from the CPU 41. It is also possible. For example, the gain of a circuit for setting the amplitude may be manually adjusted to correct the difference in mutual comparison.

As described above, the tester waveform observation method according to this embodiment has the following advantages.

(a) When calibrating a device tester system,
A calibration component 70 prepared in advance is inserted into the IC socket 63. Then, the pulse generation circuit 75 is activated by the test signal from the CPU 41.

Furthermore, the test signal is returned as it is to the tester body 4.
0 and a mode in which the pulse S75 generated by the pulse generation circuit 75 is returned to the tester main body 40.
The mode is switched by the switching circuit 76, and the difference between the two modes is computed by the difference computing circuit 42a. This allows the CPU 41 to observe the pulses actually applied to the IC under test.

Therefore, it is possible to easily discover an abnormality in the output of the tester, to perform efficient calibration, and to provide a device tester system that can always supply an appropriate test signal to the F-IC under test.

(b) Pulse data generated by the pulse generation circuit 75 in the calibration product 70 is transmitted to the CPU in the return mode.
In order to improve measurement accuracy, it is desirable that the pulse data of the test signal generated from 41 exactly match the pulse data of the test signal. Here, the pulse width is the amplitude of the pulse with respect to the time axis.

(C) In order to improve measurement accuracy, it is desirable that the input impedance and output impedance of the pulse generation circuit 75 and the switching circuit 76 match those of the actual IC under test as much as possible.

Note that the present invention is not limited to the above embodiments, and various modifications are possible. Examples of such modifications include the following.

(i) In the above embodiment, the difference calculation circuit 42a is provided with a memory circuit for storing pulse data for one pulse (total of two pulses for the outward and return passes), and by generating a pulse only once, the pulse data However, the present invention is not limited to this. For example, by setting the number of pulse occurrences to multiple times, collecting the pulse amplitude at a fixed sample time each time, and gradually moving this sample time for each pulse occurrence, the final number of pulses is 1. - It is also possible to collect all data for a pulse. In an ordinary general-purpose device tester system, the above-mentioned pulse amplitude detection function by moving the sample time and scanning is provided as a standard feature, so this method is easier to implement.

(ii) In the above embodiment, first, the return transmission line 50I
Although data collection is performed for ll, and then data collection is performed for both the outbound transmission line 50a and the return transmission line 50b, the present invention is not limited to this. For example, the same advantages as in the above embodiment can be obtained by performing data collection in the reverse order or by performing them alternately.

(iii) In the above embodiment, during calibration, the calibration article 70 is inserted into the IC socket 63 to collect pulse data, but the present invention is not limited thereto.

For example, this calibration article 70 is mounted on the test board 60 as a standard, and during calibration, a switching circuit (not shown) or the like is used to change the access from the tester main body 40 to the IC under test, which is the original purpose, to this strict article 70. You may also switch to access. Thereby, the operation of attaching and detaching the calibration article 70 can be omitted.

(IV) In the above embodiment, power is supplied to the power supply lead 73 and the ground lead 74 of the calibration article 70 from the tester body 40 side, but it is also possible to supply power from a separate power supply prepared separately. This can be used, for example, when supplying power from the tester main body 40 side causes noise and the like, making it impossible to perform sufficiently high-precision observations.

(V) In the above embodiment, a waveform observation method for an IC under test has been described, but the present invention can also be applied to devices other than ICs to determine whether they are good or bad and to calibrate a tester. In addition, in FIG. 1, the calculation means 42 is provided outside the CPU 41, but the calculation means 42
may be provided within the CPU 41. Furthermore, the tester body 4
0 can be modified in various ways, such as by using other control circuits instead of the CPU 41.

(Effects of the Invention) As described in detail above, according to the present invention, the calibration device is placed, for example, in or near the device under test, and during calibration, the test signal generated by the tester main body and the The pulse generated by the pulse generation circuit in the calibration device using the test signal as a trigger is switched by the switching circuit in the calibration device, and sent back to the tester body as a return signal. Added the ability to calculate return signals. As a result, on the tester main body side, the waveform of the test signal actually applied to the device under test 1, for example, on the lid or in its vicinity, can be
Can be observed indirectly. Therefore, transmission distortion on the outward path can be observed, and abnormalities in the output of the tester can be easily discovered.

Note that transmission distortion on the return path can be easily determined by measuring the output of the pulse generation circuit on the tester main body side.

In this way, abnormalities in the output of the tester can be easily discovered, so that the device tester system can be calibrated easily and efficiently. Therefore, an appropriate test signal is always supplied to the device under test, and the quality of the device under test can be determined with high accuracy.

[Brief explanation of the drawing]

Fig. 1 shows an embodiment of the present invention, and is a block diagram of a device tester system for explaining the waveform observation method of the tester, and Fig. 2 shows a conventional device tester system for determining the quality of a device under test. System block diagram, 3rd
The figure is a block diagram of a calibration device used in an embodiment of the invention. 40... Tester body, 41... CPU
, 42... calculation means, 43... I10 controller, 44... driver/receiver circuit, 50...
...Transmission line, 50a...Outbound transmission line, 50
b... Return transmission line, 60... Test board, 61-... Input terminal, 62...
・Output terminal, 63...IC socket, 63a・
...Input lead, 63b... Output lead, 70... Calibration device (calibration supplies),
75・Pulse generation circuit, 76...Switching circuit.

Claims (1)

[Scope of Claims] A tester main body that outputs a test signal corresponding to an expected value and compares and matches whether the expected value and a response signal from a device under test match, and one end of which is connected to the tester main body. a transmission path for transmitting the test signal and the response signal, the other end of which is connected to the device under test via an input terminal and an output terminal; and a calibration device having a pulse generation circuit that generates a calibration pulse and a switching circuit that switches and outputs either the calibration pulse or the test signal, connected to the input terminal and the output terminal, During calibration, the test signal generated by the tester main body and the calibration pulse generated from the pulse generation circuit based on the test signal are switched by the switching circuit according to the test signal, and the test signal is returned to the tester main body as a return signal. A method for observing waveforms of a tester, characterized in that the two returned signals are calculated by the calculation means, and the test signal applied to the input terminal is indirectly observed.