JPH04119589A - Intermediate potential generating circuit and dynamic semiconductor storage device using the same - Google Patents

Abstract

PURPOSE:To contrive a compatibility for low power consumption and high speed responsiveness by increasing the current amount of current source circuit for a 1st or 2nd differential amplifier circuit in accordance with the potential obtained at the output terminal of an output circuit. CONSTITUTION:Feed-through currents of the differential amplifier circuits 31, 32 controlling the output circuit l are controlled in accordance with the state of outputted intermediate potential. That is, when the intermediate potential is out of the region between a 1st reference potential of the lower side and a 2nd reference potential of the higher side which put the desirable intermediate potential between both sides, i.e., an insensible band (normal condition), the output circuit 1 is controlled to charge or discharge, and further when it becomes lower than a 3rd reference potential which is lower than the 1st reference potential or becomes higher than a 4th reference potential which is higher than the 2nd reference potential, the control is performed so that the feed-through currents of the 1st and 2nd differential amplifier circuits 31, 32 are respectively made to increase. Consequently, when the outputted intermediate potential is varied, the output circuit 1 is controlled by the differential amplifier circuit 31(32) in which the feed-through current is increased, and in the normal condition, mean while, the feed-through currents of differential amplifier circuits 31, 32 are maintained to be small. Thus, the high speed feature and low power consumption can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention (Field of Industrial Application) The present invention relates to an intermediate potential generation circuit configured within an integrated circuit chip and a dynamic semiconductor memory device using the same.

(Prior Art) A circuit that generates an intermediate potential between a power supply potential Vcc and a ground potential VSS is often required inside an integrated circuit chip.

For example, in a dynamic semiconductor memory device (DRAM), there is a precharge potential generation circuit for precharging bit lines and the like to (1/2) Vcc.

Conventionally, as such an intermediate potential generation circuit, ′! The one shown in Figure s9 has been proposed. This includes an output circuit 1 in which a charging p-channel MOS transistor Q1 and a discharging n-channel MOS transistor Q2 are connected in series between a power supply potential VCC and a ground potential vSS, and an output circuit 1 having an output terminal 2 connected to a load. It has a first differential amplifier circuit 31 and a second differential amplifier circuit 32. The reference input terminals of the first differential amplifier circuit 31 and the second differential amplifier circuit 32 receive the first reference potential VREPI and the second reference potential VREF2 from the reference potential generation circuit 4 by resistance division, respectively. is input. First reference potential V. , 1 are set to a certain value lower than a desired intermediate potential, for example (1/2) Vcc,
The second reference potential V REP2 is set to a certain value higher than the intermediate potential. 1st. A constant bias is applied by the bias circuit 5 to the current source transistors of the second differential amplifier circuits 31 and 32.

The operation of this intermediate potential generation circuit is as follows.

In a steady state, that is, in a state where the output potential of the output circuit 1 is between the first reference potential VREPI and the second reference potential V2, the two MOS transistors Ql,
Both Q2 are off. When the output potential decreases and becomes lower than the first reference potential VREF+, the first differential amplifier circuit 3
1 determines this and turns on the p-channel MOS transistor Q1 of the output circuit 1. As a result, the power supply potential VC
The load is charged from C, and the decreased output potential increases. The output potential rises to the second reference potential V REP2
If it exceeds this, the second differential amplifier circuit 32 determines this and turns on the n-channel MOS transistor 2 of the output circuit 1. As a result, the load is discharged, and the increased output potential is lowered. In this way, in this intermediate potential generation circuit, the first reference potential VRRP+ and the second reference potential VR
An operation is performed in which the period between BP2 is set as a dead zone, and when the output potential deviates from this range, this is automatically compensated for.

This intermediate potential generation circuit uses a differential amplifier circuit, so it has a large driving capacity, and uses a reference potential by resistor division, so the reference potentials V REPI, V
REF2 is affected by variations in process parameters.
< has the advantage of being able to generate a stable potential. However, there are still problems when applying this to, for example, next-generation large-scale DRAMs of 16M or 64M bits.

This is because it is difficult to simultaneously satisfy the requirements of high-speed response and low power consumption. That is, as is clear from the configuration of FIG. 9, this intermediate potential generation circuit has the first. Through current flows through four locations: the second differential amplifier circuit 31 and 32, the reference potential generation circuit 4, and the bias circuit 5. It is possible to reduce power consumption to some extent by optimizing the dimensions of the elements that make up the circuit. However, if the through current of the differential amplifier circuit is set to a small value, the driving ability will decrease and sufficient high-speed response cannot be obtained.

(Problems to be Solved by the Invention) As described above, the intermediate potential generation circuit using the differential amplifier circuit proposed in the past has the problem of not being able to satisfy the conditions of low power consumption and high-speed response at the same time. there were.

SUMMARY OF THE INVENTION An object of the present invention is to provide an intermediate potential generation circuit that controls through current according to operating conditions to reduce overall power consumption and achieves high-speed performance.

Another object of the present invention is to provide a DRAM using the above-described intermediate potential generation circuit as a precharge potential generation circuit.

[Structure of the Invention] (Means for Solving Issues) An intermediate potential generation circuit according to the present invention includes a charging transistor and a discharging transistor that are connected in series between a power supply potential and a ground potential and are off in a steady state. a first reference potential lower than the intermediate potential and higher than the ground potential; and a second reference potential higher than the intermediate potential and lower than the power supply potential. a reference potential generation circuit that generates a reference potential of , and a current source circuit, a first reference potential of the reference potential generation circuit is input to a reference input terminal, and an output terminal of the output circuit is connected to a signal input terminal. , a first differential amplifier circuit whose output terminal is connected to the gate of the charging transistor and turns on the charging transistor when the intermediate potential becomes lower than the first reference potential; and a current source. The second reference potential of the reference potential generation circuit is input to the reference input terminal, the output terminal of the output circuit is connected to the signal input terminal, and the output terminal is connected to the gate of the discharge transistor. , when the intermediate potential becomes higher than the second reference potential, the discharge MO8
) when the potential obtained at the output terminal of the second differential amplifier circuit that turns on the transistor and the output circuit becomes equal to or lower than the third reference potential of the reference potential generation circuit that is lower than the first reference potential; The amount of current in the current source circuit of the second differential amplifier circuit is increased, and when the current amount becomes equal to or higher than the fourth reference potential of the reference potential generation circuit, which is higher than the second reference potential, the first
A through-current control means for controlling to increase the amount of current of the current source circuit of the differential amplifier circuit.

A DRAM according to the present invention includes a memory cell array in which a plurality of word lines and a plurality of bit line pairs are arranged in an intersecting manner, and dynamic memory cells are arranged at the intersecting positions, and the bit line pairs are connected to each other during a precharge period. The present invention is characterized in that it has a precharge potential generation circuit for precharging to an equal intermediate potential, and that the above-described intermediate potential generation circuit is used as the precharge potential generation circuit.

(Function) In the intermediate potential generation circuit according to the present invention, the through current of the differential amplifier circuit that controls the output circuit is controlled according to the state of the output intermediate potential. In other words, when the intermediate potential leaves the dead zone (steady state) region between the lower first reference potential and the higher second reference potential that sandwich the desired intermediate potential, the output circuit is controlled to charge or discharge. is performed, and the voltage is further lower than the third reference potential which is lower than the first reference potential, or the second reference potential is lower than the first reference potential.
When the voltage reaches the fourth reference potential which is higher than the reference potential of the first . Control is performed to increase the through current of the second differential amplifier circuit. Therefore, when the intermediate potential to be output fluctuates, the output circuit is controlled by the differential amplifier circuit with increased through current, so that the fluctuation can be compensated for at high speed. On the other hand, in a steady state, the through current of the differential amplifier circuit is kept small, so the overall power consumption is kept at a small level.

Furthermore, the DRAM according to the present invention can achieve high-speed performance and low power consumption characteristics by using the above-described intermediate potential generation circuit as a precharge potential generation circuit for bit lines and the like.

(Example) The present invention will be explained in detail below.

FIG. 1 shows the configuration of an intermediate potential generation circuit according to one embodiment, and FIG. 2 shows a more specific configuration of this. This intermediate potential generating circuit includes an output circuit 1 for outputting, for example, (1/2) Vcc as an intermediate potential, and a first circuit to which the output potential of this output circuit 1 is fed back and outputs a signal for controlling the output circuit 1.
．． Similarly, the output potential of the output circuit 1 is fed back to the second differential amplifier circuits 31 and 32, and the output potential of the output circuit 1 is fed back to the second differential amplifier circuits 31 and 32. A third . Fourth differential amplifier circuit 33, 34
, a reference potential generation circuit 4 that generates reference potentials required as reference inputs of these differential amplifier circuits 31 to 34, respectively;
1st. Current source circuit 6 of the second differential amplifier circuit 31, 32,
7 includes a bias circuit 5 and the like that applies a bias so that a constant current flows in a steady state.

Output circuit 1 includes a charging p-channel MOS transistor Q connected in series between power supply potential VCC and ground potential VS2.
1 and an n-channel MOS transistor RO 2 for discharging. These MOS transistors Q1. Q
2 connection point or output terminal 2. The reference potential generation circuit 4 includes five resistors R1 between the power supply potential VCC and the ground potential 788.
~R5 are connected in series. The node N3 closest to the ground terminal has a third voltage lower than (1/2) Vcc.
A reference potential VREF3 is obtained, and a fourth reference potential VREF4 higher than (1/2) Vcc is obtained at the inode N4la closest to the power supply terminal. The second node Nil: on the ground side is a first reference potential VREF that is lower than (1/2) vCC and higher than the third reference potential VRP, P3.
I is obtained, and the second node N2 on the power supply side has (1/
2) A second reference potential VRHP2 higher than Vcc and lower than the fourth reference potential vREF4 is obtained.

The first differential amplifier circuit 31 includes n-channel MOS transistors Qll and Q12 as differential transistors, and p-channel MOS transistors Q13 . This is a current mirror type CMO5 differential amplifier circuit in which a current mirror circuit is configured by Q14. The current source circuit 6 of the first differential amplifier circuit 31 includes a differential transistor Q11. It consists of two n-channel MO8) transistors Q15.016 connected in parallel between the common source of Q12 and the ground terminal. The first reference potential V from the reference potential generation circuit 4 is applied to the reference input terminal of the differential amplifier circuit 31, that is, the gate of the MOS transistor Qll. , 1 are input, and the output terminal 2 of the output circuit 1 is fed back and input to the signal input terminal, that is, the gate of the MOS transistor Q12.

The output terminal of the first differential amplifier circuit 31 is connected to the gate of the p-channel MOS transistor Q1 of the output circuit 1. The second differential amplifier circuit 32 includes p-channel MOS transistors Q21. Q22 is a differential transistor,
n-channel MOS transistor Q23. Current mirror type CMO with a current mirror circuit configured by Q24
5 differential amplifier circuit. The current source circuit 7 of this second differential amplifier circuit 32 includes differential transistors Q21. Two p-channel MOS transistors Q25.Q22 are connected in parallel between the common source of Q22 and the power supply terminal. It is composed of Q2B. The second reference potential VIIIP2 from the reference potential generation circuit 4 is input to the reference input terminal of the differential amplifier circuit 32, that is, the gate of the MOS transistor Q21, and the second reference potential VIIIP2 from the reference potential generation circuit 4 is input to the signal input terminal, that is, the gate of the MOS transistor Q22. Output terminal 2 is fed back and input. The output terminal of this second differential amplifier circuit 32 is connected to the gate of the n-channel MOS transistor RO 2 of the output circuit 1.

These first. One MOS transistor Q15 forming each current source circuit 6, 7 of the second differential amplifier circuit 31, 32
．． Q25 is the 1st. Second differential amplifier circuit 31
．． This is for setting the through current in the steady state of 32, and a constant bias is applied by the bias circuit 5. Here, the bias circuit 5 is configured by a diode-connected p-channel MOS transistor Q51 and an n-channel MOS transistor Q52 connected in series between a power supply potential VCC and a ground potential 788 with a current limiting resistor R6 in between. . Then, from the power supply potential vcc to MO
The potential reduced in absolute value of the threshold value of the S transistor Q51 is applied as a bias to one current source MOS transistor Q25 of the second differential amplifier circuit 32. Further, a potential higher than the ground potential by the threshold of the MOS transistor Q51 is applied to one current source Mo of the first differential amplifier circuit 31.
It is applied as a bias to the gate of the s-transistor Q15.

1st. Each current source circuit 6 of the second differential amplifier circuit 31 and 32
, 7)) transistor Q 16.
Q28 is used to compensate for fluctuations in the output potential of the output circuit 1. They are for increasing the through current of the second differential amplifier circuits 31 and 32, respectively.
It is controlled by a fourth differential amplifier circuit 3334. The third differential amplifier circuit 33 includes p-channel MO8) transistors Q31 . Q32 and an n-channel MOS transistor Q forming a current mirror circuit 33. This is a current mirror type CMOS differential amplifier circuit constituted by Q34 and a p-channel MOS transistor Q35 for a current source. The reference input terminal, that is, the gate of the MOS transistor Q31 is connected to the third reference potential VRBF from the reference potential generation circuit 4.
3 is input, and the output terminal 2 of the output circuit 1 is fed back to the signal input terminal, that is, the gate of the MOS transistor Q32. Current source MO3) A constant bias on the high potential side of the bias circuit 5 is applied to the gate of the transistor Q35.

The pressure terminal of the third differential amplifier circuit 33 is connected to the gate of the other MOS transistor Q1B of the current source circuit 6 of the first differential amplifier circuit 31. The fourth differential amplifier circuit 34 includes n-channel MOS transistors Q41 . Q42 and a p-channel MOS transistor 043. which constitutes a current mirror circuit. Q44
, and n-channel MOS transistor Q4 for current source.
5. Its reference input terminal i.e. M
The fourth reference potential V1, 4 from the reference potential generation circuit 4 is input to the gate of the OS transistor Q41, and the output terminal 2 of the output circuit 1 is fed back to the signal input terminal, that is, the gate of the MOS transistor Q42. There is.

A constant bias on the low potential side of the bias circuit 5 is applied to the gate of the current source MOS transistor Q45. The output terminal of the fourth differential amplifier circuit 34 is connected to the gate of the other MOS transistor Q26 of the current source circuit 7 of the second differential amplifier circuit 32.

The operation of the intermediate potential generation circuit configured in this way is explained in the third section.
This will be explained next with reference to the figures. Figure 3 shows the relationship between the output potential vO and the charging/discharging current by the output circuit 1, and the output potential vO
and 1st. It shows the relationship between the through currents of the second differential amplifier circuits 31 and 32. In this intermediate potential generation circuit, the through current of the first and second differential amplifier circuits 31 and 32 that control the output circuit 2 is small in a steady state, as shown in FIG.
When performing output compensation, control is performed to increase the output. First, the output potential ■0 obtained at the output terminal 2 is (1/
2) Consider the steady state at or near Vcc. That is, the range in which the output potential vO is higher than the reference potential VRHFI of '1a1' from the reference potential generation circuit 4 and lower than the second reference potential ■REP□ is the steady state (dead zone) of the output. The output potential vO is the reference potential VRI of I@1!
Higher than Pi, the second reference potential VRI! When the range is lower than P2, the output v3 of the third differential amplifier circuit 33 is 4
It is L level. Therefore, at this time, one MOS transistor Q1B of the current source circuit 6 of the first differential amplifier circuit 31 is turned off. Also, the fourth differential amplifier circuit 3
The output 4 of 4 is at "H" level, so that one current source MOS transistor Q of the second differential amplifier circuit 32
2B is still turned off. In other words, the through current of the first differential amplifier circuit 31 is kept at a small level determined by the other current source MOS transistor Q15 biased near the threshold value. The through current of the second differential amplifier circuit 32 is also kept at a small level determined by the current source MOS transistor Q25 biased near the threshold value. Third. Fourth differential amplifier circuit 33.34
Also, those current source transistors Q35゜Q4
5 are biased near their respective threshold values, and the through current is small. In addition, in this steady state, the MOS transistor Q1. Both Q2 are off, and no through current flows here either.

The output potential vO decreases and this becomes the first reference potential VRK.
When it becomes lower than P+, the output v of the first differential amplifier circuit 31
1 becomes 'L Lebel. As a result, the p-channel MOS transistor Ql on the power supply side of the output circuit 1 is turned on, and as shown in FIG. 2, the load connected to the output terminal 2 is charged from the power supply potential VCC, and the drop in output potential is compensated for. Ru. At this time, the output potential VO further decreases to the third reference potential ■, +1. When the current source transistor Q1B of the first differential amplifier circuit 31 is turned on, the output of the third differential amplifier circuit 33 becomes "H" level. Immediately after the potential vO decreases and the output circuit 1 starts charging as shown in FIG. 3, the first differential amplifier circuit 31 that drives the output circuit 1 is set to a state where the through current is large. As the through-current of the first differential amplifier circuit 31 increases in this manner, its current driving ability improves, thereby ensuring high-speed performance of the charging operation by the output circuit 1 driven.

The operation is similar when the output potential vO increases. When the output potential VQ becomes higher than the second reference potential VR1F2,
The output v2 of the second differential amplifier circuit 32 becomes H" level. As a result, the n-channel MOS transistor 2 of the output circuit 1 is turned on, the load connected to the output terminal 2 is discharged, and the output potential The increase is compensated for.At this time, when the output potential vO further increases and crosses the fourth reference potential VREPa, the output v4 of the fourth differential amplifier circuit 34 goes to "L" level, which causes the second The other current source transistor Q2B of the differential amplifier circuit 32 is turned on.That is, the output potential vO rises, and immediately after the output circuit 1 starts discharging as shown in FIG. The second differential amplifier circuit 32 that drives the second differential amplifier circuit 32 is set to a state where the through current is large.As the through current of the second differential amplifier circuit 32 becomes large in this way, as in the case of a potential drop, High-speed performance of the discharge operation by the output circuit 1 is ensured.

As described above, in the intermediate potential generation circuit according to this embodiment,
In a state where high-speed responsiveness of the circuit is not required, that is, when the output potential vO is in the dead zone, the differential amplifier circuit is maintained in a state where almost no current flows. The through current of the differential amplifier circuit is controlled to be large near the end of the dead zone where high-speed response is required. This provides an intermediate potential generation circuit with low power consumption and excellent high-speed performance.

By the way, in the present invention, as shown in the embodiment of FIG.
The first one controls the output circuit. 3. Control the through current outside the allowable range determined by the second reference potential. A fourth reference potential is set. Therefore, no through current flows unnecessarily, and power consumption can be reduced. When the output potential fluctuates, the first or second differential amplifier circuit 31 or 32 starts operating, but initially these differential amplifier circuits are in a state where the through current is small, and immediately after that the output potential becomes permissible. When the voltage exceeds the range and changes to the outside of the third or fourth reference potential, the third or fourth differential amplifier circuit operates to increase the through current.

In this case, there may be a delay in the operation of returning to the intermediate potential. In other words, even if the output potential deviates significantly from the intermediate potential and the output circuit and current source circuit are controlled and the output potential starts to return, the potential is not within the desired tolerance range and is between the first reference potential and the third reference potential. When the voltage is stabilized between the reference potentials or between the second and fourth reference potentials,
Since the through current is already small in those areas, it will take time to return to the desired tolerance. An embodiment that improves this point will be described below.

FIG. 4 shows an intermediate potential generation circuit of such a second embodiment. Portions corresponding to those in FIG. 1 are designated by the same reference numerals as in FIG. 1, and detailed description thereof will be omitted. In this embodiment, the third. The fourth differential amplifier circuits 33 and 34 and the first differential amplifier circuits 33 and 34 controlled by these. Second differential amplifier circuit 31
．． A gate voltage control circuit 89 is provided between the 32 current source transistors QlB and Q2[i, which functions to delay the end of the on-drive signal. Gate voltage control circuit 8
is composed of a delay circuit gl, a NOR gate 82, and an inverter 83. The gate voltage control circuit 9 is
Delay circuit 91. NAND gate 92 and inverter 9
It is composed of 3.

The operation of the intermediate potential generation circuit according to this embodiment is as follows. As in the previous embodiment, when the output potential vO falls below the first reference potential VREFI, the first differential amplifier circuit 3
1 becomes the "L" level, and the p-channel MOS transistor Ql of the output circuit 1 is turned on. This compensates for the drop in output potential. When the output potential VO further decreases and crosses the third reference potential V REP3, the output v3 of the third differential amplifier circuit 33 becomes "H" level, which directly passes through the gate voltage control circuit 8 and becomes the first voltage. The other current source transistor Ql of the differential amplifier circuit 31
B is turned on. The output potential recovers to the third reference potential VRI! When the voltage exceeds P3, the output of the third differential amplifier circuit 33 becomes "L" level. At this time, the output of the gate voltage control circuit 8 returns to the "L° level" because the delay circuit 8
Delayed by 1 delay time. That is, the end of the on-drive signal for transistor Q1B (current source MOS transistor) is delayed by that amount, and then MOS transistor QIB is turned off.

The operation is similar when the output potential vO increases. When the output potential ■0 becomes higher than the second reference potential ■□εP2,
The output v2 of the second differential amplifier circuit 32 becomes "H level". As a result, the n-channel MOS transistor Q2 of the output circuit 1 is turned on, the load connected to the output terminal 2 is discharged, and the output potential At this time, when the output potential vO further increases and crosses the fourth reference potential vREF4, the output of the fourth differential amplifier circuit 34 becomes "L" level, and this is directly controlled by the gate voltage control. The other current source transistor Q2B of the second differential amplifier circuit 32 is turned on through the circuit 9. The pressure potential is restored and the fourth
When the reference potential "REF4" becomes lower than "REF4", the output of the fourth differential amplifier circuit 34 becomes "H" level. At this time, the output of the gate voltage control circuit 9 returns to "H2 level" due to the delay of the delay circuit 91. After a delay of time, MOS transistor Q2G is turned off.

Thus, according to this embodiment, low power consumption and high-speed response can be obtained as in the previous embodiment. Particularly in the case of this embodiment, the first. Second differential amplifier circuit 31.
By supplying the signals for driving the 32 current source circuits for a certain period of time even after the signals for turning on the 32 current source circuits fall, the output potential can be restored quickly. In other words, the through current is prevented from becoming low before the output potential becomes sufficiently stable, thereby ensuring high speed recovery of the output potential.

FIG. 5 shows an intermediate potential generation circuit of the third embodiment. Its basic configuration is the same as the embodiment shown in FIG.

However, unlike FIG. 1, in this embodiment, the highest level fourth reference potential VREF4 is input to the reference input terminal of the third differential amplifier circuit 33, and the fourth reference potential VREF4 of the output circuit 1 is input to the signal input terminal. The output terminal of the first differential amplifier circuit 31, that is, the gate terminal of the p-channel MOS transistor RO 1 is connected to the reference input terminal of the fourth differential amplifier circuit, not the output terminal. Level 3rd reference potential V
REP3 is input, and the output terminal of the second differential amplifier circuit 34 is connected to the signal input terminal. Fourth reference potential VRI! P4 is Vc, where the threshold voltage of p-channel MOS transistor RO1 of output circuit 1 is Vthp.
e −V ap, p4 to l V thp are set.

Further, the third reference potential VRIIP3 sets the threshold voltage of the n-channel MOS transistor Q2 of the output circuit 1 to V t
hn is set to V Rap3 to V thn.

The operation of the circuit of this embodiment is also basically the same as that of the previous embodiment. In this embodiment, when the first differential amplifier circuit 31 drives the p-channel MOS transistor Q1 of the output circuit 1 to charge it, the third differential amplifier circuit 31 drives the p-channel MOS transistor Q1 of the output circuit 1 to charge the third differential The output of the amplifier circuit 33 is “H”
current source MO of the first differential amplifier circuit 31.
The S transistor Qlft is turned on. Further, the second differential amplifier circuit 32 is an n-channel MOS of the 8-power circuit 1.
) When the transistor Q2 is driven to discharge, the output of the fourth differential amplifier circuit 34 is maintained at "H" level until the n-channel MOS transistor Q2 is turned off, and the output of the second differential amplifier circuit 32 is Current source MOS transistor Q2B is turned on.

Therefore, as in the embodiment shown in FIG. 4, the first differential amplifier circuit 31 or the second differential amplifier circuit 32 is maintained in a state where the through current is large until the output potential is restored, and the potential of the output terminal 2 is High-speed recovery is ensured.

FIG. 6 shows an intermediate potential generation circuit of the fourth embodiment. This is an embodiment in which the embodiment shown in FIG. 5 is modified to obtain the same effect as the embodiment shown in FIG.

The third reference potential vREP3 is inputted to the inverting input terminal of the third differential amplifier circuit 33 as a reference input terminal, and the output potential of the output terminal 2 is inputted to the signal input terminal. A two-man power NOR gate 10 is provided between the output terminal of the third differential amplifier circuit 33 and the current source circuit 6. This NA
A first differential amplifier circuit 31 is connected to the input terminal of the ND gate 10.
The output terminal of , that is, the gate terminal of p-channel MOS transistor Ql of output circuit 1 is connected. The differential amplifier circuit 34 at tJ4 uses the inverting input terminal as a reference input terminal and applies the fourth reference potential VRE? is input, and the output potential of the output terminal 2 is input to the signal input terminal. A two-man power NOR gate 11 is provided between the output terminal of the fourth differential amplifier circuit 34 and the current source circuit 7. One input terminal of this NOR gate 11 is connected to the output terminal of the second differential amplifier circuit 32, that is, the gate terminal of the n-channel MOS transistor Q2 of the output circuit 1.

This embodiment also allows the same operation as the embodiment shown in FIG. That is, the potential of the output terminal 2 is the third reference potential VR1! When it becomes lower than P3, the output of the third differential amplifier circuit 33 becomes "H" level, and the other NAN
The input of the D gate 10 is “L” of the first differential amplifier circuit 31
Since it is a level output, the output of the NAND gate 10 is “H”.
"Depending on the level, the n-channel MOS transistor Q1B of the current source circuit of the first differential amplifier circuit 31 is turned on. The potential of the output terminal 2 is set to the third reference potential V REF3
Even if the output of the third differential amplifier circuit 33 becomes "L" level as the voltage becomes higher, the output of the first differential amplifier circuit 31 remains "L" level while it is lower than the first reference potential VREF+. During this period, the output of the NAND gate 10 is kept at the "H" level, and the n-channel MOS transistor 01B is kept in the on state. - When the potential of the power output terminal 2 becomes higher than the fourth reference potential VRI!Pa, The output of the fourth differential amplifier circuit 34 is "L".

level, which turns on the p-channel MOS transistor Q2B of the current source circuit of the second differential amplifier circuit 32 via the NOR gate 11. Even if the potential of the output terminal 2 becomes lower than the fourth reference potential VR and 24 and the output of the fourth differential amplifier circuit 34 becomes "L" level, as long as it is higher than the second reference potential VR1F2, the NOR The output of gate 11 is kept at the "L" level, and p-channel MO8) transistor Q2B is kept on.

FIG. 7 shows an intermediate potential generation circuit of the fifth embodiment. This is a modification of the embodiment shown in FIG. 4, and a fifth differential amplifier circuit 35. A sixth differential amplifier circuit 36 and current source MOS transistors Q17 .
Q27 is added. Fifth differential amplifier circuit 35
The non-inverting input terminal is used as a reference input terminal, and the "H0 level potential of the bias circuit 5, that is, the absolute clavicle lower value of the threshold voltage of the n-channel MOS transistor from Vcc is inputted here, and the first signal input terminal is inputted to the signal input terminal. The output of the differential amplifier circuit 31 is input, and the output of this fifth differential amplifier circuit 35 is input to the MOS transistor Q added to the current source circuit 6.
It is input to 17 gates. Sixth differential amplifier circuit 3
Similarly, B also uses the non-inverting input terminal as a reference input terminal, and the "L# level potential of the bias circuit 5, that is, a value equivalent to the threshold voltage of an n-channel MOS transistor, is input here, and the second difference is input to the signal input terminal. The output of the dynamic amplifier circuit 32 is inputted, and the output of this sixth differential amplifier circuit 3B is inputted to the gate of the MOS transistor Q27 to which the current source circuit 7 is added.

In this embodiment as well, as in the embodiment shown in FIG. Or the sixth differential amplifier circuit 3G
The MOS transistors Q17 to Q27 added to the current source circuits 6 and 7 are turned on by the output of the current source circuits 6 and 7, and the through current is maintained in a large state. Therefore, the output terminal 2 returns to the intermediate potential at high speed.

FIG. 8 shows the main configuration of an embodiment in which the present invention is applied to a DRAM. The figure shows - word lines WL, a pair of bit lines BL intersecting with the word lines WL, and one dynamic memory cell arranged at the intersecting position of these. The memory cell consists of a transfer gate MOS transistor QM and a memory capacitor C2. A memory cell array is constructed by arranging a large number of such word line and bit line pairs, and arranging memory cells at their intersections. The bit line pair BL, BL is provided with a bit line sense amplifier 10 for each sub cell array, for example.

Also, set this to (1/2) Vcc for the bit line pair BL, BL.
An equalization circuit 11 for precharging is provided. The equalization circuit 11 includes MOS transistors Q61 . Q62, and a MOS transistor Q83 that short-circuits the bit line pair BL and BL. As the precharge potential generation circuit 13, any of the intermediate potential generation circuits described in each of the previous embodiments is used.

Although not shown in the figure, the precharge potential generation circuit 13
The output of the bit line pair BLBL, for example, the cell
It can also be applied to plates, I10 wires, etc.

During the precharge period, the precharge signal PRCH is “H”.
" level, and the equalization circuit 11 works. As a result, the bit line pair BL, BL has a potential VpL obtained from the precharge potential generation circuit 13 = (1/2) Vc
It is set to c. When entering the active period, the equalize circuit 11 is turned off, the bit line pair BL is placed in a floating state, and data read and write operations are performed.

In a large-capacity DRAM, the load that must be precharged to the bit line pairs, cell plates, and their intermediate potentials becomes extremely large. By using the intermediate potential generation circuit as described in the previous embodiments as a precharge potential generation circuit for such a large capacity DRAM, a high performance DRAM with low power consumption can be obtained.

The present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above in detail, the present invention provides an intermediate potential generation circuit that is advantageous when applied to a large-scale integrated circuit that achieves both low power consumption and high-speed response, and such an intermediate potential generation circuit. High performance DR using a generation circuit as a precharge potential generation circuit
AM can be provided.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an intermediate potential generating circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing a more specific example of the circuit configuration, and FIG. 3 is a diagram explaining the operation of the intermediate potential generating circuit according to the embodiment. Figure 4 is a diagram showing the intermediate potential generation circuit of the second embodiment, and Figure 5 is a diagram showing the intermediate potential generation circuit of the third embodiment. 6 is a diagram showing an intermediate potential generation circuit according to the fourth embodiment. FIG. 7 is a diagram showing an intermediate potential generation circuit according to the fifth embodiment. FIG. 8 is a diagram showing the intermediate potential generation circuit according to the fifth embodiment. Embodiments FIG. 9 is a diagram showing a conventional intermediate potential generation circuit. 1... Output circuit, Ql... p-channel MOS for charging
Transistor, Q2...N-channel MOS for discharge) transistor, 2...Output terminal, 31...First differential amplifier circuit, 32...Second differential amplifier circuit, 33...Third differential amplifier circuit Differential amplifier circuit, 34... Fourth differential amplifier circuit, 35.
...Fifth differential amplifier circuit, 36...Sixth differential amplifier circuit, 4...Reference potential generation circuit, 5...Bias circuit, 6.7...Current source circuit, 8 .9...Gate voltage control circuit, 10...NAND gate, 11...NOR
Gate. Figure Figure

Claims (7)

[Claims] (1) An output circuit that has a charging transistor and a discharging transistor that are connected in series between a power supply potential and a ground potential and are off in a steady state, and a common connection terminal of these transistors is an output terminal that outputs an intermediate potential. , a reference potential generation circuit that generates a first reference potential that is lower than the intermediate potential and higher than the ground potential, and a second reference potential that is higher than the intermediate potential and lower than the power supply potential; and a current source circuit, and has a reference input terminal. A first reference potential of the reference potential generating circuit is input, an output terminal of the output circuit is connected to a signal input terminal, an output terminal is connected to the gate of the charging transistor, and the intermediate potential is set to the first reference potential. a first differential amplifier circuit that turns on the charging transistor when the voltage becomes lower than a reference potential of the current source circuit; , an output terminal of the output circuit is connected to a signal input terminal, an output terminal is connected to the gate of the discharge transistor, and when the intermediate potential becomes higher than the second reference potential, the discharge MOS
a second differential amplifier circuit that turns on a transistor; and a second differential amplifier circuit that turns on a transistor; The current amount of the current source circuit of the second differential amplifier circuit is increased, and when the current amount reaches the fourth reference potential of the reference potential generation circuit which is higher than the second reference potential, the current amount of the current source circuit of the first differential amplifier circuit is increased. An intermediate potential generation circuit comprising: through-current control means for controlling an increase in the amount of current in a current source circuit; (2) In the through-current control means, the third reference potential is inputted to a reference input terminal, the output terminal of the output circuit is connected to the signal input terminal, and the output terminal is connected to the output terminal of the first differential amplifier circuit. a third differential amplifier circuit connected to a control terminal of the current source circuit; a reference input terminal to which the fourth reference potential is input; a signal input terminal to which an output terminal of the output circuit is connected; The intermediate potential generation circuit according to claim 1, further comprising: a fourth differential amplifier circuit connected to a control terminal of a current source circuit of the second differential amplifier circuit. (3) between the output terminal of the third differential amplifier circuit and the control terminal of the current source circuit of the first differential amplifier circuit, and between the output terminal of the fourth differential amplifier circuit and the second 3. The intermediate potential generating circuit according to claim 2, further comprising a control circuit between control terminals of the current source circuits of the differential amplifier circuit, each of which delays the end of the ON drive signal of the current source circuit. (4) In the through-current control means, the fourth reference potential is input to a reference input terminal, the output terminal of the output circuit is connected to a signal input terminal, and the output terminal is connected to the output terminal of the first differential amplifier circuit. a third differential amplifier circuit connected to the control terminal of the current source circuit; the third reference potential is input to the reference input terminal; the output terminal of the output circuit is connected to the signal input terminal; The intermediate potential generation circuit according to claim 1, further comprising: a fourth differential amplifier circuit connected to a control terminal of a current source circuit of the second differential amplifier circuit. (5) The current source circuit of the first differential amplifier circuit includes a first current source transistor to which a constant bias is applied to the gate, and a second current source transistor whose gate is controlled by the third differential amplifier circuit. The current source circuit of the second differential amplifier circuit includes a third current source transistor to which a constant bias is applied to the gate, and a current source transistor of the fourth differential amplifier circuit connected in parallel. 5. The intermediate potential generation circuit according to claim 2, comprising a parallel connection circuit of fourth current source transistors whose gates are controlled by the circuit. (6) The output circuit is configured by a series connection of a p-channel MOS transistor and an n-channel MOS transistor, the third reference potential is set near the threshold voltage of the n-channel MOS transistor, and the fourth reference potential is set near the threshold voltage of the n-channel MOS transistor. 2. The intermediate potential generating circuit according to claim 1, wherein the difference between the potential and the power supply potential is set close to the absolute value of the threshold voltage of the p-channel MOS transistor. (7) A memory cell array in which a plurality of word lines and a plurality of bit line pairs are arranged in an intersecting manner, and dynamic memory cells are arranged at the intersecting positions, and each bit line pair is set to an equal intermediate potential during a precharge period. In a dynamic semiconductor memory device having a precharge potential generation circuit for precharging, the precharge potential generation circuit includes a charging transistor connected in series between a power supply potential and a ground potential and which is off in a steady state, and a discharging transistor. an output circuit including transistors, with a common connection terminal of these transistors as an output terminal for outputting an intermediate potential; and a plurality of resistors connected in series between the power supply potential and the ground potential, the output circuit being lower than the intermediate potential. a reference potential generation circuit that generates a first reference potential higher than the ground potential and a second reference potential higher than the intermediate potential and lower than the power supply potential; and a current source circuit, and has a reference input terminal connected to the reference potential generation circuit. A first reference potential is input, an output terminal of the output circuit is connected to a signal input terminal, an output terminal is connected to the gate of the charging transistor, and the intermediate potential is lower than the first reference potential. a first differential amplifier circuit that turns on the charging transistor when the charging transistor is turned on, and a current source circuit; a second circuit to which an output terminal of an output circuit is connected, the output terminal is connected to a gate of the discharge transistor, and turns on the discharge transistor when the intermediate potential becomes higher than the second reference potential; a differential amplifier circuit; and when the potential obtained at the output terminal of the output circuit becomes equal to or lower than a third reference potential of the reference potential generation circuit, which is lower than the first reference potential, the second differential amplifier circuit increasing the amount of current in the current source circuit, and increasing the amount of current in the current source circuit of the first differential amplifier circuit when the current reaches a fourth reference potential of the reference potential generating circuit that is higher than the second reference potential; What is claimed is: 1. A dynamic semiconductor memory device, comprising: through-current control means for controlling the current.