JPH04119036A - Test method for transmission equipment interface circuit - Google Patents

Abstract

PURPOSE:To check an error generated between packages by adding a parity generator to an output section of each package being a component of a transmission line interface circuit or a subscriber line interface circuit and adding a parity checker to an input section. CONSTITUTION:An optical signal enters a photoelectric signal conversion circuit 7 of a transmission line/subscriber line interface circuit 6, in which the optical signal is converted into an electric signal. An inter-package error check means 11 adds a parity to a data and the result is inputted to a SONET termination circuit 8 of the transmission line/subscriber line interface circuit 6. The check means 11 executes a parity check to detect a data error generated between packages of the circuits 7,8 and the result is sent to a total error data integration means 12. The means 12 receives a data from the means 11 and when an error takes place in a bit corresponding to the information of the circuit 8 from the circuit 7, '1' is inserted to the bit and when no error is generated, '0' is inserted to the bit. The means 11 executes parity check to detect an error generated from an output of the circuit 8 till an output of a temporary storage memory of a cell synchronizing circuit 9.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a test method for transmission equipment interface circuits that detects errors that occur in transmission line interface circuits or subscriber line interface circuits in ATM exchanges and isolates the location where they occur. The aim is to be able to separate the occurrence site into individual packages, and ATM consists of an ATV switch circuit, a call processing device, a transmission line, or a subscriber line interface circuit.
(Asynchronous Transfer
Mode: Asynchronous transfer mode) SONET (Synchronous Transfer Mode)
When using a 0ptical network (synchronous optical network) type optical cable,
In a transmission line or subscriber line interface circuit consisting of a photoelectric signal conversion circuit, a SONET termination circuit, a cell synchronization circuit, a multiplexing/demultiplexing circuit, an optical electric signal conversion circuit, a SONET termination circuit, a cell synchronization circuit, a multiplexing/demultiplexing circuit. inter-package error detection means for detecting errors occurring between each circuit package; and all-error data integration means for integrating error detection results for each package detected by the inter-package error detection means into one data. The apparatus is configured to have an error diagnosis means for receiving the error data integrated by the total error data integration means and isolating the part of the failure that has occurred between the packages.

[Industrial Application Field] The present invention relates to a test method for a transmission device interface circuit, and more specifically, it detects an error that occurs in a transmission line interface circuit or a subscriber line interface circuit in an ATM exchange, and locates the location where the error occurs. This invention relates to a test method for a transmission device interface circuit to be isolated.

[Conventional technology]

A broadband l
Research and development of 5DN is currently being actively conducted. Among them, ATM (Asynchr.

nous Transfer Mode: Asynchronous transfer mode) transfers continuous information such as audio and moving images, CAD,
This is a technology that converts burst information such as AM data and the communication speed of each piece of information into fixed information called a cell, and then transfers the information at high speed.

The ATM switch that implements this technology is currently under development and is expected to be commercialized in the next few years7.

An ATM switch consists of a switch circuit that performs switching processing, a call processing device, a transmission line interface circuit that connects the transmission line and the switch circuit, a subscriber line interface circuit that connects the subscriber line and the switch circuit, and the like.

FIG. 4 is a configuration diagram of the transmission line interface circuit.

The transmission line interface circuit includes an opto-electrical signal converter 41 that converts optical signals and electrical signals, and a SONET (sy
nchronous opt 1ca1 netw
ork) format optical signal; a cell synchronization unit 43 that synchronizes ATM (asynchronous transfer mode) cells; The multiplexing/demultiplexing section 44 executes multiplexing/demultiplexing processing. Since the subscriber line interface circuit also has a similar circuit configuration, the configuration, operation, and conventional diagnostic method of the transmission line interface circuit will be explained here.

First, a down highway transmission line interface circuit that sends a signal output from the ATM switch 47 to the transmission line 45 as an optical signal 46 will be described.

A signal input from the ATM switch 47 to the transmission line interface circuit first enters the multiplexing/demultiplexing section 44 in the transmission line interface circuit. Downbound highway multiplex/
The separation unit 44 includes a separation device (DMX: demultip
lexer) 48 is present and separates the multiplexed signals. The separated signal is a signal in which 1-bit parity is added to 16-bit wide data.

This signal is then input to the cell synchronization section 43. The cell synchronization unit 43 uses a HEC generator (HECGEN: h
eader error check gene
later) 49, and parity check 7ka (P
C: party checker) 50, data width converter 51, erasure link store (ES: era
stic 5tore) 52, and a separation device (D
The signals separated by MX)4B proceed in this order within the cell synchronization section 43.

In ATM (asynchronous transfer mode), data is transferred in units of cells. FIG. 5 is a block diagram of the cell.

Cells are currently standardized to have a length of 53 bytes according to international standards, of which 5 bytes are used as a header 80 and the remaining 48 hides as an information field 81.

The cell input to the cell synchronization unit 43 is first input to the HEC generator (i (ECGEN) 49.HEC
The generator 49 applies HEC (head) to the input cell.
error check) 82.

HEC82 is control data for cell synchronization, and is given as one byte in the header 8o within the cell.

HE C'; The signal given HEC82 by Enele949 2 is then sent to parity checker PC50.
is input. For example, when even parity is used, the parity generator sets the parity so that the number of bits in which '1' is set among 16-bit wide data is an even number. The parity checker PC 50 determines whether or not the number of bits set to "1" among the 16-bit data + parity bit is an even number. If it is an even number, it can be determined that the data was transmitted correctly. , and if it is an odd number, it can be determined that an error has occurred during transmission.

The parity checker 50 sends "O" if the number is even, and "1" if the number is odd to the maintenance scanner (MSCN:
mattenance 5 cann e r) 5
Output to 3. The maintenance scanner MSCN 53 is, for example, a 32-bit wide data interface, and is connected so that the output of the parity checker 50 is read into one bit of the data interface. Maintenance scanner 5
3 is connected to the interface of the call processing device in the ATV switch. The call processing device has error detection software, and this software is used by the maintenance scanner 5.
3 data is read and each bit is determined. That is, if the bit to which the data of the parity checker 50 is written is '0', it is determined that there is no error in the cell data sent from the ATM switch 47. on the other hand,
1", it is determined that an error has occurred in the cell data,
Perform appropriate error handling.

The 16-bit wide cell data other than the parity bit that has passed through the parity checker 50 is then input to a data width converter 51, where it is converted from 16-bit width to 8-bit width. This is because 16-bit width processing is executed in an ATM switch to increase processing speed.

The cell data converted to 8-bit width is temporarily stored in the elastic store ES52.

ATM exchanges are asynchronous, while SONET is synchronous, so the clocks inside and outside the exchange are different. The elastic store ES52 is placed to absorb this difference in clock time between the internal and external clocks.

The 8-bit wide cell data once stored in the elastic store ES52 is then transferred to the 5ONNET termination unit 4.
2 is input. The SONET termination section 42 consists of a down highway SONET termination circuit 54. down highway S
The ONET termination circuit 54 is an overhead inserter (OHI).

ver head 1nsertor), a scrambler (SCR:scrambler), and an alarm instruction signal inserter (AIS INS:alarm 1).
indication signal insertor
).

The 8-bit cell data is first assembled into SONET format data by an overhead inserter OHI. Then, the information field is scrambled by a scrambler SCR. If the optical signal is constant, for example, if there is no signal, the clock for extracting data cannot be extracted as it is. The scramble is
This means putting a certain signal into the information field so that the clock can be extracted even in such cases.

Next, the alarm indication signal inserter (AISINS) adds the scrambled signal to the alarm indication signal (AISINS).
:alarm 1 indication sign
a 1) Insert 55. This completes the SONET data.

The 8-bit signal output from the downlink highway SONET termination circuit 54 is input to the opto-electrical signal converter 41, and first, the 8-bit parallel signal is converted into a serial signal by the parallel-to-serial converter 56.

The serial signal is then converted into an optical signal 46 by an electrical/optical signal conversion circuit 57 and sent to a transmission line 45.

Next, a transmission line interface circuit that receives the optical signal 46 from the uplink highway, that is, the transmission line 45, and interfaces with the ATV switch 47 will be described.

The optical signal 46 transmitted through the transmission line 45 is first input to the opto-electrical signal converter 41 of the transmission line interface circuit. The optical/electrical signal converter 41 includes an optical/electrical signal converter (0/E) 58 and a serial/parallel converter 59. The input optical signal 46 is converted into an electrical signal by an optical/electrical signal conversion circuit (0/E) 58. This electrical signal is a serial signal, which is converted into a parallel signal by a serial/parallel converter 59. In this case, it is converted to 8-pin parallel data.

The 8-pin parallel data is then input to SONET termination 42. Uplink highway SONET termination circuit 60 and alarm sign data (ALM 5
ND) Consists of 61. The SONET termination circuit 60 also includes a synchronous circuit (SYNC), a descrambler (DSCR), and a descrambler (DSCR).
er), alarm detection circuit (ALM DET:ala
rmdetector), overhead access circuit (OHA)
Consisting of

The 8-bit data is input to the uplink highway SONET termination circuit 60, and synchronization is first established by a synchronization circuit (SYNC). Then, the descrambler (DSCR) restores the scramble that the scrambler (SCR) of the down highway SONET termination circuit 54 applied to the data in the information field to its original value. Furthermore, the alarm detection circuit (ALM DET) detects frame synchronization and AIS (alarm indicator).
ionsignal), and the overhead access circuit (OHA) performs SONET overhead processing.

Abnormal information such as frame synchronization detected by the alarm detection circuit (ALM DET), AIS included in the input SONET data, and line abnormalities detected during overhead processing is sent to the alarm sign data (ALM DET).
LM SND: alarm sign data
)61. Abnormality information found in the optical/electrical signal conversion circuit 5th processing of the optical/electrical signal converter 41 is also sent to this alarm sign data (ALM 5ND) 61.

Alarm sign data (ALM 5ND) 61 analyzes this abnormality information and sends it to the maintenance scanner MSC.
Insert the value '1゜"0゛ into the corresponding bit of N53.

SONET (7) by the overhead access circuit (OHA) of the uplink highway SONET termination circuit 60
, t-ha head processed 8-bit data is
Next, the signal is input to the cell synchronization section 43.

The cell synchronization unit 43 has an elastic store (ES) 6
2. Data width converter 63, parity generator (
PG: parity generator) 64, cell synchronizer (CELL 5YNC: cell 5yn
chronous) consists of 65.

The 8-bit data is first stored in elastic store E.
Temporarily stored in S62, SONET clock and A
The time difference between TM (asynchronous transfer mode) clocks is absorbed. Next, the data width converter 6-3 converts the data width from 8 bits to 16 bits. That is, two pieces of 8-bit data are arranged to form 16-bit data. This is to speed up the exchange process by processing in units of 16 bits inside the ATM switch 47.

Parity generator PG64 then adds parity bits to the data converted to 16 bits wide. For example, use an even parity generator. This parity bit is used to detect errors occurring within the ATM switch 47, and is checked by a parity checker 50 in the downlink highway cell synchronization section 43.

The parity-added cell data is then input to a cell synchronizer 65 for cell synchronization.

This is the HEC in the cell synchronization section 43 of the down highway.
HEC (heacier errOr CheC) added to the header section 80 of the cell by the generator 49
ker). This detection is performed using a cyclic redundancy check (CRC).
dancy check). When an error is detected in a cell by the HEC's cyclic redundancy check, "1" is set in the corresponding bit of the maintenance scanner MSCN53.

The cell synchronized cell data having a parity bit width of 16 bits is then input to the multiplexing/demultiplexing section 44.

The multiplexing/demultiplexing unit 44 uses VCC (virtual channel
First, the VCC 66 is connected to a VCI (virtual channel 1de) in a header 80 within a cell.
ntifier) from the sending VCI to the receiving VCT.
Convert to

The ATM switch 47 automatically selects the output highway based on the converted VCI. The cell data for which VCI conversion has been completed is multiplexed by a multiplexer 67 and sent to the ATM switch 47.

In the transmission line interface circuit explained above,
Four types of data checks are performed.

That is, in the first data check, the parity added by the parity generator 64 of the uplink highway cell synchronization unit 43 is applied to the downlink highway cell synchronization unit 4.
This is a check for data errors placed inside the ATM switch by checking with the parity checker 50 of No. 3.

The second data check is performed by the cell synchronizer 65 in the uplink highway cell synchronization section 43.
This is the detection of The cell synchronizer 65 on the up highway detects the NEC added by the HEC generator 49 in the cell synchronization section 43 on the down highway, and if there is an abnormality in this, it is determined that an error has occurred in the cell data.

The third data check is the detection of an input signal disconnection detected by the optical/electrical signal conversion circuit 58 on the up highway.

Finally, the fourth data check is
This is done in the ONET termination circuit 60. In other words, frame synchronization detected by the alarm detection circuit (ALMDET) and AIS (alarm 1 indication)
signal), this is an error detected by the overhead access circuit (○HA). AIS is an alarm signal provided by an alarm indication signal inserter (AIS IN5) in the downlink highway SONET termination circuit 54.

[Intelligence B that the invention attempts to solve] However, the conventional data check method has the following problems:
There is a problem that the data check is incomplete.

That is, on the down highway, cell data errors occurring inside the ATM switch 47 can be detected by the parity checker 50, but after that, the data is converted into an optical signal 46 and sent out to the transmission line 45. There is no way to detect errors that occur between them. Errors that occur during this time are only detected when an HBC check is performed at the cell synchronizer 65 on the upbound highway on the receiving side. This is insufficient to isolate the location where the failure occurs.

Also, regarding up-bound highways, optical signal abnormalities are caused by optical/
Although it can be detected by the electrical signal conversion circuit 58 and the uplink highway SONET termination circuit 60, errors occurring in cell data cannot be detected until the HEC check performed by the cell synchronizer 65 of the cell synchronization section 43. In this case, A.T.
Failure isolation for M cell data (ATM layer) is insufficient.

As described above, the transmission line interface circuit includes the opto-electrical signal converter 41. SONET termination section 42, cell synchronization section 43
, multiplexing/demultiplexing section 44. In general, most errors occur when data is transferred between these packages, and less often within a package. Errors within the package are often caused by element failures, and the frequency of such errors is low.

SUMMARY OF THE INVENTION An object of the present invention is to enable the location where data errors occur to be isolated on a package-by-package basis.

[Means for Solving the Problems] FIG. 1 is a block diagram of the present invention. The present invention is based on an ATM exchange 1 connected to a transmission line 2 and a subscriber line 3 and comprising an ATM switch circuit 4, a call processing device 5, and a transmission line or subscriber line interface circuit 6. The transmission line or subscriber line interface circuit 6 includes a photoelectric signal conversion circuit 7. It consists of four packages: a SONET terminal circuit 8, a cell synchronization circuit 9, and a multiplexing/separating circuit 10.

First, the transmission line or subscriber line interface circuit 6
has inter-package error detection means 11. The inter-package error detection means 11 includes a photoelectric signal conversion circuit 7-S.
Data errors occurring between ONET termination circuits 8 and between SONET termination circuits 8 and cell synchronization circuits 9 are detected.

Next, the transmission line or subscriber line interface circuit 6
has a total error data aggregation means 12. All errors/
The data integration means 12 integrates the error information such as data error occurrence information and optical signal abnormality detected by the inter-package error detection means 11 into one data. That is, by associating each error information with 1 bit of the 32-pinto maintenance scanner data, and inserting 1゛ if an error has occurred and 'O if no error has occurred, Generate one error occurrence information data.

On the other hand, the call processing device 5 has an error diagnosis means 13.

The error diagnosis means 13 periodically reads the maintenance scanner data generated by the total error data integration means 12 and analyzes it bit by bit, thereby diagnosing the type and location of the error.

[Function] In the case of an up-highway where an optical signal is input from the transmission line 2 or subscriber line 3 to the ATM exchange 1, the optical signal is first input to the opto-electrical signal conversion circuit 7 of the transmission line/subscriber line interface circuit 6. enter. The opto-electrical signal conversion circuit 7 converts the optical signal into an electrical signal.

Here, the inter-package error detection means 11 adds parity to the data of the converted electrical signal. The electrical signal to which parity has been added is input to the SONET termination circuit 8 of the transmission line/subscriber line interface circuit 6. The inter-package error detection means 11 executes a parity check in the manual section of the SONET termination circuit 8, and detects data errors occurring between the packages of the opto-electrical signal conversion circuit 7 and the SONET termination circuit 8. The detection results are sent to the total error data integration means 12.

The total error data integration means 12 receives the error detection data sent from the inter-package error detection means 11, and receives the error detection data sent from the inter-package error detection means 11, and detects the error detection data between the packages from the opto-electrical signal conversion circuit 7 to the SONET termination circuit 8 in the 32-bit maintenance scanner data. Insert "1' or 0" data into the bit corresponding to the error information. If an error has occurred, insert "1"
, if no error has occurred, insert 0゛.

The SONET termination circuit 8 performs a SONET (sync chrono
terminating the US optical network). The inter-package error detection means 11 then adds parity to the data at the exit of the SONET termination circuit 8. The data to which parity has been added is input to the cell synchronization circuit 9. In the cell synchronization circuit 9, AT
In order to absorb the time difference between different clocks inside and outside the V switch circuit 4, data is temporarily stored in the memory.

At the output part of this memory, inter-package error detection means 1
1 performs a parity check. by this,
Errors occurring between the output of the SONET termination circuit 8 and the output of the temporary storage memory of the cell synchronization circuit 9 are detected.

The detection result is sent to the all-error data integration means 12, which sets the bit corresponding to the error in the section of the maintenance scanner data as '1' (error occurred) or '0' (error). None) Insert the data of ゛.

The cell synchronization circuit 9 executes data width expansion processing for parity-checked data, conventional parity addition processing, and cell synchronization processing. This cell data undergoes demultiplexing processing in the multiplexing/demultiplexing section 10 and is input to the ATM switch circuit 4.

On the other hand, on the down highway where the cell data output from the ATM switch circuit 4 is sent to the transmission line 2 or the subscriber line 3, the cell data output from the ATM switch circuit 4 is first sent to the transmission line/subscriber line interface circuit. The signal is input to the multiplexing/demultiplexing circuit 10 of No. 6. Cell data is separated for each channel in a multiplex/separate circuit 10.

The separated cell data is then input to the cell synchronization circuit 9. The cell synchronization circuit 9 is a HEC (header) used for synchronization in uplink highway cell synchronization processing.
error checker) is inserted into the header section of the cell data. Thereafter, the cell synchronization circuit 9 checks the parity added by the cell synchronization circuit 9 on the up highway.

This parity is conventionally added parity. The parity check result is sent to the total error data integration means 12.
inserts "1" or "0" data into the corresponding bit of the maintenance scanner data.

The cell synchronization circuit 9 then executes data width reduction.

The inter-package error detection means 11 adds parity to the data whose data width has been reduced. Parity
The added data is temporarily stored in memory to absorb the time difference between the internal and external clocks.

The data with the time difference absorbed is then input to the SONET termination circuit 8. The inter-package error detection means 11 performs a parity check at the entrance of the SONET termination circuit 80. As a result, errors occurring between the temporary storage memory of the cell synchronization circuit 9 and the SONET termination section are detected.

The detection result is sent to the total error data integration means 12, and the total error data integration means 12 inserts data of 1" or "0° into the corresponding bit of the maintenance scanner data.

The parity-checked data is subjected to SONET termination processing by the SONET termination circuit 8 and output to the opto-electrical signal conversion circuit 7. The inter-package error detection means 11 adds parity to the data at the exit of the SONET termination circuit 8 and checks the parity at the entrance of the opto-electrical signal conversion circuit 7. This allows SONE
An error occurring between the T-termination circuit 8 and the package of the opto-electrical signal conversion circuit 7 is detected. The detection results are all errors/
The error data is sent to the data integration means 12, and the all error data integration means 12 inserts data of 1' or 0' into the corresponding bit of the maintenance scanner data.

The parity-checked data is first converted from a parallel signal to a serial signal by the opto-electrical signal conversion circuit 7, then converted from an electrical signal to an optical signal, and output to the transmission line 2 or subscriber line 3. .

On the other hand, the error diagnosis means 13 in the call processing device 5 takes in the maintenance scanner data created by the total error data integration means 13 at certain regular intervals. Then, it is determined bit by bit whether the value is 111 or "0", and if it is 1, it is determined that an error has occurred, and if it is '0', it is determined that no error has occurred.

If an error occurs, the part where the error occurs is diagnosed based on which bit.

〔Example〕

Hereinafter, embodiments will be described with reference to FIGS. 2 and 3.

FIG. 2 is a system configuration diagram of an embodiment of the present invention.

Although this embodiment describes the configuration and operation of a transmission line interface circuit, a subscriber line interface circuit can also be realized with a similar configuration and operation.

The transmission line interface circuit includes a photoelectric signal converter 21 .similar to the description of the conventional system. It consists of a SONET termination section 22, a cell synchronization section 23, and a multiplex/separation section 24.

First, a description will be given of a down-highway transmission line interface circuit that sends a signal output from the ATV switch 27 to the transmission line 25 as an optical signal 26.

The cell data signal input from the ATM switch 27 first enters the multiplex/demultiplexer 24 . The multiplexing/demultiplexing unit 24 on the down highway includes a demultiplexing device (DMX).
iplexer) 28 is present and separates the multiplexed signals. The separated signal is a signal in which 1-bit parity is added to 16-bit wide data. Parity is added by the cell synchronization unit 23 of the uplink highway on the transmitting side.

This signal is then input to the cell synchronization section 23. The cell synchronization unit 23 uses a HEC generator (HECGEN: header error check) similar to the conventional system.
k generator) 29, and parity checker (PC)
30, data width converter 31, elastic store (
ES: elastic 5tore) 32, and
The parity generator (
PG (parity generator) 70. Parity generator 70 is inserted between data width converter 31 and elastic store 32.

The cell input to the cell synchronization unit 23 is first input to the HEC generator (HECGEN) 29, which generates 1-byte control data HEC (header) for cell synchronization.
error check) 82 is added to the header section within the cell. The cell data given HEC82 is then input to the parity checker PC30,
A parity check is performed at the cell synchronization section of the uplink highway. Processing of the detection results of the parity checker 30 will be described later.

The 16-bit wide cell data excluding the parity bit from the output of the HEC generator 29 is then input to a data width converter 31, where it is converted from 16-bit width to 8-bit width. The cell data converted to 8-bit width is then sent to the newly added parity generator 7.
0 is input, and 1 bit of parity is added to 8 bits of data. The 8-bit parity bit data is then temporarily stored in the elastic store 32.

Cell data having a width of 8 bits plus parity bits, once stored in the elastic store ES 32, is then input to the 5OSNET termination unit 22. SONET
The termination section 22 consists of a down highway SONET termination circuit 34, one newly added parity checker 71, and one parity generator 72. A new parity checker 71 is inserted into the inlet portion of the SONET termination 22, and a parity generator 72 is inserted into the outlet portion of the SONET termination 22.

A parity checker 71 is placed at the entrance of the SONET termination section 22 and checks the parity added by the parity generator 70 in the cell synchronization section 22. As a result, the data width converter 31 in the cell synchronization section 23 and the SO
Errors that occur up to the entrance of the NET termination section 22 can be detected.

Processing of the detection results of the parity checker 71 will be described later.

Of the 8-bit parity bit data inputted to the 5ONNET termination unit 22, 8-bit data excluding the parity bit is inputted to the downlink highway SONET termination circuit 34. The downlink highway SONET termination circuit 34 uses an overhead inserter (OHI) as described in the conventional system.
1nsert.

r) and a scrambler (SCR)
, arm instruction signal inserter (AI 5INS:a
larm 1ndition signal
1nsertor).

The 8-bit cell data is first assembled into SONET format data by an overhead inserter OHI. Then, the information field is scrambled by a scrambler SCR, and further,
The alarm indication signal inserter (AIS lN5) adds the scrambled signal to the alarm indication signal (AIS:
afarm 1ndition signal
)35 is inserted. This completes the SONET data.

The output data of the downlink highway SONET termination circuit 34 is input to the newly inserted parity generator 72, and parity is added thereto.

The parity-added data then enters the opto-electrical signal converter 21.

The opto-electrical signal converter 21 includes the parallel-to-serial converter 36 and the electrical/optical signal converter circuit 37 described in the conventional system, and a newly added parity checker 73. The new parity checker 73 is inserted at the entrance of the opto-electrical signal converter 21 and performs a parity check on data with parity input from the SONET termination section 22.

This makes it possible to detect errors between the SONET termination section 22 and the packages of the two optoelectrical signal converters. Processing of the detection results will be described later.

The 8-bit data signal other than the parity bit is input to a parallel-serial converter 36, which converts the 8-bit parallel signal into a serial signal. Then, the electrical/optical signal conversion circuit 37 converts the serial signal into an optical signal 26.
and sends it out to the transmission line 25.

Next, a transmission line interface circuit that receives the optical signal 26 from the uplink highway, that is, the transmission line 25, and interfaces with the ATM switch 27 will be explained.

The optical signal 26 transmitted through the transmission line 25 is first input to the opto-electrical signal converter 21 of the transmission line interface circuit. The optical/electrical signal converter 41 includes the optical/electrical signal converter (○/E) 38 and the serial/parallel converter 39 described in the conventional method, and the newly added parity generator 74.
Consisting of The parity generator 74 is inserted at the outlet of the opto-electrical signal converter 21 .

The input optical signal 26 is first converted into an electrical signal by an optical/electrical signal conversion circuit (0/E) 38.

This electrical signal is a serial signal, which is converted into a parallel signal by a serial/parallel converter 39. In this case, it is converted into 8-bit parallel data.

The signal is then input to a parity generator 74 to which a parity bit is added.

The 8-bit parallel data with parity bin I is then input to SONET termination 22. The SONET termination unit 22 includes the uplink highway SONET termination circuit 90 and alarm sign data (ALMSND) 91 described in the conventional system, one newly added parity checker 75, and one parity generator 76. Parity Chie Tsuka 75
is inserted into the inlet of SONET termination 22, and parity generator 76 is inserted into the exit.

Parity checker 75 performs a parity check on data input to SONET termination section 22. This allows the photoelectric signal converter 21 to
Errors between packages to ET terminations become detectable.

Of the data input to the SONET termination section 22, 8-bit data excluding the parity bit then enters the uplink highway SONET termination circuit 9o. The uplink highway SONET termination circuit 9o is a synchronous circuit (SYNC:
5ynchronous), and descrambler (
DSCR: descrambler), alarm detection circuit (ALM DET: alarm detect)
r), Overhead Access Circuit (OHA)
r head access).

The 8-bit data is first input to the synchronization circuit (SYNC) of the uplink highway SONET termination circuit 90, and synchronization is established. Then, the descrambler (DSCR)
), the scrambler (SCR) of the downlink highway SONET termination circuit 34 returns the scramble applied to the information field data to its original value. In addition, the alarm detection circuit (ALM DET) detects frame synchronization and AIs (alarm 1 indications).
gna I), etc., and the overhead access circuit (OHA) performs SONET overhead processing.

On the other hand, the alarm sign data (ALM SND:
The alarm signal data) 91 includes an alarm detection circuit (ALM DET) as in the conventional system.
Frame synchronization detected by
Abnormal information such as AIS included in the T data and line abnormalities detected during overhead processing is sent, as well as parity information in the cell synchronization unit 23 of the down highway.
A parity checker 30, a parity checker 71 located at the SONET terminal end 22 of the down highway, a parity checker 73 located at the opto-electrical signal converter 21 of the down highway, and a parity checker 73 located at the 5OSET end of the up highway. The check results of a parity checker 77, which will be described later, in the cell synchronization unit 23 of the uplink highway are sent to the check engine 5.

This alarm sign data (ALM 5ND) 9
inserts these abnormality information and parity checker output information into the corresponding bits of the maintenance scanner MSCN33. In other words, if an error occurs, '1
If " has not occurred, '0" is inserted into the maintenance scanner data bit corresponding to each error information.

The up-highway SON F, T terminal circuit 90's over head access circuit (OHA)
The 8-bit data subjected to T overhead processing is then input to the cell synchronization section 23.

The cell synchronization unit 23 includes the elastic store (ES) 92 described in the conventional method, the data width converter 93,
parity generator (PG)
enerator) 94, cell same M device (CELL 5
YNC: cell 5 synchronous) 95 and a new parity checker 77. A parity checker 77 is placed between the elastic store 92 and the data width converter 93, and performs a parity check on data with parity that is temporarily stored in the elastic store to absorb time differences. Do this. This makes it possible to detect errors that occur between the exit of the SONET termination section 22 and the exit of the elastic store 42 of the cell synchronization section 23. The output of the parity checker 77 is input to the alarm sign data (ALM 5ND) of the SONET termination section 22.

The 8-bit data other than the parity bit is then
A data width converter 93 converts the data width from 8 bits to 16 pintos. Furthermore, the conventional parity
Generator PG94 adds parity bits to the data converted to 16 pint width. This parity
・The focus is to detect errors occurring in the ATM switch 47, and the cell synchronization unit 23 on the down highway
The parity checker 30 is used to check the parity.

The parity-added cell data is then input to a cell synchronizer 95 for cell synchronization.

This is the HEC in the cell synchronization section 23 of the down highway.
HEC (header error check) added to the header section 80 of the cell by the generator 29
ker). This detection is performed using a cyclic redundancy check (CRC).
dancy check). If an error is detected in a cell by the HEC's cyclic redundancy check, this fact will be sent to the alarm sign data (AL, M5ND
)91.

The cell synchronized cell data with a parity bit width of 16 pins is then input to the multiplexing/separating section 24.

The multiplexing/demultiplexing unit 24 uses VCC (vir
tual channel converter)96
and multiplexer W (MUX: multiplexer) 9
Consists of 7. First, the VCC 96 connects the VCI (virtual channel 1
dentifier) from the transmitting side VCI to the receiving side VCI so that the TM switch 27 can automatically select the output highway. The cell data for which VCI conversion has been completed is multiplexed by the multiplexer 97 and sent to the ATM switch 27.

As described above, four new parity generators (70, 72, 7
4,76) and four parity checkers (71,73
, 75, 77), and on the down highway, between the packages from the cell synchronization unit 23 to the SONET termination unit 22,
and from the SONET termination section 22 to the opto-electrical signal conversion section 2
1, and on the up highway, errors can be detected between packages from the opto-electrical signal converter 21 to the SONET termination section 22, and between packages from the SONET termination section 22 to the cell synchronization section 23.

Also, all parity checkers (30, 71, 7
3, 75, 77) and CR by the cell synchronizer 95.
The detection results of C, the optical signal disconnection detection signal of the optical/electrical signal conversion circuit 38, and various abnormal signals detected by the uplink highway SON E Tl terminal circuit 90 are sent to the alarm sign cage (ALM 5ND) of the SONET terminal section 22. are collected and inserted into the maintenance scanner 39 in bulk.

The maintenance scanner 39 is read at regular intervals by error diagnosis software in the call processing device 5 in the ATM switch 1. The data of the error diagnosis software and the maintenance scanner 39 read are "1" for each focus.
" or 0'. If it is "1', it is determined that an error has occurred. Here, the location where the error has occurred is determined based on the position of the bit.

FIG. 3 is a block diagram of a parity check circuit inserted between each package.

A parity generator circuit is placed at the output part of the processing device 110 of the package A100, and the package BIOI
A parity check circuit is placed at the inlet of the circuit.

When 8-bit data 102 is output from the package A 100, the 8-bit data 102 is sent to the bar cage B 101 via the buffer 103 and is also input to the even parity generator 104. The even parity generator 104 generates parity if the number of bits set to 1' in the input 8-bit data is odd.
If the number of bits in which 1' is set is an even number, the output is "1" and the parity output is "0". The parity output is sent to the package BIOI via buffer 105 along with 8 bits of data.

8-bit data 102 sent to package B 101
is sent to the package BIOI processing circuit 109 via the buffer 106 and is also input to the even parity checker 107.

In addition to this, the even parity checker 107 has
Parity data P generated by even parity generator 104 of package A 100 is also manually input.

The even parity checker 107 outputs "1" if the number of bits in which 1' is set is an odd number among the input 8 bits + parity bit data, and outputs "1" as the number of bits in which "1' is set". If the output of the even parity checker 107 is 0', it can be determined that no data error has occurred, and if it is 1', an error has occurred. It can be determined that there is.

Even parity generator 104 and even parity checker 107 can be configured with similar circuits, except that even parity checker 107 has one more human data line.

The output of the even parity checker 107 is the flip
The signal is sent to a certain bit of the 32-bit maintenance scanner MSCN33 via the flop circuit 108. The position of the bit sent is predetermined depending on which package to package error detection is being performed.

Although the parity check circuit shown in the figure is for a data width of 8 bits, the parity check circuit can be constructed in a similar manner even when the data width is 16 bits. The number of data lines can be increased to 16. Further, even parity is used in the figure, but odd parity is more appropriate when the buffer is configured with an inverter.

〔Effect of the invention〕

According to the present invention, it becomes possible to isolate faults in ATM cells (ATM layer), which was not possible with conventional methods. In other words, by adding a parity generator to the output section of each package constituting the transmission line interface circuit or subscriber line interface circuit and a parity checker to the population section, errors that occur between each package can be reduced. detection becomes possible. Additionally, errors detected in transmission line interface circuits or subscriber line interface circuits are notified all at once to the error diagnosis software via the maintenance scanner MSCN, thereby automatically executing error diagnosis for these circuits. This makes it possible to improve error diagnosis ability.

[Brief explanation of drawings]

Figure 1 is a block diagram of the present invention, Figure 2 is a system configuration diagram of one embodiment (configuration diagram of a transmission line interface device), Figure 3 is a configuration diagram of a parity check circuit between packages, and Figure 4. 5 is a system configuration diagram of a conventional transmission line interface device, and FIG. 5 is a cell configuration diagram. 1...ATM switch, -Transmission line, -Subscriber line, -ATM switch circuit, -Call processing device, -Transmission line/subscriber line interface...Optical electrical signal conversion circuit, SONET termination circuit, cell synchronization circuit, Multiplex/separate circuit, package open error detection means, all error data integration means, error diagnosis means.

Claims (1)

[Claims] 1) ATM switch circuit (4) and call processing device (
5), transmission line or subscriber line interface circuit (
6) ATM (Asynchronous Tra
nsfeMode: Asynchronous transfer mode) SONET (
Synchronous Optical Network
: Optical electrical signal conversion circuit (7), SONET termination circuit (8), cell synchronization circuit (9), multiplexing/demultiplexing circuit (
In the transmission line or subscriber line interface circuit (6) consisting of 10), a photoelectric signal conversion circuit (7), a SONET termination circuit (8), and a cell synchronization circuit (9).
, inter-package error detection means (11) for detecting errors occurring between each circuit package of the multiplexing/separating circuit (10).
); All error data integrating means (12) for integrating the error detection results for each package detected by the inter package error detecting means (11) as one data; and All error data integrating means (12). ) Error diagnosis means (13) that receives the error data integrated by
1. A test method for a transmission device interface circuit, comprising: 2) The inter-package error detection means (11) is an AT
On the down highway from the M switch circuit (4) to the transmission line (2) or subscriber line (3), the output part of the data width conversion circuit (converts from 16 bits to 8 bits) in the cell synchronization circuit (9) Place a parity generator and connect the parity generator to the inlet of the SONET termination circuit (8).
Cell synchronization circuit (9)-SON by placing a checker
A test method for a transmission device interface circuit according to claim 1, wherein an error occurring between the ET termination circuits (8) is detected. 3) The inter-package error detection means (11) is an AT
On the down highway from the M switch circuit (4) to the transmission line (2) or subscriber line (3), the SONE
By placing a parity generator at the outlet of the T-termination circuit (8) and a parity checker at the entrance of the opto-electric signal conversion circuit (7), the SONET termination circuit (8) - photo-electric signal conversion circuit (7) is created. 2. A test method for a transmission device interface circuit according to claim 1, which detects an error occurring between the transmission device interface circuit and the transmission device interface circuit. 4) The inter-package error detection means (11) is installed at the exit portion of the opto-electrical signal conversion circuit (7) on the upward highway from the transmission line (2) or subscriber line (3) to the ATM switch circuit (4). 2. An error occurring between the opto-electrical signal conversion circuit (7) and the SONET termination circuit (8) is detected by placing a parity generator and a parity checker at the entrance of the SONET termination circuit (8). A test method for transmission equipment interface circuits. 5) The inter-package error detection means (11) detects the SONE on the up-highway from the transmission line (2) or subscriber line (3) to the ATM switch circuit (4).
A SONET termination circuit (8) is created by placing a parity generator at the exit of the T termination circuit (8) and a parity checker at the input of the cell synchronization circuit (9).
- A test method for a transmission device interface circuit according to claim 1, wherein an error occurring between the cell synchronization circuits (9) is detected. 6) The total error data integration means (12) scans the errors between each package detected by the inter-package error detection means (11) using a 32-bit maintenance scanner (MSCN).
2. The test method for a transmission device interface circuit according to claim 1, wherein all error data are integrated into one data by making the error data correspond to one bit of the error data. 7) The error diagnosis means (13)
exists in the call processing device (5) and analyzes the maintenance scanner data bit by bit received from the all-error data integration means (12) to connect the transmission line or subscriber line interface circuit (6). 2. The method for testing a transmission device interface circuit according to claim 1, wherein the test method diagnoses at which location between which packages the error has occurred.