JPH04117878A - Band compression circuit - Google Patents

Abstract

PURPOSE:To use a memory with a small capacity by dividing a digital data into a consecutive Os part and a non-zero part in succession thereto, stopping a memory write address with a zero detection signal, applying time division multiplex to a zero run signal and a non-zero signal and writing the result to the memory. CONSTITUTION:A two-dimension coding section 51 detects a consecutive Os part and a non-zero part in succession thereto and outputs a zero run data(ZRD) representing consecutive number of Os and a non-zero data(NZD) in succession thereto. Moreover, a zero run identification signal (ZID) to identify a period of consecutive Os and a period of non-zero consecution is outputted. A selection circuit 52 makes selection in response to the zero run identification signal (ZID) and outputs selectively the zero run data(ZRD) for a period when Os are consecutive and the non-zero data(NZD) for a period of non zero data(NZD). Then the zero run data(ZRD) and the non-zero data(NZD) are subjected to time division multiplex and the resulting output is fed to a memory 53.

Description

Detailed Description of the Invention [Purpose of the Invention (Industrial Field of Application) This invention relates to a band compression method used in a recording/reproducing device that records a video signal on a magnetic tape or reproduces it from a magnetic tape, for example. Regarding circuits.

(Prior Art) When handling Video Shingo in a digital recording/reproducing device, since the amount of information is large, large hardware is required to record it as it is. Therefore, for consumer use, band compression is generally performed to reduce the amount of pigs handled. In recent years, as a method for band compression, a method has been announced that performs DCT (discrete cosine transform) processing and further performs variable length encoding (1.989 National Conference of the Society of Television Engineers 19-22.1.9- 23'). Video tape recorder technology that adopts this method has also been announced (August 1989, IE3. Transact
ions on ConsumerElectroni
s, Vol 35 'AN EXPI Mi 1, l M
E N T A L S T 11 D YIko01
? All0) IE-USE DIGITAL VT
R”).

FIG. 4 shows the block configuration of the video tape recorder.

The input video signal is digitized by an analog-to-digital (A/D) converter 1 and input to a frame processing section 12, where it is converted into frame-by-frame data. The output of the frame processing unit] 2 is subjected to DCT transformation in a DCT band compression unit 13, inputted to a variable length encoding unit 14, converted into Huffman code, for example, and further inputted to a parity addition unit 15,
A parity code for error correction is added. Parity
The output of the adding section 15 is interleaved by an interleaving section 6 and modulated by a modulator 17.

The output of the modulator 17 is supplied to a recording/reproducing section 18 and recorded on a magnetic tape.

The signal reproduced by the recording/reproducing section 18 is demodulated by a demodulator, and the demodulated signal is input to the deinterleaving section 20 and deinterleaved.

The deinterleaved signal is then subjected to error correction in the error correction section 2], and input to the variable length decoding section 22 where it is decoded (Huffman decoded). The data rate of the decoded signal is returned to the original value by the IDCT band expansion section 23, and is input to the frame inverse processing section 24, where it is returned to data for each field. The signal demodulated in this way is D
The signal is input to the /A converter 25, converted into an analog video signal, and outputted to the output terminal 26.

In the above system, the variable length encoder] 4 is an important part for reducing the amount of information recorded on the recording medium.

As variable length encoding methods, run-length encoding method and
A two-dimensional code Huffman coding method that is a combination of Huffman coding methods has been proposed by JPEG (130/CCITT Natural Picture Coding Standard Discussion Group).

This method converts continuous parts of zero data into one code (NN
NN), and the bit length (S S S S) that is the sum of the data immediately after the zero cut (additional bit) is combined and Huffman encoded, and then this (=I addition bit) is combined to form one native language. This is a method to do so.

For example, if you input 00040013... as PCM data, the first consecutive zero number NNNN = 3, and the additional bit length is 5SSS = 3.
, the additional bits are 4=100.

That is, [3,3] + [100], of which [3
, 3] is Huffman encoded, [Huffman code[1,00]
is treated as one codeword. Such encoding is 2
This is called dimensional encoding.

The two-dimensional code is a variable length code, and as it is, it causes inconvenience in signal processing. Therefore, at a constant rate (serialization,
It is necessary to convert it into a part-time job, etc.).

At this time, in the VTR, it is necessary to maintain a constant rate in real time. Even in the case of obtaining electronic still photographs, it is preferable to perform constant recording in real time as much as possible considering the continuous photographic mode.

A possible way to achieve a constant rate is to use a frame memory to set a fixed length in units of frames.

In this case, the data may be loaded into the frame memory and set to a constant value when read. However, in pigs, the maximum code length of variable length may occur continuously for an instant, so in order to cope with this, the memory must have a width of the maximum code length and a frame depth. What is required is something that has quality.

The variable length code section] 4 is configured as shown in FIG. 5, for example.

The pig that has been adaptively quantized by the DCT band compression section 13 is input to the two-dimensional encoding section 31, where consecutive zero parts and non-zero parts are detected.

The argument values in consecutive zero parts are input to the Huffman coder 32, and the non-zero parts are input to the bit length detection section 33. The bit length detection unit 33 detects the bit length of the non-zero portion and supplies it to the Huffman Deco 9'. The Huffman coder 32 creates a Huffman code (RFC) using continuous zero values and the bit length of the non-zero portion. /\
The human code (RFC) and the data of the non-zero portion are supplied to the memory 34 as a two-dimensional code (2DC). In addition, this memory 34 includes a two-dimensional COF (2CD).
At the same time, bit length data (BLD) representing the total number of bits is also input from the Huffman coder 32.

In this state, the two-dimensional code (2CD) is a variable length code, and its total bit length is
It is expressed by

Write control of the memory 34 is performed by three write address generation units. The data written to the memory 34 is
After one frame, the data is read out under control from the read address generation section 38.

The data to be read out includes a two-dimensional code (2CD), which is a variable length code, and bit length data (2CD) indicating its total bit length.
BLD). The two-dimensional code (2CD) is input to the rate fixing section 35, and is given a fixed rate and output to the output section 36. The bit length data (BLD) is input to the read address stop section 37. Then, the read address output from the read address generator 38 is stopped for a time proportional to the code length, thereby making it possible to fix the rate.

(Problem to be Solved by the Invention) According to the above-described band compression circuit, the total amount of data for each frame is compressed to a constant value, but data of variable length maximum value may continue at a certain time. For this,
The memory 34 must have a bit width equal to the maximum length of variable-length encoded data and a capacity with a depth equivalent to a frame, increasing the scale of the hardware.

SUMMARY OF THE INVENTION An object of the present invention is to provide a band compression circuit that can use a memory with a small capacity, reduce the hardware scale, and reduce the cost.

[Structure of the Invention] (Means for Solving the Problems) The present invention divides digital data into a consecutive zero part and a non-zero part following it, and divides the digital data into data indicating the number of consecutive zeros (zero run data). two-dimensional encoding means for outputting data indicating a non-zero portion (non-zero data), a zero-run identification signal that identifies the continuous zero portion and the non-zero portion; and the zero-run data and the non-zero data. a selection means for selecting and deriving the zero run identification signal in a time-sharing manner; a storage means to which the output data from the selection means is supplied; If it indicates a period during which data is read from the storage means, a write control means capable of stopping the write address, a read control means generating a read address for reading data from the storage means, and a period during which data is read from the storage means are provided. The first latch means latches the zero run data at different timings, and when the non-zero data is latched, the outputs of the second latch means and the first latch means are zero. A zero insertion means for inserting a value and the output of this zero insertion means,
a third latch means launching with the same clock as said second latch means;
a latch means of ]0, a bit length detecting means for detecting the bit length after conversion from the output of the second latch means, and a variable length detecting means using the output of the bit length detecting means and the output of the third latch means. A variable length code conversion means for converting into a long code, a two-dimensional No. 71 code obtained from the variable length code conversion means and bit length data of the two-dimensional code, and the above-mentioned code that detects consecutive zeros read from the one-time code. control means for creating a signal for controlling address stop of the read control means and latch timing of the first, second and third latch means from the zero run identification signal; and a code obtained from the variable length code conversion means; and output means for outputting the non-zero data obtained from the second launch means at a constant rate.

(Operation) With the above means, the memory write address is stopped by the zero detection signal, and the zero run signal and the non-zero signal are time-division multiplexed and written into the memory.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The ff quantized input data is sent to the two-dimensional encoder 5 via the input terminal 50.
1 is input.

The two-dimensional encoding unit 51 detects consecutive zero portions of input data and subsequent non-zero portions. Then, zero run data (ZRD) indicating the number of consecutive zeros and subsequent non-zero data (NZD) are output. Furthermore, the two-dimensional encoding unit 51 generates a zero run identification signal (Z
ID) is output.

Zero run data (ZRD) and non-zero data (NZ
D) is supplied to one and the other of the selection circuits 52. The selection circuit 52 performs a selection operation in response to a zero run identification signal (ZID), and selects zero run data (
ZRD) is selected and derived, and non-zero data (NZD) is selected and derived for the period of non-zero data (NZD). Therefore, the selection circuit 52 time-division multiplexes the zero run data (ZRD) and the non-zero data (N Z D), and this output is supplied to the memory 53 . Further, the previous zero run identification signal (Z ID) is also supplied to the memory 56.

The two-dimensional encoder 51 also outputs a zero count over signal (zcov) when the number of consecutive zeros is two or more.
is output, and this signal is supplied to the write address generation section 54.

As a result, the memory 53 has a fixed length (17 rem) (<
(maximum number of bits of variable-length code) or zero parts are deleted and stored.

The data stored in the memory 53 is read out according to the read address from the read address generation section 55.

Zero run data (
ZRD) and non-zero data (N Z D) are time-division multi-Φ
The output signal is output in the same state and supplied to latch circuits 56 and 57. Further, the previous zero run identification signal (Z ID) is read out from the output section 53d of the memory 53 and supplied to the read address stop circuit 58.

The latch circuit 56 latches zero run data (ZRD) and inputs it to the zero insertion circuit 59.

The zero insertion circuit 59 creates zero run data indicating that there is no zero run when there is no zero run in terms of clock units, and in this case, supplies "0" to the latch circuit 60 as zero run data. If zero run data exists in terms of tarok units, the zero run data is directly supplied from latch circuit 56 to latch circuit 60.

The zero run data reproduced in this manner is supplied to the zero run data input section of the Huffman coder 63.

On the other hand, the latch circuit 57 latches non-zero data in clock units. Non-zero data is detected by bit length detection section 6
1 and is also input to the rate fixing section 63. The bit length data of non-zero data detected by the bit length detection section 61 is supplied to the bit length input section of the Huffman coder 62.

The Huffman coder 62 creates a Huffman code using the zero run data and the bit length data of non-zero data, and supplies this to the rate fixing unit 63. Further, the Huffman decoder 62 outputs a total pit length decoder representing the total number of bits of the Huffman code, and supplies it to the read address stop circuit 58. The read address stop circuit 58 uses the total bit length data and the zero run identification signal to generate the latch pulses of the latch circuits 65, 57, and 60, the timing pulses of the five zero insertion circuits, and the address stop signal of the read address generator 55. I'm creating it.

The rate fixing unit 63 uses the read address IL for the period of the total bit length obtained from the Huffman coder 62.
Using this time, for example, serialization, byte conversion, etc. are performed to fix the rate.

FIG. 2 is a timing chart shown to explain the operation of the above embodiment.

FIG. 2(a) shows a system clock, which has a frequency of 4 fsc, which is, for example, four times the frequency of the color subcarrier. Further, FIG. 2B shows an example of quantized data. FIG. 2C shows a detection signal obtained as a result of distinguishing between zero data and non-zero data within the two-dimensional encoder 51. When this detection signal indicates a period of zero, tarok is counted inside the two-dimensional encoder 51. FIG. 4(d) shows how the number of consecutive zero data is counted.

Using the clock shown in FIG. 2(a) and the detection signal shown in FIG. 2(d), the data latch pulse shown in FIG. 2(e) can be obtained. Since this latch pulse is obtained when non-zero data exists, non-zero data can be latched by this launch pulse (FIG. 2(f)). This non-zero data is then latched by the clock (FIG. 2(g)), derived as non-zero data (NZD), and supplied to the selection circuit 52.

Furthermore, by using the detection signal and the clock, the latch pulse shown in FIG. 2(i) can be obtained.

In other words, it is a pulse indicating the part where the continuous zero data is broken. This pulse allows the old value indicating the number of consecutive zero data to be taken out (FIG. 2 (J)). This data is supplied to the selection circuit 52 as zero run data (ZRD).

On the other hand, if the previous detection signal (FIG. 2(C)) is latched for one clock while indicating the detection of non-zero data, the pulse shown in FIG. 2(H) can be obtained. If this pulse is further delayed by one clock, the result is as shown in Figure 2 (k
) pulses can be obtained. This pulse in FIG. 2(k) is located at the beginning of the non-zero data in FIG. 2(j). Therefore, this pulse is used as a zero run identification signal (ZID).
It is used as a signal to control the selection circuit 52. That is, zero run data (ZRD) is supplied to the memory 53 for a clock period, and thereafter non-zero data (N Z D) is supplied to the memory 53. Then, the data input to the memory 53 can be expressed as shown in FIG. 2 (1).

Here, by performing an AND operation using the signals shown in FIG. 2(C) and FIG. 2(k), the signal shown in FIG. 2(m) is obtained. This signal becomes high level when there are two or more consecutive zeros.

If there are two or more consecutive zeros, this means that among the time-division multiplexed data, non-zero data obtained before the consecutive zeros are successively output. In the example shown, for example x
O, X 2 is being output for a long period of time. Therefore,
To store it in the memory 53, it is only necessary to specify the address once at the clock timing, so as shown in FIG. 2(m)
When the signal is high level, the write address generator 5
4 address output is stopped. In other words, the signal in FIG. 2(m) is the zero count over signal (
ZCOV) is supplied to the write address generation unit 54.

As a result, data can be efficiently stored in the memory 53.

FIG. 3 is an operation timing chart]8 when reading out the pig stored in the memory 53 and supplying it to the Huffman coder 62 and the rate fixing section 63.

FIG. 3(a) shows a system clock, and FIG. 3(b) shows a clock having a frequency four times that of the system clock. Furthermore, the same figure (C)
is a frame pulse, and (d) in the figure is a frame reset pulse.

The read address generator 55 generates an address (
FIG. 3(e)) is output.

As a result, time-division multiplexed data (zero run data and non-zero data) is output from the memory 53, as shown in FIG. 5(f). In addition, the zero run identification signal (
ZID) (FIG. 3(g) = FIG. 2(k)) is also read out at the same time.

The zero run identification signal (ZID) is used in the read address stop circuit 58 to create a latch pulse. FIG. 3(h) is a zero randy clutch pulse, which is supplied to the latch circuit 56. As a result, the zero run data is latched in the latch circuit 56 (Fig. 3 (i)
)) will be done.

This latched data is further latched by a latch pulse (FIG. 3(j)) in a latch circuit 960. This latch pulse is synchronized with the clock and is output when non-zero data is output. Here, the read address stop circuit 58
The signal in figure (k) is created using the signals in figure (11) and (j). That is, by using the signals shown in FIG. 3 (h) and (j) as the zero I input and reset input of the flip-flop circuit, the signal shown in FIG. 3 (IO) can be obtained.

This signal takes a low level when non-zero data continues as seen from the timing chart. Therefore, when non-zero data are consecutive, it is necessary to recognize whether zero data is continuous or absent between the non-zero data. For this reason, it is necessary to create "0" as a zero lamp. To achieve this, the signal in Figure 3(k) is
The zero insertion circuit 59 is controlled to generate zero run data "0" between the non-zero data when the non-zero data are consecutive, and to cause the latch circuit 60 to latch the data. As a result, zero run data is output from the launch circuit 60 as shown in FIG. 3 (1') (F).

Furthermore, since the latch pulse shown in FIG. 3(j) indicates the position where non-zero data exists, it is also supplied to the back/notch circuit 57. As a result, from the false Sochi circuit 57, the third
Non-zero data is output as shown in Figure (m).

The output of the latch circuit 57 is input to a bit length detection circuit 61 to detect the bit length, and the rate fixing unit 6
3 is input. The data indicating the non-zero data bit length detected by the bit length detection circuit 61 is processed by the Huffman coder 6.
2 is input. As a result, the Huffman coder 62
A human code is created and supplied to the rate fixing section 63. Also, the total bit length obtained from the Nofman coder 62 (
code length) data is read address stop circuit 58
is input.

The read address stop part 58 corresponds to the code length,
During this period, the read address generator 55 is controlled to stop the read address.

''-As mentioned above, according to this embodiment, the memory is allocated before the variable code is naturalized. For this reason, the bit width of the memory is fixed. Furthermore, since zero-run data and non-zero data are stored in a time-axis multiplexed manner, the memory capacity can be significantly smaller than in conventional systems. For example, when used in a digital VTR, conventional 1. /2.4 times. It is also constant when creating data for video processing.
You can get it in real time.

[Effects of the Invention] As explained above, according to the present invention, a memory with a small capacity can be used, and the size and cost of the hardware can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a process diagram showing one embodiment of the present invention;
3 and 3 are timing charts shown to explain the operation of the circuit shown in FIG. 1, FIG. 4 is a system explanatory diagram of a digital VTR, and FIG. 5 is a diagram showing a conventional band compression circuit. 51... Two-dimensional encoding unit, 52... Selection circuit, 53
, memory, 54. Write address generation section, 55.J-door address 56, 57, 60..Ratch circuit, zero insertion circuit, ...pit length detection section, Huffman coder, 6.3.

Claims (1)

[Claims] Digital data is divided into a continuous zero part and a non-zero part following it, and data indicating the number of consecutive zeros (zero run data) and data indicating the non-zero part (non-zero data)
and two-dimensional encoding means for outputting a zero-run identification signal that identifies the continuous zero portion and the non-zero portion; and selection means for selecting and deriving the zero-run data and the non-zero data in a time-sharing manner. and a storage means to which the output data from the selection means is supplied, and a write address of the storage means is controlled, and when the zero run identification signal indicates a period in which the zeros are continuous, the write address is controlled. write control means capable of stopping the writing; read control means generating a read address for reading data from the storage means; latch means latching data read from the storage means at different timings; a first latch means for latching zero run data and a second latch means for latching the non-zero data; a zero insertion means for inserting a zero value into the output of the first latch means; third latch means for latching the output of the means with the same clock as the second latch means; bit length detection means for detecting the bit length after conversion from the output of the second latch means; variable length code converting means for converting into a variable length code using the output of the length detecting means and the output of the third latch means; the code of the two-dimensional code obtained from the variable length code converting means and the bit length of the two-dimensional code; Based on the data and the zero run identification signal that detected consecutive zeros read from the storage means, the address stop of the read control means, the first
, a control means for creating a signal for controlling the latch timing of the second and third latch means, and a code obtained from the variable length code conversion means and the second latch means.
1. A band compression circuit comprising: output means for outputting non-zero data obtained from the latch means at a constant rate.