JPH04117582A - Graphic plotting device - Google Patents

Abstract

PURPOSE:To attain plotting processing for a short time irrespective of the cycle of a memory and operating speed by writing picture element data in a picture memory en bloc when address change except a direction able to be processed en bloc is detected by an address detecting means or the number of bits of the picture element data is coincident with the number of bits of a processed bit number determining means. CONSTITUTION:The speed of a line plotting circuit 40 is defined as attaining the processing of three times to one memory cycle, when the operation of three times is executed to the one memory cycle, a controller 14 controls so as to write line dot data in a picture memory 1 when a dot with hatching given is changed in an arrow direction for the access conditions of the address of the picture memory 1. That is, when the address changes in a Y direction, or the address of an X direction changes or the sum of the processing cycle time of a line plotting processing circuit 40 from memory access one before is equal to a memory cycle, the picture memory 1 is accessed respectively and the line plotting dot is written in the picture memory 1 from a data register 3. Thus, plotting speed can be raised.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a figure drawing device for drawing lines in computer graphics such as word processors, desktop publishing (hereinafter abbreviated as DTP), or workstations. .

(b) Conventional Technology In systems such as word processors and DTP, there is a demand for higher quality of various characters, symbols, etc. However, having characters of different sizes in a dot font is undesirable because the font capacity becomes enormous. Therefore, characters are displayed or printed using so-called outline fonts, in which only the outline information of characters is memorized, and when the characters are displayed or printed, the outline is drawn using a graphic drawing device and the inside is filled in based on the outline information. ing.

The outline of the character described above is drawn divided into several straight lines. Then, each straight line is calculated by a graphic drawing device using the Presentham algorithm or the like to create pixel bits. Lines are drawn by writing the pixel bits into the image memory.

By the way, when comparing the operating speed of a graphic drawing device using a conventional processor or the like and an image memory, the speed of the graphic drawing device is significantly faster. Therefore, the graphic drawing device is adapted to the operating speed of the image memory. In other words, the operation speed is adjusted according to the memory cycles of reading and writing to the image memory, various basic figures are drawn one dot per memory cycle, and the figures read out every l cycle are transferred to the figure drawing device. Line drawing is performed by ORing all the numbers according to the bit width to be processed and writing them to the same address in the image memory.

(c) Problems to be Solved by the Invention In the conventional graphic drawing device described above, the memory cycle and operating speed of reading and writing to the image memory are the bottlenecks, and even if the processing speed of the processor that constitutes the graphic drawing device is fast, However, it is necessary to draw one dot at a time in accordance with the memory cycle and operating speed of the image memory, which poses a problem in that it takes time to draw figures. Moreover, the improvement in speed also depends on the speed of the memory, and there are memory constraints such as the need for high-speed memory, and in order to increase the speed, it is necessary to use expensive memory.6 This invention solves the above-mentioned conventional problems. It is an object of the present invention to provide a graphic drawing device that is designed to solve the problem and can perform drawing processing in a short time regardless of memory cycles and operating speed.

(d) Means for solving the problem The present invention provides means for setting starting point and ending point data of a line segment;
Line drawing means for creating a line segment according to start point and end point data; an image memory for storing pixel data created by the line drawing means; address detection means for detecting changes in addresses of the pixel data in both the X and Y directions; means for detecting the number of bits of the pixel data; processing bit number determining means for determining the number of bits to be processed at once based on a ratio of the cycle time of the image memory and the processing cycle time of the line drawing means; detecting an address change in a direction other than that in which batch processing is possible, or writing the pixel data in a batch to the image memory when the number of bits of the pixel data matches the number of bits of the processing bit number determining means; It is characterized by

(E) Function According to the present invention, a plurality of dots can be simultaneously drawn in one image memory read and write cycle. Therefore, the drawing speed can be improved by increasing the number of dots drawn simultaneously, regardless of the image memory cycle.

(f) Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block circuit diagram illustrating one implementation of the present invention.

In Figure 1, 1 is an image memory, and as shown in Figure 3, this image memory l has 8 bits for each address in the X direction and 8 bits for each address in the Y direction, depending on the number of processing bits of the processor. The data is memory mapped in units of l bits.

30 is an address calculation unit for setting write and read addresses of the image memory 1, an address register 2 for storing address data, and a random access memory (for storing parameters for calculating addresses).
Hereinafter, it will be abbreviated as RAM. ) address memory 6 consisting of
, and an address arithmetic circuit 5 which adds and subtracts data from the address memory 6 and calculates an address.The address data subjected to the address calculation by the address arithmetic circuit 5 is stored again in the address register 2 and the address memory 6.

3 is a data register for storing data written and read from the image memory l.

On the other hand, the address arithmetic circuit 5 outputs a carry output to the data bus 4 every time the address changes, and this carry output is input to the controller 14 via the bus 4.

The controller 14 detects a change in the address of the image memory 1 based on this carry output.

The output of the address memory 6 is a read-only memory (hereinafter abbreviated as ROM) 7.8 in which the dot array to be drawn in the image memory 1 is stored according to each address of the memory.
given to. This ROM7 stores an array (MRML) for the address (SXL) as shown in FIG. 9(a), and the ROM8 stores an array (MRMR) for the address (SXR) as shown in FIG. 9(b). is memorized.

Both ROMs? .
is stored in

40 is a line drawing processing circuit which calculates drawn dots based on the Presentham algorithm, and register 17.1.
8.20, a multiplexer 16.19, and an adder/subtractor 15.

Reference numeral 22 denotes a parameter RAM in which parameters used for line drawing calculations are stored, and the starting point and ending point data J (XS, YS) are input from the outside via the data bus 4.
(XE, YE) and parameters of the Bresenham algorithm based on both data are stored. Furthermore, this parameter RAM 22 stores the number of processing bits ( C.N.T.E.
) is set.

13 is a counter that counts the number of processing cycles of the line drawing circuit 40, 21 is an adder/subtractor, and the parameter RAM 2
2. Calculate each data and set each parameter as parameter RA.
Store again in M22.

23 is a DIR register in which data of the linear vector shown in FIG. 5 is stored.

Next, the operation of the present invention will be further explained.

In the image memory 1 of this embodiment, as shown in FIG. 3, 8 bits, ie, 1 byte, are allocated to the X address l. Therefore, for example, when drawing dots of 3 bits at each address in the X direction as shown in FIG.
Conventionally, the address No. 1 in the X direction and the address No. 5 in the X direction are specified three times, read out, logical summed, and rewritten. In contrast, in the present invention, the number of processing bits determined by the ratio of the memory cycle to the processing cycle of the line drawing processing circuit 40 is written into the image memory l at once.

In this embodiment, it is assumed that the speed of the line drawing circuit 40 is capable of processing three times per one memory cycle, as shown in FIG. 7, and three calculations are performed per one memory cycle. .

Therefore, the access condition for the address of image memory l is the eighth
As shown in the figure, when the hatched dot changes in the direction of the arrow, the controller 14 controls 11J to write line dot data into the image memory 1. That is,
If the address changes in the X direction as shown in Figure 8(a), or if the address changes in the X direction as shown in Figure 8(b), or as shown in Figure 8(C), , when the total processing cycle time of the line drawing processing circuit 40 from the previous memory access becomes equal to the memory cycle,
In this embodiment, when three processes are completed, the image memory 1 is accessed and line drawing dots are written from the data register 3 into the image memory 1.

Now, to explain the above-mentioned operation with reference to FIG.
E) from the outside via data bus 4, the parameter RA
Each parameter of the Bresenham algorithm is calculated based on this data, and each parameter is stored in a predetermined area of the parameter RAM 22. This series of operations is executed under the control of the controller 14.

Furthermore, the ratio of the memory cycle time when the processing cycle time of the graphic drawing processing circuit 40 is set to 1 is given to the parameter RAM 22 as a variable CNTE. In this embodiment, 3 is stored.

Each data from this parameter 22 is given to each register 17, 18 and 20 of a line drawing circuit 40 which draws a line based on the Bresenham algorithm. This register 17
．． Digital differential analysis (DDA) will be discussed later in 18.20.
), each drawing dot of the line segment is calculated and provided to the controller 14 via the multiplexer 16 and the adder/subtractor 15. The controller 14 provides this created data to the address calculation section 30.

In the address calculation section 30, the above-mentioned created data is input to the address memory 6, and the data input to the address memory 6 is compared with the data input last time.
The controller 14 determines whether there is a change in the address described above.
is to judge.

Further, the counter 13 counts the number of processing cycles of the drawing processing circuit 40. That is, each time the drawing processing circuit 40 processes, the counter 13 counts up, and the value of this counter 13 is compared with the value of CNTE of the parameter RAM 22.

When the created data from the drawing processing circuit 40 satisfies the access conditions shown in FIG. By writing the drawn dots obtained by ANDing both array patterns in the AND circuit 9 to the image memory 1 via the data register 3, a plurality of dots are written to the image memory 1 at once within 1 memory cycle. Then, as shown in FIG. 6, a line is drawn in the image memory l.

Next, the operation of this embodiment will be further explained according to the flowchart of FIG. 1O.

When the operation starts, each register and the parameter RAM 22 are initialized in step S1, and the number of bits that can be drawn in the image memory l is written all at once into CNTE of the parameter RAM 22, and the process proceeds to step S2.

In step S2, the data of the start point (XS, YS) and end point (XE%YE) input from the outside via the data bus 4 for line drawing are stored in a predetermined area of the parameter RAM 22.

Next, the distance between the starting point and the ending point of the X and Y coordinates is determined based on the Presentham algorithm. That is, DX=X
E-XS, DY=YE-YS (7) calculation is performed, and the calculation result is stored in a predetermined area of the parameter RAM 22. Then, D indicates the direction of the line vector shown in FIG.
Assuming that the flag FLl corresponding to the 3rd bit of the flag representing IR as a binary number is "1", the parameter RAM2
2 and proceeds to step S4.

In step S4, it is determined whether DY is positive or negative. If it is negative, the process proceeds to step S5, where DY is multiplied by "-1'°, the value is re-stored in a predetermined area of the parameter RAM 22, and the flag FLI is set to 0. '', the process advances to step S6.

In step S4, if DY is positive, the process directly advances to step S6.

In step S6, it is determined whether DX is positive or negative, and if it is negative, the process proceeds to step S7, where DX is multiplied by "-1" and the value is re-stored in a predetermined area of the parameter RAM 22.
After setting the flag FL2, which corresponds to the second bit of the flag indicating DIR in binary, to "1", the process proceeds to step S8.

In step S6, if DX is positive, the process directly advances to step S8.

In step S8, it is determined which of the inclinations in the X direction and the Y direction is larger, that is, DX<DY. If the inclination in the Y direction is larger (DX<DY), in step S9, DX and DY are exchanged, and DIR is After setting the flag FL3, which corresponds to the first bit of the flag expressed in binary, to "bi", the process proceeds to step S10.

If the inclination in the X direction is large, that is, DX is larger than DY, the process directly proceeds to step SIO. At this time, FL3 remains at the initial setting of 0''.

Then, in step SIO, the linear direction vector DI
Calculate R, store the value in the DIR register "?3, and then calculate the parameter C0N based on the Presentham algorithm.
52 is calculated and stored in the corresponding register 17.

Furthermore, in step Sit, the errors E and C0N5L of the parameters of the Presentham algorithm are calculated and stored in the corresponding registers 18 and 20, respectively, and the process proceeds to step 312.

In step S12, X of the parameter RAM 22,
While storing xS%YS in each Y area, the absolute address SX is determined and stored in a predetermined area of the parameter RAM 22, and the process advances to step S13.

In step 313, the line segment counter C1 is counted up and the count value is stored in a predetermined area of the parameter RAM 22.

Subsequently, in step S14, the line drawing processing circuit 40
The counter 13 counts up the number of processing cycles, and the process advances to step S15.

In step S15, the area x of the address memory 6
The values of X and Y of the parameter RAM 22 are stored in O and Y, and the address of the image memory l is calculated. Then, the ROM 7 is accessed by the lower bits of xO of the address memory 6. That is, this lower bit is shown in FIG. 9(b).
This corresponds to SXH.

Then, in step S16, subroutine DDA
Call I. The subroutine DDAl is shown in FIG. 11(a).
As shown in , by digital differential analysis (DDA),
For the line direction vector (D I R), the XY of the next drawing
The address is determined, and the address is sequentially given to the address calculation section 30 to rewrite the address memory 6. When subroutine DDA 1 ends, the process advances to step S17. At this time, when the condition shown in FIG. 8(a) occurs, the flag FL in the parameter RAM 22 is set to "1''.

In step S17, it is determined whether the value of the register 20 is greater than "0" based on the Presentham algorithm. If it is greater than '0', the process proceeds to step S18, and if it is smaller, the process proceeds to step S19.

If E is larger than O'', in step 818, subroutine DDA2 is called, and the value of E in register 2 and the value in register 18 are added in adder 15 and stored in register 20 again. As shown in FIG. 11(b), the XY address of the next drawing is determined for the line direction vector (DIR) by digital differential analysis, and this address is sent to the address calculation unit 3.
0 successively and rewrites the address memory 6. When subroutine DDA2 ends, the process advances to step S20.
At this time, when the condition shown in FIG. 8(a) occurs, the flag PL in the parameter RAM 22 is set to 1''.

On the other hand, in step S19, the value of the register 20 and the value of the register 17 are added by the adder 15 based on the Presentham algorithm, the resulting value is stored again in the register 20, and the process proceeds to step S20.

In step S20, the absolute address of the newly calculated X address is determined and the process proceeds to step S21.

In step S21, the value CNT of the counter 13 and 1
When CNT is equal to 1, that is, it is the first X address of the Y coordinate, the process advances to step S22.

In step S22, the ROM 7 is accessed using the lower bits of xO stored in the address memory 6. That is, this lower bit corresponds to SXL in FIG. 9(a). Then, the process advances to step S23.

On the other hand, in step S21, if CNT and CNTE are not equal, the process directly advances to step S23.

In step S23, it is determined whether the conditions shown in FIG. 8 are satisfied, that is, whether or not the image memory 1 is to be accessed in order to write drawn dots in the image memory 1 all at once. If any of the conditions shown in FIG. 8 is satisfied, the process proceeds to step S24, and if none of the conditions are satisfied, the process proceeds to step S26.

In step S24, the physical address of the image memory 1 is determined, and the ROM 8 is accessed using the lower bits of xO. This lower bit corresponds to SXR in FIG. 9(b). Furthermore, the counter 13 is cleared and step S
Proceed to step 25.

In step S25, the calculated drawing dots are written in the image memory 1 all at once. That is, as shown in FIG. 4, ROM? , 8 output is AND circuit 9, OR circuit 1
The data that had been written to the data processing RAM 1l via the data register 2 is written from the data register 3 to the area specified by the address calculation unit 30. For example, in the examples of FIGS. 3 and 6, X address 1. Y address 5
Three dots are drawn in one memory cycle in the area.

Thereafter, in step S26, it is determined whether or not the line drawing counter value C1 has become equal to DX. If not, the line segment has not been drawn, and the process returns to step S13 to repeat the above-described operation. When they are equal, the drawing of the line segment has ended, so step S2
Proceed to step 7.

Then, in step S27, the physical address of the end point is determined, and in step S28, the end point dot is drawn in the image memory 1, thereby terminating the operation.

FIG. 2 shows a second embodiment of the present invention, and the differences from the embodiment in FIG. 1 are as follows:
The dot array is stored in two ROMs 7.8, and the AND circuit 10 calculates the logical product of both values.In contrast, in the second embodiment, as shown in FIG. 9(C) One ROM 7a having a pattern arrangement is used, and the AND circuit is omitted, and the other configuration is the same as that of FIG. 1.

FIG. 12 is a flowchart showing the operation of the second embodiment of the present invention shown in FIG. As mentioned above, the first embodiment and the second embodiment use a ROM that stores the dot array.
Since only the configuration is different, only that part is different in this flowchart. That is, step 515
Only step a and step 824a are different, and step 821.22 in FIG. 10 is omitted. Both steps differ only in the access to the ROM, and are substantially the same as those in FIG. 10.

Further, the other steps are the same as those in FIG. 10, so the same step numbers are given here and the explanation is omitted.

(G) Effects of the Invention As described above, according to the present invention, a plurality of dots can be simultaneously drawn in one image memory read and write cycle. Therefore, the drawing speed can be improved by increasing the number of dots drawn simultaneously, regardless of the image memory cycle.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing a first embodiment of the present invention;
FIG. 2 is a block circuit diagram showing a second embodiment of the present invention. FIG. 3 is a schematic diagram showing the storage area of the image memory used in the present invention, and FIG. 4 is a schematic diagram showing dots written in the image memory. FIG. 5 is an explanatory diagram showing line direction vectors, FIG. 6 is a schematic diagram showing a state in which line drawing is performed according to the present invention, and FIG. 7 is a timing chart showing the relationship between memory cycles and arithmetic processing cycles. FIG. 8 is a schematic diagram showing conditions for writing to an image memory according to the present invention. FIG. 9 is a diagram showing the relationship between addresses and dot arrays in this embodiment. FIG. 10 is a flowchart explaining the operation of the first embodiment of the invention, FIG. 11 is a flowchart showing digital differential analysis, and FIG. 12 is a flowchart explaining the operation of the second embodiment of the invention. be. 1... Image memo 1c 14... Controller. 22...Parameter, 30...Address calculation section, 4
0...Line drawing circuit. Figure 2 Figure 10 (b) A Figure 10 (C) Figure 11 (a) Figure 11 (b) Figure 12 (b) Figure 12 (C)

Claims (1)

[Claims] (1) A means for setting the starting point and end point data of a line segment, a line drawing means for creating a line segment according to the starting point and end point data, an image memory for storing pixel data created by this line drawing means, an X of the pixel data , address detection means for detecting changes in both addresses in the Y direction, means for detecting the number of bits of the pixel data, and the number of bits to be processed at once based on the ratio of the cycle time of the image memory and the processing cycle time of the line drawing means. processing bit number determining means for determining the number of processing bits, and the address detecting means detects an address change in a direction other than that in which batch processing is possible, or the number of bits of the pixel data is equal to the number of bits of the processing bit number determining means. A graphic drawing device characterized in that when a match occurs, the pixel data is written all at once into an image memory.