JPH0411426A - serial transmission system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a serial transmission system for exchanging data between multiple microcomputers installed within a short distance.

[Prior art]

Conventionally, various control systems in automobiles have been independent, and a microcomputer has been used for each system. However, when considering the sharing of resources and the integration of control systems, it is necessary to send and receive data between each control system. For data transmission between each system, serial transmission is desired in order to reduce the amount of wiring. Serial transmission between microprocessors requires
There are cases where the serial input/output function of a microprocessor is used, and cases where a dedicated interface circuit is used. The former is IIART (llniversal As
ynchronous Receiver Trans
Asynchronous bidirectional serial communication called mitter is common. The latter network has three types: loop type, bus type, and star type.

[Problems to be solved by the invention]

11ART is basically an l:1 communication function, so
It is not suitable for exchanging data between multiple microcomputers. In bus-type networks, it is difficult to use optical fiber as the transmission path. Therefore, high-speed communication is not possible when used in a noisy environment such as in a car. In addition, in a star-type network, communication concentration and communication load at the center node of the star are large, making it suitable for small-scale systems. In order to solve the above-mentioned problems, the present inventor invented a method described in Japanese Patent Application Laid-Open No. 157546/1983 as a loop-type data exchange method between a plurality of computers with a simple structure. In this method, shift registers are arranged in a ring, and the shift registers essentially form a transmission path, and data input/output between the computer and the transmission path is controlled via the shift registers. . In this method, it is necessary to detect the empty state of the transmission path so that data frames output from each node do not collide. That is, it is necessary to determine whether there is an empty state in the shift register in which a new data frame can be generated. Therefore, it was required that the data frame length be shorter than the number of digits of one shift register. On the other hand, in order to reduce the amount of hardware in the input interface circuit and to shorten communication delay, it is desirable that the number of digits in one shift register be small, and therefore it has been impossible to increase the size of the data frame. As a result,
There has been a problem in that the proportion of communication data containing substantial information in a data frame is small. The present invention has been made to solve the above problems, and its purpose is to easily exchange data between multiple computers with a simple configuration. The purpose of this invention is to improve transmission efficiency by making it possible to make the data length of one data frame longer than the number of digits of one shift register.

[Means to solve the problem]

The configuration of the invention for solving the above problems is, as shown in FIG. 1, a data transmission system between a plurality of computers A1 to An.
Transmission line B configured in a ring shape for data transmission between n
and input/output interfaces 01 to Cn, which are arranged between the transmission line B and the computers A1 to An, and control data input/output between them, and the transmission line is connected to the input/output interface CI-Cn. Shift registers F1 to Fn for inputting and outputting serial data to and from B are provided, each of the shift registers F1 to Fn is inserted in series into the transmission line B, and each of the shift registers F1 and Fn is
In a transmission system in which data is circulated by sequentially shifting each of the shift registers of ~Fn, there is provided a status signal output means for outputting a status signal indicating whether or not its own shift register is in a predetermined empty state; and data generation means for generating a data frame when a status signal indicating that the shift register of the input interface is in a predetermined empty state is input and the shift register of the input interface is in a predetermined empty state of data. That's true.

[Effect]

In a system in which the distance between computers is short, such as a system installed in a car, the data propagation delay time in the transmission path B can be ignored. Therefore, the shift registers F1 to Fn inserted in series in the transmission path B become the actual transmission path, and the data to be transmitted is stored in these shift registers F1 to Fn, and is synchronized with one synchronization signal. It circulates through the shift registers F1 to Fn while shifting one bit at a time. When generating a data frame, it is determined whether the own shift register in the input/output interface that generates the data frame is in a predetermined empty state. Furthermore, it is determined from the input status signal whether the shift register of the upstream input/output interface is in a predetermined empty state. Here, the predetermined empty state in both shift registers is the difference between the lower empty bit of its own shift register (input side of the shift register) and the upper empty bit of the upstream shift register (output side of the shift register). This means that the sum is larger than the data length of one data frame. Therefore, if the above two conditions are met, even if a data frame is generated in its own shift register, collisions between subsequent data frames can be prevented. As described above, in the present invention, the empty state of an upstream shift register can be determined by inputting a status signal indicating a predetermined empty state of the upstream shift register from the upstream interface. Therefore, data collision does not occur even if the data frame length is longer than the bit length of each shift register F1 to Fn, so it is possible to carry multiple data on one data frame, and the transmission efficiency (communication data/
data frame).

【Example】

The present invention will be described below based on specific examples. (1) Overall configuration As shown in FIG. 2, this embodiment uses three microcomputers and allows data to be transmitted and received between them. Each of the microcomputers A1 to A3 is connected to each input/output interface 01 to C3, and these input/output interfaces (hereinafter also referred to as "nodes") are inserted in series along the transmission line to form a ring-shaped transmission line. is formed. The microcomputer AI is responsible for controlling the entire vehicle, controlling the display on the dash board, and controlling switches for lights, wipers, air conditioner, radio, etc. The microcomputer A2 controls the power train, and performs fuel injection control, ignition timing control, throttle opening control, etc. The microcomputer A3 performs chassis control, and performs suspension control, brake control, etc. (2) Structure of Data Frame As shown in FIG. 3, the data frame is composed of a start data section DA, a data identification data section DB, a data section DD, and a stop data section DE. The data identification data section DB is composed of a frame identification data section DBI and a data address data section DB2. Data identification data part DB and data part DD are subjected to simple code processing, and the center of the bit always changes from "1" to "0" or "0".
The structure is such that a change of 1' occurs from . The start data section DA has a structure in which two bits of "0" continue. Further, the stop data section DE is configured to be "1" continuously for one bit. On the other hand, when there is no data on the transmission path, that is, when there is no data frame or status signal and the transmission path is idle, the transmission path is always at the "1" level. With this configuration, the start of a data frame can be easily detected. By performing code processing on both the data identification data section DB and the data section DD, the signal change at the center of the bit has a clock component, so there is no need to use a common external synchronization signal, and the internal clock of each input/output interface section can be used. , a synchronization signal is generated from the clock component due to signal change, and 1
Shifts the data frame on the shift register bit by bit. The frame identification data section DBI indicates the node address of the node that generates the data frame and transmits the data. The data address data section DB2 is for identifying one set of data to be transmitted and received, and indicates the address of one set of data. The data portion DD constitutes data to be transmitted and received, and in this embodiment, three pieces of data, DDI-DD3, are transmitted. Each of the three pieces of data is 8 bits. The length of the data section DD depends on the length of the shift register, and there is a constraint that the total data frame length must be shorter than the length of empty space on the transmission path that can be confirmed from the status signal and the status of the data frame on the shift register. It can be changed within the range that satisfies the following. (3) Status signal As shown in FIG. 4, the status signal is composed of a start signal SA and an empty status signal SB♂stop signal SE. The start signal SA has a configuration in which 0' continues for one bit, and then 21' continues for one bit. The empty state signal SB has a configuration in which '0' continues continuously. Also, the stop signal SE is a signal of 1 bit interval ml' like the stop data of the data frame. (4) Configuration of input/output interface The input/output interfaces C1 to Cn are configured as shown in FIG. A decoder 11 is connected and an encoder 20 is connected to the output side.The decoder 11 decodes the encoded bits of the data frame input from the transmission path B, and the encoder 20 encodes the bits of the frame data. Further, a data frame detection circuit 14 is connected to the shift register 13, and the data frame detection circuit 1
4 detects the start data section DA to detect the beginning of the data frame. When the beginning of the data frame is detected, a start data detection signal is output to the transmission/reception control circuit 23. Further, a data identification data receiving register 15 is connected to the shift register 13 . The data identification data reception register 15 is connected to the data frame detection circuit 14.
The frame identification data section DBI and data that appear on the shift register 13 in synchronization with the control signal output from the transmission/reception control circuit 23 are timed by the synchronization signal input after the start data detection signal output from the transmission/reception control circuit 23 is input. Input the data in the address data section DB2. These frame identification data and data address data are output to the transmission/reception control circuit 23. In addition, the shift register 13 includes a receive data register 16.
is connected, and the reception data register 16 takes in the data in the data section DD on the shift register 13 in response to a control signal from the transmission/reception control circuit 23. When receiving a data frame, the transmission/reception control circuit 23 compares the node address of the input/output interface C1 sent from the microcomputer A1 with the value of the received frame identification data, and if they match, erases the data frame. Then, "work" is written to the transmission line B via the multiplexer 22, and furthermore, the state signal generating circuit 19 generates an empty state signal. Further, if the node address of the input/output interface C1 and the value of the received frame identification data do not match, the data is transferred to the address of the reception data register 16 corresponding to the data address data input to the data identification data reception register 15. The data of section DD is input. The shift register 13 also includes a transmission data register 17.
and a data identification data transmission register 18 are connected. Transmission data register 17 is microcomputer A
1, and outputs the data to the shift register 13 in synchronization with the control signal output from the transmission/reception control circuit 23. The data identification data transmission register 18 sets the data address data and frame identification data (node address) of the transmission data output from the microcomputer A1, and the transmission/reception control circuit 23
It outputs the control signal to the shift register 13 in synchronization with the control signal output from the shift register 13. After receiving or transmitting a data frame, the transmission/reception control circuit 23 monitors the state of the data frame on the shift register by counting synchronization signals, and detects whether the shift register 13 has become empty. When the shift register 13 is empty, the status signal generating circuit 19 outputs a status signal to the transmission path B indicating that the shift register 13 is empty. Furthermore, even if a data frame is generated from the own shift register depending on the empty state of the own shift register 13 and the signal level of the status signal output from the previous node (upstream side of the data flow) from the status signal monitoring circuit 24, the data When it is confirmed that there will be no frame collision, the transmission/reception control circuit 23 controls the multiplexer 22 to generate the start data DA output from the start data generation circuit 21.
is output to transmission path B. Next, data identification data composed of frame identification data in which a node address is written and data address data that is the address of data corresponding to the data to be transmitted is written from the data identification register 18 to the shift register 13, and the transmission data register 17 Write the data set in the shift register 13. The data on shift register 13 is shifted one bit at a time by a synchronizing signal, and the data in shift register 1 is shifted by the synchronizing signal.
The timing of input or output to 3 is controlled. As the synchronization signal, a clock obtained by dividing the basic clock is used. However, when a data frame is input, the phase of this synchronization signal is corrected in the clock generation circuit I2 by a clock component included in the data frame. On the other hand, when controlling the output timing, a synchronization signal obtained by dividing the basic clock is used as is. In addition, reception data register 16 or transmission data register 1
By configuring 7 with a 2-bot RAM, input/output to the shift register 13 and input/output to the microcomputer A1 can be performed in parallel and independently. (5) Data transmission Data can be transmitted from all input/output interfaces. In addition, since all the input/output interfaces have similar functions, the input/output interface C1 shown in FIG.
The explanation will be based on. The node address of input/output interface C1 is "001", and there are three pieces of data to be sent.
rooool those data address data,
Let them be rooloJ and rooollJ. Prior to transmission, the node address "001" of the interface C1 is given to the transmission/reception control circuit 23 from the microcomputer A1. The transmission/reception control circuit 23 receives this data and writes frame identification data r001J into the data identification data transmission register 18. Next, transmission data is sent from the microcomputer A1. At this time, each data address data is
roooolJ, ro 0010J, roooll" three data rl O10111O", I"11Q
01100'' and roolooolooJ are sent. As a result, data address data r00001'',
"rloolo" and "rlololl" are stored in the transmission data register 17 at the address corresponding to rooollJ, respectively.
lo”, rllooolloo”, roolooooloo”
is written. The transmission/reception control circuit 23 detects that data has been written to the transmission data register 17, and moves to execution of a data transmission procedure. It is determined whether the transmission path is empty or not, that is, the transmission path empty status signal has arrived from the upstream input/output interface C3, and the previous data frame has already passed through the shift register. , confirm that no data collision occurs even if a data frame is generated. If it is free, start data is immediately sent to the interface C2. Immediately after the start data, frame identification data "001" is added, followed by data address data roo representative of the three data. Ol”, followed by three pieces of data N 010111
0J, rllooolloo", rooloooloo",
Then, the last stop data is written onto the shift register 13 and sent to the next input/output interface C2. Once one data frame has been transmitted from an input/output interface, the next data can be transmitted after a time interval has elapsed during which one data frame can be transmitted from each of the other input/output interfaces. In this way, when data transmission is commanded from the microcomputer A1, a set of three pieces of data is sequentially transmitted from the input/output interface C1 at fixed time intervals. Data can then be transmitted from other input/output interfaces during that free time. (6) When the start data arrives at the data reception input/output interface C1, the data frame detection circuit 14 detects the beginning of the frame and outputs a frame detection signal to the transmission/reception control circuit 23. When the transmission/reception control circuit 23 receives the frame detection signal, it counts a predetermined number of synchronization signals and then takes out the frame identification data to the data identification data reception register 15 at the timing when the frame identification data can be taken out from the shift register 13. The transmission/reception control circuit 23 determines whether the frame identification data taken out to the data identification data register 15 is equal to the node address of the input/output interface C1, and if the data frame is equal to the node address of the input/output interface C1, the data frame received by the shift register 13 is This is a data frame transmitted from the input/output interface C1, and means that the data frame has gone around the serial transmission system. Therefore, in that case, by outputting "1" equal to the length of the data frame from the beginning of the data frame to the shift register 13, the data frame is erased and the shift register is set to an empty state indicating that there is no data frame. Generate a signal. On the other hand, if the frame identification data of the received data frame does not match the node address of the received input/output interface, it means that the data frame was sent from another input/output interface, and the data Import is performed. The transmission/reception control circuit 23 measures the timing based on the synchronization signal after inputting the start data.
At each successive output timing, the representative data address data is transferred from the shift register 13 to the data identification data receiving register 1.
5, and three pieces of data are read to the reception data register 16. The three pieces of data are stored in the reception data register 16 in correspondence with the address indicated by the representative data address data taken into the data identification data reception register 15 and the address following that address. In this embodiment, all data sent from other input/output interfaces is read, but only the necessary data is selectively read by the microcomputer connected to the received input/output interface. It may also be read out. Note that if the configuration is configured to read all data, the configuration of the transmission/reception control circuit 23 becomes simple, and all the input/output interfaces can have the same configuration. (7) Initialization of transmission path The data stored in the shift register 13 of each input/output interface is initialized to "1" at reset. This initialization prevents false detection of data frames. Data frames generated at each input/output interface are erased at each generated input/output interface based on frame identification data, but if this frame identification data becomes a value that does not belong to any input/output interface due to noise etc. There is. At this time, the data frame will continue to circulate around the transmission path forever. To prevent this, it is necessary to initialize the transmission path at certain intervals, or to monitor such data frames at the master node and eliminate data frames with non-existent frame addresses. The positional relationship of the data identification data reception register 15, reception data register 16, transmission data register 17, and data identification data transmission register 18 connected to the shift register 13 shown in FIG. Since the position can be known from the count number of the synchronization signal after the start data is detected, it can be set quite freely by controlling the input/output timing for each register. Further, data input/output between each register and the shift register 13 may be performed at once in parallel data format, or may be performed one bit at a time in synchronization with a synchronization signal in serial data format starting from one digit of the shift register 13. . Further, although the data frame shown in FIG. 3 is not provided with check bits for checking received data, it is desirable to add some check bits to check the data upon reception. The check bit is 1 for the entire data frame.
Either one bit may be added, or one bit may be added for each frame identification data, data address data, and data. In this case, a parity bit generation circuit and a parity bit check circuit are added to the input/output interface shown in FIG. As described in detail above, according to the present invention, it is possible to check the availability of a transmission path with a simple configuration, and to construct a transmission system in which data frame collisions do not occur. Moreover, since all the input/output interfaces can be configured in the same way, it is possible to incorporate the input/output interfaces into the microcomputer as the input/output function of the microcomputer. Furthermore, a photoelectric conversion element is placed on the input side of the shift register.
By connecting an electro-optical conversion element to the output side of the shift register and using an optical fiber as the transmission path, it is possible to construct a transmission system that is resistant to fiber noise, particularly a highly reliable transmission system for automobiles.

【Effect of the invention】

The present invention connects shift registers that can store data frames in a ring, and circulates the data while shifting the data on the shift registers one bit at a time in synchronization with a synchronization signal, and inputs and outputs data to and from each shift register. Since data is transmitted serially by using the following steps, data can be easily transmitted between multiple computers. Furthermore, it is possible to detect a predetermined empty state of the upstream shift register based on the status signal output from the upstream interface. Therefore, when it is detected that the own shift register is in a predetermined empty state and the predetermined empty state of the upstream shift register is detected from the status signal, the data frame is transferred without colliding with the subsequent data frame. It becomes possible to output to its own shift register. As a result, without increasing the number of shift register stages,
Transmission efficiency (communication data/data frame) can be increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the concept of the present invention. FIG. 2 is a block diagram showing the overall structure of a serial transmission system according to a specific embodiment of the present invention. FIG. 3 is a configuration diagram showing the configuration of a pig frame transmitted and received in the system of the embodiment. FIG. 4 is a configuration diagram showing the configuration of status signals transmitted and received in the system of the embodiment. FIG. 5 is a block diagram showing the configuration of the interface used in the system of the embodiment. 24 Status signal monitor circuit

Claims (1)

[Claims] A data transmission system between multiple computers,
consisting of a ring-shaped transmission path for transmitting data between the plurality of computers, and an input/output interface disposed between the transmission path and the computer to control data input/output between them; A shift register for inputting and outputting serial data to and from the transmission line is provided in the input/output interface, each of the shift registers is inserted in series into the transmission line, and each bit of each of the shift registers is sequentially changed in synchronization with a synchronization signal. In a serial transmission system that circulates data by shifting, the input/output interface includes: status signal output means for outputting a status signal indicating whether or not its own shift register is in a predetermined empty state; Generates a data frame when a status signal indicating that the shift register of the upstream input interface is in a predetermined empty state is input from the input interface, and the own shift register is in a predetermined empty state of data. A serial transmission system comprising: data generation means.