JPH04114261U - Vertical deflection linearity correction circuit - Google Patents

Abstract

(57) [Summary] [Objective] To provide a vertical deflection linearity correction circuit that can obtain good vertical deflection linearity at all frequencies even when the vertical synchronization frequency is switched over a wide range to a plurality of values. [Structure] The negative vertical sawtooth voltage appearing on the feedback resistor 6 is input to the electronic volume 15. electronic volume 15
is the vertical oscillation circuit 1 by controlling the amplitude of the vertical sawtooth voltage.
supply to. The fv-v conversion circuit 14 supplies an fv-v voltage proportional to the vertical synchronization frequency of the input vertical synchronization pulse to the electronic volume 15. Electronic volume 15 is fv
By controlling the amplitude of the vertical sawtooth voltage according to the -V voltage, good vertical deflection linearity is always obtained regardless of the vertical synchronization frequency.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

This invention is a vertical deflection linearity correction device used in various image display devices using picture tubes. Regarding circuits.

0002

[Conventional technology]

FIG. 5 is a block diagram showing a vertical deflection circuit including a conventional vertical linearity correction circuit. . By the way, the purpose of the vertical deflection circuit is to attach a vertical saw with good linearity to the vertical deflection coil. The idea is to vertically deflect an electron beam by passing a wave current. Vertical deflection times shown in Figure 5 The vertical oscillation circuit 1 is synchronized with the vertical synchronization pulse supplied from the input terminal. The vertical amplifier circuit 2 amplifies this vertical sawtooth voltage. do. The vertical output circuit 3 outputs the vertical sawtooth current from the vertical sawtooth voltage. A vertical sawtooth wave current, which is a vertical deflection current, is passed through the vertical deflection coil 4. Sara , the vertical sawtooth current flows through the coupling capacitor 5 and into the feedback resistor 6. The voltage is converted into a voltage by this, and this voltage is negatively fed back to the vertical oscillation circuit 1. stop Therefore, the vertical oscillation circuit 1 receives the negative feedback vertical sawtooth voltage and the vertical oscillation circuit 1. The absolute value slope of both sawtooth waves is compared with the vertical sawtooth wave voltage created by The vertical sawtooth current with good linearity is applied to the vertical deflection coil. It will flow to 4.

0003 7(A) to (C) are circuit diagrams for explaining the vertical oscillation circuit 1 in FIG. 5. . Here, FIG. 7(A) shows a basic circuit of the vertical oscillation circuit 1. First, in Figure 7(A) When a DC voltage VB is applied to the base of the PNP transistor 9, the charging/discharging circuit is turned on. The capacitor 10 has a constant current determined by a DC voltage VB, a power supply voltage Vcc, and a resistor 8. will be charged. Therefore, the voltage across the capacitor 10 is as shown in FIG. 8(A). In the period from time 0 to t0, it increases linearly with time t. After that, N.P. When a vertical synchronizing pulse is input to the base of N transistor 11, the collector-emitter conduction between the capacitors and the capacitor 10 is instantly discharged during the period from time t0 to t1. Ru. This charging and discharging is repeated, and both ends of the capacitor 10 are synchronized with the vertical synchronizing pulse. A vertical sawtooth voltage is generated, and this vertical sawtooth voltage is used as a reference signal to circulate. Since the path moves, good linearity can be obtained.

0004 However, in reality, as shown in FIG. 7(B), there is some kind of load on the vertical oscillation circuit 1. (load resistor 12) should be connected, so the current also flows to this load resistor 12. will flow in separate streams. The shunt current flowing through the load resistor 12 is connected to the capacitor 10. As the voltage increases as the capacitor 10 is charged, the voltage across the capacitor 10 will eventually become as shown in FIG. As shown in B), the waveform changes from a linearly increasing waveform to an exponentially decreasing waveform. . If this waveform is used as a reference signal, for example, a pattern with a constant grid interval can be input. When a force is applied, the image that appears on the picture tube surface will stretch at the top and expand at the bottom, as shown in Figure 6. Shrink.

[0005] In order to correct this distortion of vertical linearity, such as elongation at the top and contraction at the bottom, As shown in 7(C), a vertical sawtooth voltage with a negative slope is applied to the coupling It is input to the base of transistor 9 through capacitor 13. Then, the capacitor In the first half of the charging period to 10, the charging current is suppressed, and in the second half, It acts to promote the charging current and increases the charging current in a quadratic manner. and , by adjusting the amplitude of this negative vertical sawtooth voltage to reduce the current through the load resistor 12. 8(C), the voltage across the capacitor 10 increases linearly. It approximates the waveform. The negative vertical sawtooth voltage is applied to the feedback resistor as shown in Figure 5. It is common to divide the resistance from the resistor 6 and correct the waveform using the waveform correction circuit 7. .

[0006]

[Problem that the idea aims to solve]

By the way, in the conventional vertical deflection linearity correction circuit described above, the vertical synchronization frequency In the case of a certain frequency, the division ratio of the resistance division from the feedback resistor 6 should be optimized. By doing so, good vertical deflection linearity can be obtained. However, vertical In cases where the synchronization frequency is switched over a wide range to multiple , it is possible to obtain good vertical deflection linearity at one of the frequencies. Even if there is, it is difficult to perform optimal correction at other frequencies.

[0007] This is because the amplitude of the negative vertical sawtooth voltage used for correction is set to the vertical sync frequency Even if it is constant regardless of , when the amplitude of the vertical deflection current is controlled by frequency, the negative value used for correction is (The amplitude of the vertical sawtooth voltage is also constant), and the linearity correction amount is inversely proportional to the frequency. This is because it is proportional. To further explain using FIG. 9, as shown in FIG. 9(B), (A) If the frequency is low as shown in (the lower the frequency, the more correction is required) If the frequency shown in (C) is high, it will be under-corrected. I end up.

[0008]

[Means to solve the problem]

In order to solve the problems of the conventional technology mentioned above, this invention provides vertical synchronization pulses. a vertical oscillator circuit that generates a vertical sawtooth voltage, and the vertical sawtooth voltage generates a vertical deflection current and supplies this vertical deflection current to the vertical deflection coil. Vertical output circuit and control the amplitude of the vertical sawtooth voltage obtained from the vertical deflection current. an amplitude control circuit that controls and supplies the vertical oscillation circuit to the vertical oscillation circuit; to generate a voltage proportional to the vertical synchronization frequency and supply it to the amplitude control circuit. and a vertical synchronization frequency-to-voltage conversion circuit, the vertical synchronization frequency to A vertical sawtooth wave is generated by the amplitude control circuit according to the voltage obtained from the voltage conversion circuit. A vertical sawtooth wave output from the vertical oscillation circuit by varying the amplitude control amount of the voltage. Vertical deflection linearity correction characterized by correcting the linearity of vertical deflection by correcting the voltage. It provides a positive circuit.

[0009]

【Example】

The vertical deflection linearity correction circuit of the present invention will be explained below with reference to the attached drawings. Ru. FIG. 1 is a block diagram showing an embodiment of the vertical deflection linearity correction circuit according to the present invention. FIG. 2 shows the vertical synchronous frequency-voltage conversion circuit (hereinafter referred to as fv-V conversion circuit) 14 in FIG. FIG. 2 is a circuit diagram showing a specific configuration. Figure 3 also shows the vertical deflection linearity correction circuit of the present invention. Figure 4 is a waveform diagram for explaining the vertical deflection linearity correction circuit of the present invention. FIG. In Figure 1, the same parts as in Figure 5 are given the same symbols. However, the explanation of the circuit operation will be omitted.

0010 In Figure 1, the negative vertical sawtooth voltage appearing on the feedback resistor 6 is the electronic volume (amplitude control circuit) 15. Electronic volume 15 is set to control voltage It controls the amplitude of the more negative vertical sawtooth voltage. Here, the control voltage is a voltage proportional to the voltage (fv-V voltage) output from the fv-V conversion circuit 14. be. Therefore, it is output from the electronic volume 15, and the coupling capacitor 13 The negative vertical signal used to correct the vertical deflection linearity is input to the vertical oscillator circuit 1 through Is the amplitude of the sawtooth voltage smaller as the frequency is lower and larger as the frequency is higher? By appropriately adjusting the change in control voltage depending on the frequency, Good vertical deflection linearity can always be obtained regardless of the

[0011] The fV-V conversion circuit 14 in FIG. 1 will be explained using FIG. 2. From the input terminal The supplied vertical synchronizing pulse is a monostable multivibrator in the fv-v conversion circuit 14. data (MM) 16. Monostable multivibrator 16 has vertical synchronization pulse When input, it detects the rising edge and starts operation. The positive phase output Q has a constant A pulse with a pulse period Td is also sent to the inverted output Q bar, which is opposite to the positive phase output Q. Phase pulses appear. The output pulse of the inverted output Q bar is connected to the resistor 18 and the capacitor. 19 to obtain a DC voltage. So actually this DC voltage is this Since this will have a fairly large ripple voltage, the positive phase output Q Ripple compensation is achieved by applying the output pulse through resistor 20 and capacitor 21. I am doing the right thing.

0012 Figures 3 (A) and (B) show the vertical synchronization pulse and the Q-balance of the monostable multivibrator 16. - Waveform diagram showing the output and average voltage, (A) is a waveform diagram showing the output and average voltage. (B) shows the case where the vertical synchronization frequency is high. The DC voltage averaged by the resistor 18 and capacitor 19 described above (average voltage Vave) is shown by a broken line. When the frequency is low (A), the average voltage Vave is high It can be seen that when the frequency is high (B), the average voltage Vave is low. In other words, The higher the direct synchronization frequency is, the lower the value will be, and it will be inversely proportional to the frequency. Also, this The DC voltage is changed by changing the pulse period Td using the variable resistor 17. be able to.

[0013] Furthermore, the DC voltage is determined by the operational amplifier 22 and the voltage determined by the resistors 23 and 24. is inverted and amplified by a gain determined by resistors 25 and 26 with reference to . Therefore, The output voltage of the operational amplifier 22 becomes a DC voltage proportional to the frequency. And its output The slope of the voltage can be changed by changing the resistance value of the variable resistor 26, as shown in FIG. can be adjusted accordingly.

[0014] Also, when performing vertical deflection linearity correction adjustment, first set multiple vertical (synchronous) frequencies. The frequency is set to an intermediate frequency among the frequencies of , and resistor 17 is adjusted to Match the voltage determined by Then, by adjusting the variable resistor 27, fv- The control voltage of the electronic volume 15 is changed by adjusting the V voltage. to this Therefore, the electronic volume 15 outputs a negative vertical sawtooth wave voltage with the optimum amplitude, resulting in a good It is preferable to correct vertical deflection linearity. Additionally, the lowest (or highest) frequency A vertical synchronization pulse is input and the variable resistor 26 is adjusted to correct linearity. to this Therefore, it is possible to obtain good vertical deflection linearity over a wide range of vertical synchronization frequencies. can.

[0015]

[Effect of the idea]

As explained in detail above, the vertical deflection linearity correction circuit of the present invention is constructed as described above. Since the vertical synchronization frequency is changed over a wide range of Good vertical deflection linearity can be obtained at all frequencies even when It has an extremely excellent practical effect of being able to

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a vertical deflection linearity correction circuit of the present invention.

FIG. 2 is a specific circuit diagram of the fV-V conversion circuit 14 in FIG. 1.

FIG. 3 is a waveform diagram for explaining the vertical deflection linearity correction circuit of the present invention.

FIG. 4 is a diagram for explaining the vertical deflection linearity correction circuit of the present invention.

FIG. 5 is a block diagram showing a conventional vertical deflection linearity correction circuit.

FIG. 6 is a diagram for explaining the upper part of the image and the lower part of the image;

FIG. 7 is a circuit diagram for explaining a conventional vertical deflection linearity correction circuit.

FIG. 8 is a waveform diagram for explaining a conventional vertical deflection linearity correction circuit.

FIG. 9 is a diagram for explaining problems in the conventional technology.

[Explanation of symbols]

1 Vertical oscillation circuit 2 Vertical amplifier circuit 3 Vertical output circuit 4 Vertical deflection coil 5,13 Coupling capacitor 6 Feedback resistance 14 Vertical synchronous frequency-voltage conversion circuit 15 Electronic volume (amplitude control circuit)

Claims (1)

[Scope of utility model registration request] 1. A vertical oscillation circuit that is supplied with a vertical synchronization pulse and generates a vertical sawtooth voltage, and a vertical output that generates a vertical deflection current using the vertical sawtooth voltage and supplies the vertical deflection current to a vertical deflection coil. an amplitude control circuit that controls the amplitude of a vertical sawtooth voltage obtained from the vertical deflection current and supplies it to the vertical oscillation circuit; and a voltage proportional to the vertical synchronization frequency to which the vertical synchronization pulse is supplied. a vertical synchronous frequency-to-voltage conversion circuit that generates and supplies the vertical synchronous frequency-to-voltage conversion circuit to the amplitude control circuit; A vertical deflection linearity correction circuit, characterized in that the vertical deflection linearity correction circuit corrects the linearity of vertical deflection by changing an amplitude control amount of the vertical oscillation circuit to correct the vertical sawtooth wave voltage output from the vertical oscillation circuit.