JPH04113579A - Dram driving circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a DRAMF-based system and method.

[Prior Art] In the conventional access method of a DRAM drive circuit, as shown in FIG. When writing data,
First, the row address to be written is placed on the address bus 4, and the /RAS signal on the control line 6 is turned LOW.
By doing this, the row address is latched, and then the column address is placed on the address bus 4, and the /CAS signal on the control line 6 is rubbed LOWI to latch the column address and determine the address.

Next, by putting the write data on the data bus 5 and turning the /WE signal on the control line 6 to LOW, the data on the data bus 5 is written.The number of data at this time is 1 to 4 bits.

The read operation is the same up to the address determination as described above, and then data from the DRAM is transferred to the data bus 5 by setting the 10E signal on the control line 6 to LOW.The system bus 2 side transfers the data to the data bus 5. Can communicate.

In this case, since all the signal lines of the control line 6 are common, data is written to and read from the two DRAMs 1a and 1b at the same time.

[Problems to be Solved by the Invention] However, in the above-mentioned prior art, since all the signal lines of the control line 6 are common, data is transmitted between the two DRAMs.
Since data is written to and read from data a and 1b at the same time, the peak current consumption is twice that of a single DRAM. An increase in the peak current consumption also increases the noise generated at that time, leading to malfunction of the DRAM.

In addition, as the peak of the bypass capacitor that is inserted between the power supplies increases, unless the capacitance increases, it will not be able to absorb the power supply voltage fluctuations, so the space for the bypass capacitor on the circuit board must also be large, and the circuit board is not suitable for small and thin devices. This will interfere with the design.

Additionally, in order to prevent malfunctions due to increased noise from the DRAM, the design of the circuit board becomes expensive and complicated, such as changing from a two-layer board to a four-layer board.

Therefore, the present invention is intended to solve such problems.
By shifting the timing of AM access in the DRAM drive circuit section, the peak current consumption is also shifted for each DRAM, reducing noise from the DRAM, and reducing the space on the circuit board by using a small capacity bypass capacitor. The board design can also be simplified, resulting in a small and inexpensive circuit board.

[Means for Solving the Problems] The DRAM drive circuit of the present invention staggers the access timing when accessing the DRAMs in a system equipped with two or more DRAMs (dynamic random access memories). It is characterized in that the DRAMs do not operate at the same time.

[Example code] FIG. 1 is a block diagram of an embodiment of the present invention.

In the access method of the DRAM drive circuit of the present invention, as shown in FIG. are connected by a signal line converted from

When writing data, first the row address to be written is placed on the address bus 4 on the system bus 2 side, the conversion circuit 7 puts it on the address bus 4 on the DRAM side, and then the control line 6 on the system bus 2 side is loaded. By setting the /RAS signal to LOW, the conversion circuit 7 converts to DRA.
/RAS1 on the Mla side is set to LOW, and after a delay of several nanoseconds, /RAS2 of DRAMlb is set to LOW to latch each row address, and then the column address is placed on the address bus 4 on the system bus 2 side. The conversion circuit 7 puts it on the address bus 4 on the DRAM side. Next, by making the /CAS signal on the control line 6 of the two system buses LOW, the conversion circuit 7 makes /CAS1 on the DRAM la side LOW, and Delay a few nanoseconds D
/CAS2 of RAMlb is set to LOW and each column address is latched to determine the address. Next, write data is placed on the data bus 5 on the system bus 2 side, passed through the conversion circuit 7, and placed on the data bus 5 on the DRAM la, lb side.
By making the E signal LOW, the conversion circuit 7 also makes the /WE signal on the control line 6 on the DRAM side LOW and writes the data on the data bus 5 to the DRAMs 1a and 1b.The number of data at this time is 4BIT. be. On the system bus 2 side, two DRAMs 1a and 1b are accessed at the same time, but actually the conversion circuit 7 accesses two times, 1a and 1b.

The read operation is the same up to the address determination as described above, and then the conversion circuit 7 is set to D by setting the 10E signal on the control line 6 of the two system buses to LOW.
By turning 10E of the control line 6 on the RAM side LOW, data from the DRAMs 1a and 1b is transferred to the data bus 5, and data can be exchanged on the system bus 2 side by taking in the data.

FIG. 3 is a timing chart of this embodiment, and writing will be described here.

/RASI used for the DRAMla IC becomes LOW, and the address on the address bus 4 at this time is latched into the DRAMla IC as a row address, tRR.
Used for DRAMIb IC after a delay (several nanoseconds)/RA
S2 becomes LOW and similarly the DRAM is used as a row address.
lb IC. After tRC, /CAS 1 used for the IC of DRAMla goes LOW, and the address on the address bus 4 at this time is latched into the address bus C of DRAMla as a column address.After tCC (several nanoseconds), the address of DRAM1b is latched. /CAS2 used for IC becomes LOW and similarly DRAMlb is used as a column address.
is latched into the IC. Since /WE is LOW, the data on data bus 5 is transferred to DRAM1,
written to lb.

FIG. 4 is a circuit connection diagram of the delay in this embodiment.

Similarly to the system bus 2 side, /RASI, 8 is delayed by the time constants of the inverter 14, resistor 15, and capacitor 16, and is output as /RA S 2.10. /CAS
The same applies to

FIG. 5 is a block diagram showing another embodiment of the present invention.

1a to 1d are DRAMs, and the address bus 4, data bus 5, and control line 6 from the system bus 2 are connected to a conversion circuit 7.
1b are connected to each other by converted signal lines.

When writing data, first the row address to be written is placed on the address bus 4 on the system bus 2 side, the conversion circuit 7 puts it on the address bus 4 on the DRAM Ia to 1d side, and then the control line on the system bus 2 side. By setting the /RAS signal of 6 to LOW, the conversion circuit 7 converts /RASI of 1a and /RAS of 1b on the DRAM side.
1 to LOW, and after a few nanoseconds delay, IC and 1d
/RAS2 is LOW to latch each row address, then the column address is placed on the address bus 4 on the system bus 2 side, the conversion circuit 7 places it on the address bus 4 on the DRAM side, and then the column address is placed on the address bus 4 on the DRAM side. By turning the /CAS signal on the control line 6 on the bus 2 side LOW, the conversion circuit 7 turns /CAS 1 on the DRAM side 1a and 1b LOW, and after a few nanoseconds delay, the /CAS signal on the IC and 1d signal goes LOW.
CAS2 is set to LOW and each column address is latched to determine the address. Next, the write data is placed on the data bus 5 on the system bus 2 side and passed through the conversion circuit 7.
By setting the /WE signal on the control line 6 on the system bus 2 side to LOW on the data bus 5 on the RAM side, the conversion circuit 7 also changes the /WE signal on the control line 6 on the DRAM side.
When the WE signal is set to LOW, the data on data bus 5 is written to the DRAM.The number of data at this time is 4B.
It's IT. However, for system bus 2, 4BITX4
It becomes 16BIT with IC.

On the system bus 2 side, DRAM1a, 1b, and IC
11d, but in reality it is accessed by the conversion circuit 7.
It is divided into two parts: a, lb and lc, ld.

The read operation is the same up to the address determination as described above, and then by setting the 10E signal on the control line 6 on the system bus 2 side to LOW, the conversion circuit 7
By turning 10E of the control line 6 on the RAM side LOW, data is transferred from the ICs from DRAM la to 1d onto the data bus 5, and data can be exchanged on the system bus 2 side by taking in the data.

[Effect of the invention] As described above, according to the invention, in a system equipped with two or more DRAMs (dynamic random access memories), the access timings are shifted when accessing the DRAMs so that each DRAM operates simultaneously. This allows the peak current consumption to be shifted for each DRAM, reduces noise from the DRAM, prevents DRAM malfunctions, reduces circuit board space by using a small bypass capacitor, and simplifies board design. can be made into something,
This has the effect that it can be made into a small and inexpensive circuit board.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a DRAM drive circuit of the present invention. FIG. 2 is a block diagram showing a conventional DRAM drive circuit. FIG. 3 is a timing chart diagram in the embodiment shown in FIG. 1. FIG. 4 is a circuit connection diagram of the delay circuit in the embodiment shown in FIG. 1. FIG. 5 is a block diagram showing another embodiment of the DRAM drive circuit of the present invention. la ~ld-...DRAM 2...System bus 3...System body 4...Address bus 5...Data bus 6...Control line 7...Conversion circuit 8.../RAS 1 9.../CAS 1 10.../RA S 2 11.../CAS2 12.../WE 13...10E 14...Inverter Figure 1 Resistance capacitor or higher

Claims (1)

[Claims] In a system equipped with two or more DRAMs (dynamic random access memories), the access timing is shifted when accessing the DRAMs, and each DR
A DRAM drive circuit characterized in that AM does not operate at the same time.