JPH04111310A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To substantially alleviate a step of a contact opening without increasing a contact resistance by forming a single crystalline film having the same conductivity type as that of a low resistance region and highly doped with impurity on the low resistance region, and forming a wiring material such as metal electrode, etc., thereon. CONSTITUTION:A low resistance region 2 doped with impurity in high concentration is formed on a semiconductor region 1. After an insulating film 3 is deposited thereon, a contact opening 4 is formed by patterning. Then, an amorphous film 5 is deposited. In order to made the partial region of the film 5 polycrystalline or single crystalline, it is annealed. Then, the amorphous film 5 is single crystallized upward from a part in contact with the region 2 to become a seed, a single crystal layer 6 is formed, and the residual most part remains as amorphous silicon. Only the single crystal part remains by using the difference of etching rates due to the difference of the crystallinities. In order to lower the resistance of the formed single crystal part, boron ions B<+> are, for example, implanted. Thus, the step shape of the contact, i.e., the aspect ratio is alleviated, and then a wiring layer 8 represented, for example, by Al, is formed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor substrate circuit device that is widely used as a main electronic component of electronic devices such as computers, and particularly relates to a semiconductor substrate circuit device that is widely used as a main electronic component of electronic devices such as computers. This invention relates to the structure of a contact for electrical conduction and its manufacturing method.

[Summary of the Invention] The present invention provides a method for electrically contacting a low-resistance semiconductor region such as a drain and a source in a semiconductor substrate with a wiring represented by N. After depositing a crystalline film, the amorphous is made into a single crystal, and a single crystal of the same conductivity type as the low resistance semiconductor region is formed, and then a wiring film is formed on the single crystal to reduce the contact resistance. At the same time, we aim to reduce the step shape of the contact opening during the formation of the wiring film, and at the same time, to prevent the wiring material from breaking and to improve the coverage.

[Conventional technology]

FIG. 2(b) is a process-order cross-sectional view showing a method of forming a contact between a low resistance region and a metal electrode in a conventional semiconductor device. For example, the surface portion of the semiconductor region 21 is doped with boron "Bo" by ion implantation to provide a P type low resistance region 22, and after patterning the insulating film 23 to form a contact opening 24, for example, N. Here, the case where the low resistance region 22 is P'' type has been described, but the same applies to the N'' type head region.

[Problem to be solved by the invention]

In the conventional technology, the aspect ratio of the step in the contact hole increases as the area of the contact hole decreases due to integration, resulting in problems such as metal wiring breakage, electromigration and stress migration at the edge of the hole. The impact can no longer be ignored.

[Means to solve the problem]

In the present invention, in order to solve the above-mentioned problems, a high concentration impurity of the same conductivity type as the low resistance region is doped onto the low resistance regions such as the P'' region and the N'' region formed by ion implantation on the substrate. The structure and manufacturing method are such that a single crystal film is formed, and wiring materials such as metal electrodes are formed on it.

[Effect]

By providing a highly doped single crystal layer of the same conductivity type as the substrate low resistance region between the low resistance region in the substrate and the metal electrode, the contact opening can be substantially reduced without increasing the contact resistance. Level differences can be alleviated.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to FIGS. 1, 3, and 4.

FIG. 1 (al to +fl are sectional views in the order of manufacturing steps showing a method of forming a contact according to an embodiment of the present invention.

The semiconductor region 1 refers to a silicon semiconductor substrate or a well region provided within the silicon semiconductor substrate. In FIG. 1 (al), a low resistance region 2 doped with impurities at a high concentration is provided on the surface side of a semiconductor region 1, and after depositing an insulating film 3 thereon, a contact opening 4 is formed by patterning. Figure 1 (in the case of Al, the low resistance region 2 is a P'' region heavily doped with P'' boron as an impurity). An amorphous film 5 is deposited in FIG.
E and the like are used alone or in a mixed state with hydrogen H2. In addition, the equipment is low pressure vapor phase epitaxy (LPCVD:
Low Pressure Chemical
The deposition temperature of the amorphous silicon film is preferably 500° C. or lower, and by removing the natural oxide film on the semiconductor surface of the contact opening 4 before the deposition, it is possible to It is also possible to obtain a single crystal growth layer in the solid phase growth process. In FIG. 1(C), in order to polycrystallize or monocrystallize at least a part of the amorphous film 5 close to the low resistance region 2, the temperature is higher than the substrate temperature at least when the amorphous film 5 is deposited. Annealing is performed at In this example, this process will be hereinafter referred to as a solid phase growth process. In this solid phase growth process, the amorphous silicon film 5
If there is no natural oxide film left on the semiconductor surface of the contact opening 4 immediately before depositing the amorphous film, for example, by depositing an amorphous film at 300°C and then annealing at 500°C, a low The amorphous silicon film 5 is monocrystalized upward from the portion in contact with the resistance region 2 to form a monocrystalline layer 6, and most of the rest remains amorphous silicon, with some polycrystalline film on the top of the monocrystalline layer 6. There is a transition region 7 made of silicon. In this way, the deposited film 6, which is partially single-crystalized and embedded in the contact opening 4, is etched using the difference in etching rate based on the difference in crystallinity between amorphous silicon and single-crystal silicon. Only the single crystallized portion can be left as shown at +dl. In this case, the etching method is wet etching, for example,
A mixture of hydrofluoric acid, nitric acid, ammonium fluoride, and water is
In the case of dry etching, for example, SF, C
Cj! Reactive ion etching using gases such as , etc. is effective. The single crystal part formed in Fig. 1 (fdl) has a high resistance due to its low impurity concentration.
We are performing ion implantation. At this time, annealing is necessary to activate the implanted impurities, but this is omitted in FIG. After the step shape of the contact portion, that is, the aspect ratio is thus relaxed, the wiring layer 8, which is typically made of N or the like, is formed, thereby making it possible to prevent the wiring from breaking and abnormally increasing the contact resistance.

In this example, in order to lower the resistance of the single crystal part, impurity ions are implanted after forming the single crystal part. By depositing 5, Figure 1 (
It is also possible to omit the ion implantation step shown in el. Fig. 4 ta+~(fl shows another embodiment according to the present invention. Fig. 4 al~ (C1 shows Fig. 1 (
The steps are the same as a) to (cl), and the explanation is omitted here.In contrast to the above-mentioned embodiment, the impurity doping method for the single crystal layer 6 obtained by solid phase growth was ion implantation. The present embodiment is characterized by the use of a method based on the adsorption of impurity elements onto the surface of a single crystal.
Prior to the explanation of FIGS.

FIG. 3 shows a block diagram of an apparatus used for impurity doping in the second embodiment shown in FIGS. 4 (al to ffl). In FIG. The temperature of the board 31 is controlled by a heating system 33 using an infrared lamp heating method or a resistance heating method.
It is maintained at a predetermined temperature. The inside of the chamber 32 is highly evacuated using a high vacuum evacuation system 4 composed of a plurality of pumps with a turbo molecular pump as the main evacuation pump. The degree of vacuum inside the chamber 32 is monitored using a pressure gauge 35. The transportation of the silicon substrate 31 is as follows:
The transfer is performed between the load chamber 37 and the chamber 32, which are connected to the chamber 32 via the gate valve 36a, using the transfer mechanism 38 with the gate valve 36a open. Note that the load chamber 37 is normally evacuated to a high vacuum by the load chamber exhaust system 39 with the gate valve 36b open, except when the silicon substrate 31 is taken in and out of the load chamber 37 and when it is transported. The amount of gas introduced into the chamber 32 from the gas supply source 61, the introduction mode, etc.
It is controlled using a gas introduction control system 30.

In FIG. 4(di), the surface of the solid-phase growth phase 47 formed on the silicon substrate 41 is cleaned. That is, the silicon substrate 41 has a background pressure of 1×10-'
At a substrate temperature of, for example, 850° C., hydrogen gas is introduced into the center of a vacuum chamber at a temperature of Pa or less for a certain period of time under conditions such that the pressure inside the chamber is, for example, 1.3×10−” Pa. The natural oxide film formed on the surface of the solid phase growth phase 46 is removed, and the chemically active silicon surface is exposed. This is the step of forming the adsorption layer 48 (Fig. 4 1c).
After the cleaning of the surface is completed in the step of , the introduction of hydrogen gas is stopped, and the substrate temperature is set to, for example, 825°C. After reaching the set temperature and stabilizing, boron is added to the surface of the silicon substrate 1 in the step shown in FIG. Diborane, a compound gas containing
For example, if the chamber pressure is 1.3X10-"
The adsorption layer 48 of boron or a compound containing boron is formed by introducing it for a certain period of time under conditions such that Pa. However, strictly speaking, in the process shown in Figure 4, at the same time as the formation of an adsorption layer of boron or an adsorption layer of a compound containing boron, boron is added to the bulk at a constant rate determined by the substrate temperature and diborane introduction pressure when diborane is introduced. Diffusion into the interior is also progressing, but this is also included in Figure 4 (el.
The process corresponding to is simply called the process of forming an impurity adsorption layer. Thereafter, by performing annealing as necessary, a P layer having a desired resistance value is provided on the low resistance region 42.

After the step shape of the contact portion, that is, the aspect ratio is relaxed in this way, the wiring layer 4 typified by N, etc.
By forming 9, it is possible to obtain the same effect as in the first embodiment shown above.

〔Effect of the invention〕

As described above, by using the present invention, in the case where the aspect ratio is large, the aspect ratio can be effectively reduced in the contact portion where the wiring in the semiconductor low resistance region is electrically connected, that is, the step shape can be significantly reduced. This is effective in preventing wire breakage and contact resistance increases near the edges of the insulating film. Further, by reducing the step difference in the contact portion, there is also the effect that it becomes easier to planarize the interlayer insulating film in a multilayer wiring structure of two or more layers.

[Brief explanation of drawings]

FIG. 1 (al to (fl) are cross-sectional views in the order of manufacturing steps of a semiconductor device according to the first embodiment of the present invention, and FIG. 2 (fat (b)
1 is a step-by-step sectional view showing a method of forming a contact in a conventional semiconductor device, FIG. 3 is a block diagram of an apparatus used for forming an impurity adsorption layer in a second embodiment of the present invention, and FIG. (f) is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention in the order of manufacturing steps.Semiconductor region Low resistance region Insulating film Contact Flowering portion Amorphous deposited film Anticrystalline layer Transition region Wiring layer

Claims (2)

[Claims] (1) A single-crystal region of the same conductivity type as the low-resistance region is provided on a low-resistance region doped with impurities at a high concentration, and a deposited film serving as a wiring is connected to the low-resistance region via the single-crystal thin film. A semiconductor device whose structural feature is that it is an electrical contact. (2) A first step of forming a single crystal film of the same conductivity type as the low resistance region on a low resistance semiconductor region, and a second step of forming a deposited film that will become a wiring on the single crystal film. Become,
A method for manufacturing a semiconductor device, wherein the first step comprises depositing an amorphous film and then converting the amorphous film into a single crystal by a solid phase growth method.