JPH04107950A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an electrically excellent semiconductor device by reducing a level difference from a substrate surface to the upper part of a layer insulation film through forming a conductive layer to be formed on a level difference pattern sufficiently inward of an element separation region from the boundary between element region and element separation region in a part where the element region and element separation region are in contact with each other. CONSTITUTION:An element-forming region 7 and an element separation region 5 for separating the element-forming region are provided on a semiconductor substrate 1. A conductive layer 3 is formed on the element separation region 5 via an insulating layer 4 and the conductive layer 3 is formed in a part avoiding a level difference part to be formed on the element-forming region side on the insulating layer 4. An insulating layer 20 covering the conductive layer 3 has its end on the element-forming region side in a part ranging from the boundary part between the level difference part of the insulating layer 4 and the substrate 1 to the element separation region side. Thus, the level difference is reduced so that an excellent conductive layer is formed and a highly reliable semiconductor device can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, and in particular, to reducing the level difference in a conductive layer to be formed.

[Conventional technology]

2. Description of the Related Art In recent years, semiconductor devices have rapidly become more highly integrated and miniaturized, and as a result, the steps of formed patterns tend to become larger and larger. Although this step part did not pose a problem in the past, it has become a major problem as the integration becomes higher and smaller.
In the figure, (1) is a semiconductor substrate (hereinafter referred to as the substrate) made of single crystal silicon, and (2) is a semiconductor substrate made of single crystal silicon (hereinafter referred to as the substrate). A field oxide film (3) formed on the substrate (1) to be used for device isolation; (3) a first conductive layer formed on the field oxide film (2) and wired on the device isolation region; ) Hato no tI
Covering the conductive layer (3) of Xl, the second layer to be formed later
This is an interlayer insulating film that electrically insulates the conductive layer (3) and the first conductive layer (3). (5) is the designed element isolation region, (6
) is a bird's beak formed at the end of the field oxide film (2), (7) is a region where an element is to be formed (hereinafter referred to as the element region), and (8) is a region where the first conductive layer (3) is formed. This is the residue produced during formation. Further, h is the step difference from the surface of the substrate (1) to one part of the interlayer insulating film (4), and θ is the angle formed between the surface of the substrate (1) and the interlayer insulating film (4).

By the way, as LSI devices become more highly integrated, the elements that make up the devices are becoming smaller.In the case of MOS transistors, as the channel width becomes narrower, the threshold voltage increases. This causes so-called narrow channel effects such as widening of the effective thionel width due to gate pressure, resulting in deterioration of device characteristics. This narrow channel effect depends on various factors such as substrate impurity concentration and substrate bias, but it also depends greatly on the field oxide film thickness and bird's beak length, and as shown in Figure 9, the bird's beak (6) LOC that suppressed the occurrence of
An O8 separation method is being considered.

On the other hand, as a measure against the narrow channel effect, Locos
A field shield element isolation method is being considered as an element isolation method to replace the isolation method.

FIG. 10 is a cross-sectional view showing a memory cell portion of a conventional semiconductor device using the field shield element isolation method.

In the figure, (1), (3) to (5), (7)
, (g), h, and θ are equivalent to those in FIG. (9) is an isolated conductive layer, and 00 is an interlayer insulating film region in the side portion of this isolated conductive layer (9).

In this device, separation is performed by applying a predetermined voltage to a separation conductive film (9).

[Problem to be solved by the invention]

Conventional semiconductor devices are configured as described above, and as one measure against the narrow channel effect, suppressing the bird's beak (6) as shown in FIG. In the first conductive layer (3) formed at the boundary, the angle θ is close to 90 degrees, and the step becomes high.Generally, the closer the angle θ is to 9 degrees, the higher the step. In addition, the higher the step height, the more difficult it becomes to process the anisotropic etching to be performed in the subsequent process. A part of the conductive layer 2 remains as a residue (8), causing a short circuit between formed elements, for example, between conductive layers on the same surface, or between conductive layers between lower layers.

In addition, as another measure against narrow channel burns, in the field shield element separation method as shown in Figure 10, bird's beak (6) is unlikely to occur, and the angle θ is somewhat relaxed from 90 degrees. However, the level difference cannot be eliminated only by the lateral protrusion α1 of the interlayer insulating film (4), and the level difference becomes high enough to cause residue (8) on the side part of the interlayer insulating film region α0 on the surface of the substrate (1). This causes the problem of short-circuit failure similar to that described above.

This invention was made to solve the above-mentioned problems, and a good conductive layer is formed by reducing the step difference.
The purpose is to obtain a highly reliable semiconductor device.

[Means to solve the problem]

In the semiconductor device according to the present invention, an element formation region and an element isolation region separating the element formation region and the element isolation region are provided on a semiconductor substrate, a conductive layer is formed on the element isolation region via a first insulating layer, and a conductive layer is formed on the element isolation region via a first insulating layer. The conductive layer is formed in a portion that avoids a step between the first insulating layer and the element formation region, and the second insulating layer covering the conductive layer is formed of the first insulating layer. The insulating layer has a structure in which the stepped portion of the insulating layer is coated with its end portion on the element forming region side closer to the first element isolation region than the boundary with the substrate.

[Effect]

In this invention, the conductive layer formed on the step pattern is formed in the portion where the element region and the element isolation region are in contact with each other.
Since the boundary between the element region and the element isolation region is formed sufficiently on the element isolation region, the step from the substrate surface to the upper part of the interlayer insulating film is reduced, and the angle between the substrate surface and the side wall of the layer isolation film is reduced. You can make it big.

It is an object of the present invention to obtain a semiconductor device that is electrically good without producing any residue during etching processing in a post-process.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. m1
The figure is a sectional view showing the structure of a memory cell portion of a semiconductor device using field shield isolation according to an embodiment of the present invention.

In the figure, (1), (3), (4), (
9) and 00 are equivalent to the conventional ones. 0 is the area from the end surface of the separation conductive layer (9) to the end surface of the first conductive layer (3), and is its length, and %hl is the area between the interlayer insulating film (4) of the first conductive layer (3). ) from the upper surface of the interlayer insulating film (4) on the separation conductive layer (9);
h2 is the level difference from the surface of the glabella insulating film (4) to the surface of the substrate (1). In addition, θl is the first conductive layer (3)
The angle that the glabella insulating film (4) makes with the plane of the substrate (1),
θ2 is when the interlayer insulating film (4) of the separated conductive layer (9) is
) is the angle made with respect to the plane.

FIG. 2 is a cross-sectional view showing the manufacturing process of the memory cell part of the semiconductor device shown in FIG.
Form η to the thickness of about 500 deer. Subsequently, a doped polysilicon film (9a) that will become the isolation conductive layer (9) is formed on top of it by CVD or the like to a thickness of about 2,000 to 3,000 layers, and then First interlayer insulation using high temperature CVD method! (4) The first silicon oxide film (
4a) is formed to a thickness of about 2,000 to 3,000 people. After this, for example, a positive type resist is formed to a predetermined thickness, and patterning is performed using photolithography technology to form a resist pattern (6) (see FIG. 2(a)).
).

Next, using the resist pattern @ as a mask, the first silicon oxide film (4a), which will become the first interlayer insulating film (4), and the doped polysilicon film (9a), which will become the isolation conductive layer (9), are sequentially anisotropically formed. The etching is selectively removed by reactive ion etching (hereinafter referred to as RTE) or the like. As a result, a patterned first silicon oxide film (4a) and doped polysilicon film (9a) are obtained. After this, resist pattern 4 is removed by ashing method etc. (second
Figure (b)).

Next, the patterned silicon oxide film of tlfJl (
4a) High-temperature C is applied to the entire surface of the substrate (1) soil so as to cover it.
The second silicon oxide film (4b), which will become the first interlayer insulating film (4), is heated at 2,000-3,000 A by VD method or the like.
Form the film to a thickness of approximately This film (4b) is the first silicon oxide film patterned above! It is made of the same material as (4a), and is integrated here to form the first interlayer insulating film (4a).
) (Figure 2 (C)).

Next, anisotropic RIE is performed to form the first silicon oxide film (
4a), a second silicon oxide film (ab) and a field gate oxide film 01 are formed so that each main surface of the substrate (1) is exposed.
) is removed by etching.

Here, the first silicon oxide film (4a), the isolation conductive layer (
A portion of the second silicon oxide film (4b) remains on the step-side side wall of the pattern 9). Note that this remaining second silicon oxide film (4b) becomes a *l eyebrow-cut 1# film (4) that is integrated with the first silicon oxide film (4a) and the field gate oxide film αη. The isolation conductive layer (9) is now covered by the interlayer insulating film (4) of @1 (FIG. 2(d)).

Next, after the substrate (1) has been subjected to a predetermined process, a gate oxide film made of a silicon oxide film is formed on the substrate (1) using a thermal oxidation method or the like to a thickness of approximately 150 mm. Figure (e)).

Next, a doped polysilicon film (3a), which will become the first JW layer (3), is deposited on the entire surface of the first interlayer insulating film (4) and the gate oxide film (3) to a thickness of 2,000 μm by CVD or the like. ~3,0
After forming a film with a thickness of about 00 A, high-temperature CV is applied to that b.
A silicon oxide film (20a), which will become the second glabellar insulating film, is formed to a thickness of about 3,000 to 4,000 times using the D method or the like. After this, the third layer becomes the second interlayer insulating film (e).
For example, a positive type resist is formed on the silicon oxide film (20a), and this is patterned by photolithography to form a resist pattern α thick (FIG. 2(f)).

Next, using the resist pattern Q4 as a mask, the third silicon oxide film (20a) and the doped polysilicon film (3a) are selectively etched away in sequence by anisotropic RIE or the like. This patterned WX3 silicon oxide film (20a) and doped polysilicon film (3a).
After that, the resist pattern 04 is removed by an ashing method or the like (FIG. 2@).

Next, a patterned third silicon oxide film (20a
) to coat the entire surface of the substrate (1).
#I4 becomes the second interlayer insulating film (e) by VD method etc.
Silicon oxide 111 (20a) of 3,000 to 4,0
It is formed to a thickness of about 0.000. This film (20b) is made of the same material as the third patterned silicon oxide 1K (20a), and is integrated to form the second glabellar insulating film (1) (see Fig. 2 (h). )).

Next, anisotropic IE is applied to the first glabella insulating film (4) and a portion of the substrate (1) so that the respective surfaces are calculated, and the fourth silicon oxide film (20b) is etched away. do. At this time, a portion of the fourth silicon oxide film (20b) remains on the step sidewall of the pattern of the third silicon oxide film (20a) and the first conductive layer (3).

Note that this remaining fourth silicon oxide film (20b) is integrated with the third silicon oxide film (20a) and the already formed first glabella insulating film (4) (Fig. 2). (1)).

In this way, the semiconductor device shown in FIG. 1 is obtained.

Also, Figure 3 is a plan view of a portion corresponding to Figure 1.
Figures 4 (a) and (b) are respectively ■a - of Figure 3.
■A line s A cross-sectional view taken along the Pub-Pub line. Here, in the region at the right end of the element region (7) in the figure, the left end surface of the first conductive layer (3) is shifted from the right end of the separation conductive layer (9) to the right in the figure by about 2,000 people. By arranging the
The angle θ formed between the substrate (1) and the glabella insulating film (4) is also divided into angle θ1 and angle θ2, which can prevent high steps and verticalization of the corners, and reduce the amount of residue (8). Incidentally, in the above embodiment, the first conductive layer (3) is movable in the region facing the element region (7), but the first conductive layer (3) disposed linearly is 3) may be formed to be partially narrower than the rest. That is, FIG. 5 is a plan view showing another embodiment in such a case, and FIG. 6(a)
, (10 is the line ■a - ■a and ■b in Figure 5, respectively)
It is a sectional view taken along the -vIb line. This thing.

The width of the lX1 conductive layer (3) at the right end of the element region (7) in the figure is narrow, but the width is wider in the other parts. Here, s”1 is a wide forming width, W2
is the narrow formation width and ω is the difference between their widths. Width ω
If the width ωFi becomes too large, the electrical resistance of the conductive layer (3) of tsl will increase and the characteristics of the device will deteriorate.
It is desirable that the wide width Wl of the conductive layer (3) is up to about lX3. Similar effects can be obtained by using both the case where the end face portion of the first conductive layer (3) is shifted and the case where the narrow width W2 is formed in the first conductive layer (3).

In the embodiments h and h above, semiconductor devices using field shield isolation have been described, but semiconductor devices using LOCO8 isolation may also be used.

Figures 7 and 8 are LOG! This is the case of a semiconductor device using O8 separation.

FIG. 7 shows a structural cross-sectional view of the first conductive layer (3) moved to the element isolation region (5) by a predetermined length (T),
This is an example corresponding to Fig. 3 in plan view except for the separation part,
FIG. 8 shows a cross-sectional view of a structure in which a narrow width W2 is formed in a predetermined portion of the first conductive layer (3), and is an example corresponding to FIG. 5 in plan view except for the separation portion.

In this case as well, similar to the case with the field shield isolation structure, steps are suppressed, a good conductive layer is formed, and a highly reliable semiconductor device can be obtained.

In the above embodiments, the case where the substrate (1) is of P conductivity type has been described, but it goes without saying that it may be of N conductivity type and a conductive layer may be formed thereon.

〔Effect of the invention〕

As described above, according to the present invention, the step and the angle between the substrate plane and the sidewall are sufficiently relaxed on the portion where the conductive layer formed on the element isolation region contacts the element isolation region. , no residue is generated on the sidewalls of the conductive layer,
This has the effect of providing a good semiconductor device.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the structure of a memory cell portion of a semiconductor device using field shield isolation according to an embodiment of the present invention, and FIGS. 2(a) to (1) show the manufacturing process of the device shown in FIG. The sectional view shown in FIG. 83 is a plan view of a portion corresponding to FIG. 1, and FIGS. 4(a) and 4(Iy) are sectional views taken along the line ■a-■a and the line ■b-yb in FIG. 3, respectively. FIG. 5 shows another embodiment of the invention, in which the conductive layer is
A plan view with a planar shape different from that shown in the figure,
Figure 6 (!L) and (b) are the Vla of Figure 5, respectively.
-M- line, lb-■b line sectional views, FIGS. 7 and 8 are Locos showing still other embodiments of the present invention.
A cross-sectional view of a semiconductor device using isolation, Figure 9 is LOC! O
FIG. 10 is a cross-sectional view of a conventional semiconductor device using field shield separation. In the figure, (1) is a semiconductor substrate, (2) is a field oxide film, (3) is a first conductive layer, (4) is a first interlayer insulating film, (5) is an element isolation region, and (7) is a first conductive layer. is the element region, (9
) is a separation conductive layer, and gradient is a second interlayer insulating film. Note that the same reference numerals in each figure indicate the same or equivalent parts.

Claims (1)

[Claims] A semiconductor substrate is provided with an element formation region and an element isolation region that separates the element formation region, and a conductive layer is formed on the element isolation region with a first insulating layer interposed therebetween. The second insulating layer is formed in a portion of the first insulating layer that avoids a step portion to be formed on the side of the element formation region, and the second insulating layer covering the conductive layer is formed on the first insulating layer. A semiconductor device having a structure in which an end portion thereof on the element forming region side is covered with a boundary portion with the substrate on the element isolation region side.