JPH04107920A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to the formation of connection holes in multilayer wiring integrated circuits, and is concerned with the problem that when chamfering the shoulders of the connection holes by argon sputter etching, spatter droplets adhere to the inner surfaces of the connection holes. Aiming at solving the remaining problem, the process of chamfering the connection hole shoulder included in the present invention includes the steps of: opening a connection hole in the first insulating layer deposited on the first wiring layer; A step of coating the surface of the first insulating layer, including the inner surface of the hole, with a second insulating layer having chemical properties different from that of the first insulating layer, and applying argon sputter etching to the opening edge of the connection hole. A step of etching the second insulating layer and the first insulating layer thereunder in an oblique direction. After performing the above step, etching the second insulating layer by an etching method having a higher etching rate than that of the first insulating layer. The formation of the second wiring layer included in the present invention consists of depositing a metal wiring layer on the semiconductor substrate subjected to the above treatment and patterning it. do.

[Industrial application field]

The present invention relates to the formation of multilayer wiring for integrated circuits (ICs), and particularly relates to the opening treatment of interlayer connection holes.

With the increasing integration of ICs and the miniaturization of patterns, interlayer connection holes and contact holes in multilayer interconnections have become finer, with a diameter of 1 μm or less. Generally, when a conductive layer is deposited on the surface of a substrate having a steep step, the shoulder portion of the step tends to become discontinuous. As a result, if this is patterned to form an upper layer wiring, a break will occur at the shoulder of the connection hole. As mentioned above, when the diameter becomes about 0.8 to 1 μm,
This problem of discontinuity is made even more serious because it is also difficult to deposit conductor layers within the holes.

The usual method for solving the problem of the step breakage is to chamfer the shoulder portion of the step and cover this slope with a conductive material or the like. In the case of a connection hole, this slope increases the diameter of the opening and makes the vertical cross-sectional shape of the hole Y-shaped. In this specification, the process of making the shoulder of the connection hole slope is called chamfering.

The classical method for forming chamfered connection holes is to first create an open recess at the top by isotropic etching, and then create a vertical through hole in the center of this recess by anisotropic etching. . In this two-step process, since mask alignment is performed in each of the two etchings, it is difficult to improve the processing accuracy and is not suitable for processing fine patterns.

Forming connection holes in highly integrated ICs requires a processing method that chamfers the through holes in a self-aligning manner.

C Problems to be Solved by the Prior Art and the Invention 3 By selectively etching an insulating material layer such as SrOz or PSG by anisotropic etching represented by reactive ion etching (RIE), can drill through holes with vertical sides. The cross-sectional shape of the upper end of this opening, that is, the shoulder part, has an edge that is perpendicular to . That is, the opening can be chamfered.

Argon is often used as the inert gas.

FIG. 2 is a schematic cross-sectional view showing the process of this prior art.
Here, the conventional process of the chamfering process will be described with reference to the drawings.

First, as shown in FIG. 1(a), the surface of the substrate 1 is coated with a
coated with an insulating material layer 2 of G, lithography and RIE
This opens the connection hole 3. The substrate region under this contact hole is a lower layer wiring or an element region of a semiconductor substrate, and the shoulder portion of the contact hole has an edge shape due to the anisotropy of RIE.

When this is subjected to argon sputter etching, the edges are preferentially etched, as shown in Figure (b).
A slope 5 is formed at the shoulder portion of the connection hole.

That is, chamfering is performed. Although this process provides the desired cross-sectional shape of the connection hole, the etched workpiece may scatter during the sputtering process and adhere to the bottom or side surfaces of the connection hole. If the upper layer wiring is formed in the presence of deposits 6 such as sputter droplets, the connection resistance with the lower layer wiring will increase, and in extreme cases, a connection failure will occur.

An object of the present invention is to provide a processing method that prevents sputter droplets from adhering to the bottom of the hole even when chamfering the interlayer connection hole by argon sputter etching.
Thereby, it is an object of the present invention to provide a high-performance IC in which the connection resistance of interlayer connections and contact connections does not become unnecessarily high.

[Means to solve the problem]

In order to achieve the above object, the process of chamfering the connection hole shoulder included in the present invention includes: a process of opening a connection hole in the first insulating layer deposited on the first wiring layer; and a process of chamfering the inner surface of the connection hole. A step of coating the surface of the first insulating layer containing a second insulating layer having a chemical property different from that of the first insulating layer, performing argon sputter etching to remove the second insulating layer at the opening of the connection hole. etching the layer in an oblique direction, and further etching the first insulating layer exposed by the etching in an oblique direction; after performing the above steps, etching the first insulating layer at a higher etching rate; Further, the formation of the second wiring layer included in the present invention includes depositing a metal wiring layer on the semiconductor substrate subjected to the above treatment, This is done by patterning.

[For production]

For example, argon sputter etching can be performed on PSG and Si.
For dissimilar materials such as Nx, it is possible to set the processing conditions so that the etching rate is the same. Therefore, after opening a connection hole in the PSG layer using RIH,
If the surface is coated with a +Nx film and subjected to argon sputter etching, the SiNx film is etched diagonally at the shoulder portion of the contact hole, and then the exposed PSG layer is also etched diagonally.

The change in shape of the PSG layer due to this treatment is the same as in the prior art described above, but since the side and bottom surfaces of the connection hole are covered with the SiNx film, sputter droplets will adhere to the coating film. Therefore, if the SiNx film is removed after performing the necessary chamfering on the PSG layer, the deposits will also be removed at the same time, and no foreign matter will remain attached to the inner surface of the connection hole.

By selecting a material with chemical properties different from those of the interlayer insulation material as the coating film as described above, upon its removal,
Processing that does not involve etching the interlayer insulating layer or even the lower layer wiring becomes possible, and it is possible to avoid widening of connection holes and thinning of the lower layer wiring.

〔Example〕

FIG. 1 is a cross-sectional view schematically showing the processing steps of the present invention. Hereinafter, the processing performed in the fourth embodiment will be explained with reference to the drawings.

First, as shown in the same figure (al), the surface of the substrate 1 is coated with, for example, PS
Covered with a layer of disconnected material 2 of G, lithography and RIE
This opens the connection hole 3. The substrate region under this contact hole is a lower layer wiring or an element region of a semiconductor substrate, and the shoulder portion of the contact hole has an edge shape due to the anisotropy of RIE. This process is based on conventional technology, the thickness of the PSG layer is 0.6 μm, and the RIE process conditions are etching and etching.
The gas is Ar and the pressure is 0. I Torr, high frequency electric cuff 0
At 0W, a connection hole of 1.0 μmφ is opened.

Next, as shown in the same figure (b), the entire surface of the substrate was coated with a thickness of 0.1 μm.
It is coated with a SiNx film 4 of. If the SiNx film is formed using a treatment method that provides good coverage, such as low-pressure CVD, the side and bottom surfaces of the connection hole will be coated with a very uniform thickness.

After the above processing, if argon sputter etching is applied to this, the SiNx film will first be etched obliquely at the shoulder part of the contact hole, as shown in figure fc), and the exposed PSG layer will also be etched. Etched diagonally. At this time, deposits 6 such as sputter droplets are removed from SiN.
x adheres on the membrane.

Subsequently, by etching the substrate with hot phosphoric acid to remove the SiNx film, a state in which the connection hole has been chamfered as shown in the same figure (di) is obtained.

〔Effect of the invention〕

As explained above, according to the treatment method of the present invention, foreign matter adhering to the inner surface of the connection hole is removed together with the coating film, so that a clean connection surface is obtained and the connection hole is not narrowed. Therefore, the connection hole can be chamfered while avoiding high resistance in interlayer connections and contact connections.

Furthermore, since the chamfering of the present invention is performed in a self-aligned manner, no positioning machine is required, and it is possible to improve
0 suitable for forming

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional diagram showing the process of the embodiment of the present invention, FIG. 2 is a schematic cross-sectional diagram showing the chamfering process of the prior art, and FIG. 3 is a diagram showing the problems of the prior art. , 2 is a PSG layer, 3 is a connection hole, 4 is a SiNx film, 5 is an inclined surface, and 6 is a deposit. Fig. 1 is a schematic cross-sectional diagram showing the steps of the embodiment of the present invention.

Claims (1)

[Claims] A step of opening a contact hole in a first insulating layer deposited on a first wiring layer; a step of coating a second insulating layer having different chemical properties, performing sputter etching using an inert gas to coat the second insulating layer at the opening of the connection hole so that the edge of the opening of the connection hole has an inclined surface; and the first insulating layer, after performing the above step, etching the second insulating layer using an etching method that has a higher etching rate for the second insulating layer than for the first insulating layer. and a step of depositing a metal wiring layer on the semiconductor substrate subjected to the above treatment and patterning it to form a second wiring layer connected to the first conductive layer. A method for manufacturing a featured semiconductor device.