JPH04107876A - Semiconductor device and ignitor using it - Google Patents
Semiconductor device and ignitor using itInfo
- Publication number
- JPH04107876A JPH04107876A JP22579690A JP22579690A JPH04107876A JP H04107876 A JPH04107876 A JP H04107876A JP 22579690 A JP22579690 A JP 22579690A JP 22579690 A JP22579690 A JP 22579690A JP H04107876 A JPH04107876 A JP H04107876A
- Authority
- JP
- Japan
- Prior art keywords
- region
- drain
- conductivity type
- area
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 230000015556 catabolic process Effects 0.000 claims abstract description 14
- 230000006378 damage Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Protection Of Static Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はイグナイタ用のパワー素子として使用すること
ができる半導体装置とそれを用いたイグナイタ装置に関
する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device that can be used as a power element for an igniter, and an igniter device using the same.
従来の技術
従来、MOSFETをスイッチング素子としてイグナイ
タに用いる場合、スイッチング部は第2図に示したよう
にMOSFET13のドレイン−ソース間にサージ保護
用ダイオード14を設けることが必要である。なお第2
回中、12にはトランス、15は発光点である。2. Description of the Related Art Conventionally, when a MOSFET is used as a switching element in an igniter, it is necessary to provide a surge protection diode 14 between the drain and source of the MOSFET 13 in the switching section as shown in FIG. Furthermore, the second
During rotation, 12 is a transformer, and 15 is a light emitting point.
発明が解決しようとする課題
このサージ保護用ダイオードが必要な理由について以下
説明する。第3図は第2図のMOSFET13を動作1
6.17.停止18.19したときのドレイン電圧を示
している。第3図aが外付ダイオード14有り、第3図
すが無の場合である。Problems to be Solved by the Invention The reason why this surge protection diode is necessary will be explained below. Figure 3 shows MOSFET 13 in Figure 2 operating 1.
6.17. It shows the drain voltage when stopped at 18 and 19. 3A shows the case with the external diode 14, and FIG. 3A shows the case without the external diode 14.
−点#l[#22.26がMOSFET13のドレイン
−ソース間降伏電圧である。負荷がインダクタンス負荷
のため、MOSFETが停止した瞬間、正電圧のサージ
20.21が発生する。外付のサージ保護ダイオード1
4が無い場合はサージ電圧がMOSFET13のドレイ
ン−ソース間降伏電圧より高くなるためMOSFET1
3はドレイン−ソース間で降伏し第4図に示すようにド
レインコンタクト領域28からソース31に降伏電流が
流れると、半導体基板35の抵抗成分34による電圧差
が生じ、寄生バイポーラトランジスタ33が動作し温度
上昇を引き起こし、熱破壊にいたる。そこでMOSFE
T13の降伏電圧よりも低い降伏電圧のダイオード14
をMOSFETのドレイン−ソース間に挿入する必要が
ある。なお第4図中、24はドレイン電極、25はソー
ス電極、30は延長ドレイン領域、29は第一導電型領
域、26は酸化シリコン膜、27はゲート電極、32は
基板コンタクト領域である。- Point #l [#22.26 is the drain-source breakdown voltage of MOSFET 13. Since the load is an inductance load, a positive voltage surge 20.21 occurs the moment the MOSFET stops. External surge protection diode 1
4, the surge voltage will be higher than the drain-source breakdown voltage of MOSFET13, so MOSFET1
3 breaks down between the drain and source, and as shown in FIG. 4, when a breakdown current flows from the drain contact region 28 to the source 31, a voltage difference occurs due to the resistance component 34 of the semiconductor substrate 35, and the parasitic bipolar transistor 33 operates. This causes a temperature rise, leading to thermal damage. Therefore, MOSFE
Diode 14 with a breakdown voltage lower than that of T13
must be inserted between the drain and source of the MOSFET. In FIG. 4, 24 is a drain electrode, 25 is a source electrode, 30 is an extended drain region, 29 is a first conductivity type region, 26 is a silicon oxide film, 27 is a gate electrode, and 32 is a substrate contact region.
このように従来の構造では、MOSFETのドレイン−
ソース間にサージ保護用ダイオードを設けなければなら
なかった。In this way, in the conventional structure, the drain of MOSFET
A surge protection diode had to be installed between the sources.
課題を解決するための手段
本発明では上記の課題を解決するため下記に示す横型M
OSFET構造をとる。つまり第一導電型半導体基板中
に形成した第二導電型のソース領域とドレインコンタク
ト領域の間にドレインコンタクト領域に接する第二導電
型の延長ドレイン領域を形成し、延長ドレイン領域内の
表面にドレインに対し逆バイアスされた第一導電型領域
を形成し、ドレインコンタクト領域の深さを延長ドレイ
ン領域よりも深くし、延長ドレイン領域とソース領域の
間の第一導電型半導体基板表面をチャネル領域とし、こ
のチャネル領域上にゲート酸化膜を介してゲート電極を
形成し、上記の半導体基板の下に高濃度の第一導電型の
下層高濃度領域を形成し、ドレイン−ソース間に逆電圧
を印加したとき、ドレインコンタクト領域と半導体基板
間で降伏がおこるようにした構造である。Means for Solving the Problems In order to solve the above problems, the present invention uses the horizontal M shown below.
It has an OSFET structure. In other words, an extended drain region of the second conductivity type that is in contact with the drain contact region is formed between the source region of the second conductivity type and the drain contact region formed in the semiconductor substrate of the first conductivity type, and the drain region is formed on the surface of the extended drain region. forming a first conductivity type region that is reverse biased, the depth of the drain contact region is deeper than the extended drain region, and the surface of the first conductivity type semiconductor substrate between the extended drain region and the source region is used as a channel region. , a gate electrode is formed on this channel region via a gate oxide film, a lower high concentration region of the first conductivity type is formed under the semiconductor substrate, and a reverse voltage is applied between the drain and the source. This structure is such that breakdown occurs between the drain contact region and the semiconductor substrate when this happens.
作 用
このような本発明の構造によりMOSFETのドレイン
−ソース間にMOSFETの降伏電圧よりも低い降伏電
圧のダイオードを挿入できMOSFETを降伏による破
壊から保護できる。Function: According to the structure of the present invention, a diode having a breakdown voltage lower than that of the MOSFET can be inserted between the drain and source of the MOSFET, and the MOSFET can be protected from destruction due to breakdown.
実施例
第1図に本発明の一実施例における半導体装置の断面を
示す。第一導電型(たとえばP型)の半導体基板10に
第二導電型(たとえばN型)の延長ドレイン領域6を設
け、そのドレイン領域6内の表面に、このドレイン領域
6に対して逆バイアスされた第一導電型、領域7を形成
する。半導体基板10の下には該基板10よりも高濃度
の第一導電型の下層高濃度領域11が設けられている。Embodiment FIG. 1 shows a cross section of a semiconductor device according to an embodiment of the present invention. A semiconductor substrate 10 of a first conductivity type (for example, P type) is provided with an extended drain region 6 of a second conductivity type (for example, N type), and a surface inside the drain region 6 is reverse biased with respect to this drain region 6. A first conductivity type region 7 is formed. A lower high concentration region 11 of a first conductivity type, which has a higher concentration than the substrate 10, is provided below the semiconductor substrate 10.
ドレイン領域6と基板10に設けた第二導電型のソース
領域8との間に逆電圧がかかったとき、ドレイン領域6
と基板10間とこの第一導電型領域7とドレイン領域6
間の両方がら空乏層が広がるため、この第一導電型領域
7がない構造よりも、延長ドレイン領域6の濃度を濃(
しかつ高耐圧を実現できるので、ドレイン6−ソース8
間のオン抵抗を大幅に低くできる。素子の特性をイグナ
イタ用とするため、半導体基板10の濃度を3×101
40Il−3とした。ソース領域8と接して基板10の
コンタクト領域9を形成し、同時にソース電極2でコン
タクトをとった。ゲート電極4としては多結晶シリコン
を用い基板表面には2ミクロン以上のシリコン酸化膜3
を形成した。このシリコン酸化膜3のゲート電極4下部
がゲート酸化膜となる。ドレイン電極1はソース電極と
同じ幅とした。延長ドレイン領域6の深さは5ミクロン
、ドレインコンタクト領域5の深さは10ミクロンとす
ることにより、ダイオードの降伏電圧は360V、MO
Sの降伏電圧は400vである。When a reverse voltage is applied between the drain region 6 and the second conductivity type source region 8 provided on the substrate 10, the drain region 6
and the substrate 10, and between the first conductivity type region 7 and the drain region 6.
Since the depletion layer spreads between both regions, the concentration of the extended drain region 6 is more concentrated (
Moreover, high breakdown voltage can be achieved, so drain 6 - source 8
The on-resistance between the two can be significantly lowered. In order to make the characteristics of the element suitable for an igniter, the concentration of the semiconductor substrate 10 is set to 3×101.
40Il-3. A contact region 9 of the substrate 10 was formed in contact with the source region 8, and at the same time, contact was made with the source electrode 2. The gate electrode 4 is made of polycrystalline silicon, and the substrate surface has a silicon oxide film 3 of 2 microns or more.
was formed. The lower part of the gate electrode 4 of this silicon oxide film 3 becomes a gate oxide film. The drain electrode 1 was made to have the same width as the source electrode. By setting the depth of the extended drain region 6 to 5 microns and the depth of the drain contact region 5 to 10 microns, the breakdown voltage of the diode is 360V, MO
The breakdown voltage of S is 400v.
発明の効果
以上のように本発明によればMOSFETの降伏電圧よ
りも低い降伏電圧のダイオードをMOSFETのドレイ
ン−ソース間と形成して1チツプ内に作り込むことがで
きる。Effects of the Invention As described above, according to the present invention, a diode having a breakdown voltage lower than that of the MOSFET can be formed between the drain and source of the MOSFET, and can be built into one chip.
第1図は本発明の一実施例における半導体装置の断面図
、第2図は一般的なイグナイタ装置の回路図、第3図は
第2図のMOSFETのスイッチング時のドレイン電圧
の変化を示す波形図、第4図はMOSFETのドレイン
−ソース間が降伏し第
図
1・・・・・・ドレイン電極、2・・・・・・ソース電
極、3・・・・・・シリコン酸化膜、4・・・・・・ゲ
ート電極、5・・・・・・ドレインコンタクト領域、6
・・・・・・延長ドレイン領域、7・・・・・・第1導
電型領域、8・・・・・・ソース領域、9・・・・・・
基板コンタクト領域、10・・・・・・半導体基板、1
1・・・・・・基板よりも高濃度の第一導電型領域。
代理人の氏名 弁理士 小鍛治 明ほか22第
図
1聞
M閉
?4−−−・
2’5 ・・−
?6−・・
?7 °°−
ドしインを檜
ソース電極
#i化シリコン繰
ゲート電〕参
30− 裏ト良ドレイン剣0戎
32− 養板コンタクト刻0^FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a general igniter device, and FIG. 3 is a waveform showing changes in drain voltage during switching of the MOSFET shown in FIG. Figure 4 shows breakdown between the drain and source of the MOSFET. ...Gate electrode, 5...Drain contact region, 6
...Extended drain region, 7...First conductivity type region, 8...Source region, 9...
Substrate contact region, 10...Semiconductor substrate, 1
1... First conductivity type region with higher concentration than the substrate. Name of agent Patent attorney Akira Kokaji et al. 22 Figure 1 M closed? 4----・2'5...-? 6-...? 7 °°- Drain the source electrode #i-based silicon gate electrode] 30- Back drain sword 0 32- Inner plate contact 0^
Claims (2)
のソース領域とドレインコンタクト領域との間に、上記
ドレインコンタクト領域に接する第二導電型の延長ドレ
イン領域を設け、上記延長ドレイン領域内の表面に延長
ドレイン領域と逆バイアスされた第一導電型領域を設け
、延長ドレイン領域よりも深いドレインコンタクト領域
を設け、第一導電型基板の下に半導体基板よりも高濃度
の第一導電型の下層高濃度領域を設け、延長ドレイン領
域とソース領域間に位置する第一導電型半導体基板の表
面をチャネル領域とし、このチャネル領域の上にゲート
酸化膜を介してゲート電極を設け、ソース領域は上記半
導体基板に電気的に接続されており、ドレイン−ソース
間に逆電圧を印加したとき、ドレインコンタクト領域と
半導体基板間で降伏がおこる半導体装置。(1) An extended drain region of a second conductivity type that is in contact with the drain contact region is provided between a source region of a second conductivity type and a drain contact region formed in a semiconductor substrate of a first conductivity type, and the extended drain region of the second conductivity type is provided in contact with the drain contact region. An extended drain region and a reverse biased first conductivity type region are provided on the surface of the region, a drain contact region deeper than the extended drain region is provided, and a first conductivity type region having a higher concentration than the semiconductor substrate is provided below the first conductivity type substrate. A conductivity type lower layer high concentration region is provided, the surface of the first conductivity type semiconductor substrate located between the extended drain region and the source region is used as a channel region, and a gate electrode is provided on the channel region via a gate oxide film, A semiconductor device in which a source region is electrically connected to the semiconductor substrate, and breakdown occurs between the drain contact region and the semiconductor substrate when a reverse voltage is applied between the drain and the source.
装置。(2) An igniter device using the semiconductor device according to claim 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22579690A JPH04107876A (en) | 1990-08-27 | 1990-08-27 | Semiconductor device and ignitor using it |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22579690A JPH04107876A (en) | 1990-08-27 | 1990-08-27 | Semiconductor device and ignitor using it |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04107876A true JPH04107876A (en) | 1992-04-09 |
Family
ID=16834918
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22579690A Pending JPH04107876A (en) | 1990-08-27 | 1990-08-27 | Semiconductor device and ignitor using it |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04107876A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07147400A (en) * | 1993-11-22 | 1995-06-06 | Nec Corp | Semiconductor device |
US6404012B1 (en) | 1997-11-13 | 2002-06-11 | Nec Corporation | Semiconductor device having a reverse conductive type diffusion layer in an extended drain diffusion layer |
JP2004031804A (en) * | 2002-06-27 | 2004-01-29 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method thereof |
CN113540083A (en) * | 2020-07-17 | 2021-10-22 | 成都芯源系统有限公司 | Field effect transistor device and control method thereof |
-
1990
- 1990-08-27 JP JP22579690A patent/JPH04107876A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07147400A (en) * | 1993-11-22 | 1995-06-06 | Nec Corp | Semiconductor device |
JP2658842B2 (en) * | 1993-11-22 | 1997-09-30 | 日本電気株式会社 | Semiconductor device |
US6404012B1 (en) | 1997-11-13 | 2002-06-11 | Nec Corporation | Semiconductor device having a reverse conductive type diffusion layer in an extended drain diffusion layer |
JP2004031804A (en) * | 2002-06-27 | 2004-01-29 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method thereof |
JP4677166B2 (en) * | 2002-06-27 | 2011-04-27 | 三洋電機株式会社 | Semiconductor device and manufacturing method thereof |
CN113540083A (en) * | 2020-07-17 | 2021-10-22 | 成都芯源系统有限公司 | Field effect transistor device and control method thereof |
CN113540083B (en) * | 2020-07-17 | 2023-09-05 | 成都芯源系统有限公司 | Field effect transistor device and control method thereof |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6246092B1 (en) | High breakdown voltage MOS semiconductor apparatus | |
US5973359A (en) | MOS type semiconductor device | |
JP3243902B2 (en) | Semiconductor device | |
JP2635828B2 (en) | Semiconductor device | |
KR920010314B1 (en) | Semiconductor device | |
JP3076468B2 (en) | Semiconductor device | |
JPH04283968A (en) | Insulating gate type bipolar transistor | |
JP2946750B2 (en) | Semiconductor device | |
JP3186405B2 (en) | Horizontal MOSFET | |
JPS61124178A (en) | Field effect semiconductor device | |
US9035351B2 (en) | Semiconductor device | |
JP3185292B2 (en) | Semiconductor device | |
JPH04107876A (en) | Semiconductor device and ignitor using it | |
JP3226075B2 (en) | Vertical MOS semiconductor device | |
JP3911719B2 (en) | Insulated gate bipolar transistor with built-in current detector | |
JPH0154865B2 (en) | ||
JP4431761B2 (en) | MOS type semiconductor device | |
JPH04107878A (en) | Semiconductor device and ignitor using the same | |
JPH0254969A (en) | MOS type semiconductor device | |
JPH04107871A (en) | Semiconductor device and igniter device using it | |
EP0622853B1 (en) | Insulated gate bipolar transistor | |
JPS58140165A (en) | field effect semiconductor device | |
JPH0478022B2 (en) | ||
JP2608975B2 (en) | Semiconductor device and igniter device using the same | |
US20230418319A1 (en) | Semiconductor transistors having minimum gate-to-source voltage clamp circuits |