JPH04106624A - Microprogram storing system - Google Patents

Abstract

PURPOSE:To store a microprogram in a short time by controlling the storage of the microprogram by operating a common bus which is commonly connected to various kinds of controllers. CONSTITUTION:This microprogram storing system has a CS write control circuit 16 which instructs a microprogram storing memory (CS) 17 to write microprogram data in accordance with the instruction of a monitor circuit 12 which monitors a system bus 100. This system also has a CS storage instructing section 18 which instructs the sending of the microprogram data to the system bus at data sending timing after reading out a microprogram storing instruction, the address information of the microprogram storing memory, and number information of the device in which the microprogram data are to be stored when the data read out from the main storage controller 1 are the microprogram data. Therefore, the microprogram is stored in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram storage system, and particularly to a microprogram storage system in a multiprocessor system.

[Conventional technology]

Conventionally, in this type of micro-program storage system, all control devices independently had a control circuit for storing micro-programs.

[Problem to be solved by the invention]

The conventional micro-Φ program storage method described above is carried out by means of each control device sequentially reading out the micro-Φ program data stored in the main memory and storing it in the micro-program storage memory. The disadvantage is that it takes a long time.

Furthermore, if each control unit simultaneously reads microprogram data stored in the main memory and stores it in the microprogram storage memory, contention on the system common bus increases. This has the drawback that the efficiency of using the system common bus is reduced due to certain problems.

[Means to solve the problem]

The micro program storage method of the present invention includes a system bus monitoring circuit that monitors a system common bus, and a cs write that instructs writing of micro program storage memory into the micro program storage memory based on instructions from the system bus monitoring circuit. A system that controls a system common bus for controlling access to the main memory control device and communication with other control sieve devices; At the time of program data, the CS storage instruction section reads the micro program storage instruction, the address information of the micro Φ program storage memory, and the device number information for storing the micro program data and instructs them to be sent to the system bus at the data sending timing. have.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

A main memory device (hereinafter referred to as MMU) 1 and a central processing unit (hereinafter referred to as CPU) 10 are connected by a system common bus (hereinafter referred to as system bus) 100.

CPU10 accesses the MMUI or communicates with other control devices (not shown) via the system bus 100.

The system bus 100 is a control line group (hereinafter referred to as CTL) 1
10, an instruction line group (hereinafter referred to as CMR) 120, an address display line group (hereinafter referred to as ADH) 130, and a read/write data line group (hereinafter referred to as RWD) 140.

The system control circuit 11 manages all controls for the system bus 100.

Micro program storage memory (hereinafter referred to as CS) 1
7 stores micro φ program data indicated by RWD 140 at a storage address indicated by ADR 130 at a predetermined timing according to instructions from CS write control unit 16.

The system bus monitoring circuit 12 includes a command monitoring section 13 that monitors the 0MR 120, an address/device monitoring section 14 that monitors the ADR 130, and a data monitoring section 1 that monitors the RWD 140.
5, when an instruction to store microprogram data to the CS 17 is detected on the system bus 100, the CS write control unit 16 is activated.

Write address information to the CS 17 is sent to the CS 17 via the connection line 14a, and write data is sent to the CS 17 via the connection line 15a.
supplied to

The CS storage instruction unit 18 instructs the MMUI read operation via the system bus control circuit 11, and
When the system bus control circuit reports that the right to use the MMUI has been obtained, the read data read from the MMUI becomes RWD.
140, CS storage instruction information is sent to the CMR 120, specifying a device to perform CS storage,
Instructs the system bus control circuit 11 to send CS storage address information to the ADR 130.

FIG. 2 is a timing chart showing an example of the operation of storing the micro ψ program data in the CS 17 in FIG.

The numbers shown in the drawings and the same numbers given to the control sections and connection lines shown in FIG. 1 indicate the states of the respective control sections and connection lines shown in FIG. Hereafter, Fig. 1.

This will be explained with reference to FIG.

REQ 111 is a request signal for the right to use the system bus 100, and ACP 112 is a signal indicating that the right to use the system bus 100 has been obtained, and is part of the signals in the CTL 110.

The operation stage 150 is for explaining the operation status on the system bus 100 in an easy-to-understand manner for each system bus cycle.

At stage SO, CPU10 requests the right to use the system bus 100 using REQll, and if use of the system bus 100 is permitted, at stage S1, a response from the ACP112 is returned from MMU1, and the CPU 10 obtains the right to use the system bus 100. I can do things.

The CPU 10, which has obtained the right to use the system bus 100, sends an MMUI read instruction (MMRead) to the CPU at stage S2.
Enter the MMUI access address (MM Add
ress) to ADR 140 to request a read operation of the microprogram data stored in MMU1.

The MMUI sends read data (ReadData) to the RWD 140 in stage S4 as a result of performing the read operation.

The CS storage instruction unit 18 stores the system bus 1 at stage S1.
The system large control circuit 11 has reported that the right to use 00 has been obtained, and CS is sent to ADR130 at stage S4.
The target device number (device ID number) to store the read data on the RWD 140 to the CS 17, the instruction to send the access address data (CSAddress) to the CS 17, and the CM
The system node 10 sends a micro program data storage instruction (C6Write) to the CS 17 to the DI 20.
0 to the system bus control circuit 11.

The system bus control circuit 11 performs CMD at stage S4.
120 and ADR 130.

The system bus monitoring circuit 12 performs CMD at stage S4.
When it detects that the C3Write instruction indicated by 120 and the device ID number indicated by ADR130 are equal to its own device ID number, the CSAddress, l indicated by ADR130 is sent.
! : Instructs the CS write control unit 16 to use Read Data indicated by RWD 140 to store micro program data in the CS 17 at stage S5.

In Figure 1, we have explained one CPU, but when there are multiple CPUs, the method of storing microprogram data in the microprogram memory for all CPUs is to use the ADR130. This can be done by instructing broadcast designation as device ID number information.

Figure 3 shows the device ID number information sent to the ADR 130 and the N
An example of a layout diagram of CSAdress information is shown.

ADR130 consists of 4 BYTE, and the first IB
YTE is used as a designation of device ID number information. 3
The BYTE and 4th BYTE are CSAd r e s s
Used as an information specification.

The 0th to 3rd bits of the IBYTE are device specified and are logical values.
0000'' indicates CPU selection, bits 4 to 7 specify device number, bit 7 specifies 1'1, bit 62
Specify number, bit5 specifies number 33, bxt4! Indicates No. 4 designation.

Therefore, the IBYTE has the logical value “00000001”
”, CPU specifies “1”, logical value “00001111”
"CPU"1. '2゜' 3. ' Specify 4.

Although four CPUs have been described in the figure, the device specification bit length and the device number specification bit length may be freely set depending on the system scale. Further, up to the 2nd BYTE may be set as the device ID number designation.

We have explained the CPU as a device specification, but when specifying another control device, for example, when the logical value of bito~3 is '0001', the input/output processing device is specified. It's okay.

FIG. 4 is a block diagram showing an example of a multi-processor writing system.

In the figure, 1 is the MMU, 10 is the CPU, 100 is the system bus, and in Figures 1 and 2, the explanation has been made for the above, but in a multi-processor system,
There are multiple central processing units (CPU' n-11
).

3 and 4 are input/output control devices (IO
P), there are multiple units like the CPU.

Under the control of IOP'13 is a disk controller MSC20.
Various input/output devices such as a printer control device LPG 30 are connected via an input/output bus 200.

A plurality of disk devices DSK21 are connected under the MSC 20, and a printer device 31 is connected under the LPC 30.

Similarly to IOP'13, various input/output devices are connected under IOP'n4 via an input/output bus (not shown). 5
VP2 is a processing unit that controls diagnostics of the entire multi-processor system.

CPU" 1 10. CPU' nl 1 is a processing device with the same structure, and IOP' 13. IOP' n4
The same is true.

In the explanation of the present invention, the CPU has been explained as a representative, but in the case of a processing device with the same structure, the micro
The same applies to programs, and it is clear that the micro program storage method can be used similarly when targeting IOPs. The same goes for storing microprograms in various input/output devices connected under the input/output bus 200.

〔Effect of the invention〕

As explained above, the present invention enables storage of microprograms to be controlled by bus operations of a common bus that connects various control devices in common, and a representative control device to control reading and storing of microprogram data. Micro programs can be stored for all control devices, so micro programs can be stored in a short time.
This has the effect of allowing programs to be stored.

Furthermore, since this can be done without exclusive use of the common bus, it has the effect of increasing the efficiency of using the common bus.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an operation timing chart of the system gold bus 100 shown in FIG.
FIG. 4 is a block diagram showing an example of a multi-processor system. 1.10...Control! Place, 100... system bus,
11-18...control circuit, 14a, 15b・
...Connection line, 110-140...System bus 100
A group of connecting lines that make up the .

Claims (1)

[Claims] In a microprogram storage method for a multiprocessor system configured by connecting a plurality of control devices via a system common bus, a system bus monitoring circuit monitors the system common bus, and the microprogram is stored according to instructions from the system bus monitoring circuit. a CS write control unit that instructs the memory to write microprogram data;
A system bus control circuit that controls the system common bus for controlling access to the main memory control device and communication with other control devices;・
It is equipped with a CS storage instruction unit that instructs to send a program storage instruction, address information of the micro program storage memory, and micro program data storage target device number information to the system bus common bus at the read data sending timing. When there are multiple control devices, the representative control device reads out the micro program data stored in the main memory control device and instructs the control device to store the CS, thereby reading out the micro program data of all the control devices. 1. A micro program storage method characterized by comprising means for storing at the same time.