JPH0410654B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a processing device for an electronic computer. This invention relates to a start-up control method for automatic self-diagnosis.

[Background of the invention]

Conventionally, in order to guarantee the reliability of electronic computer systems, automatic self-diagnosis functions have often been added to processing devices.

For example, MINI-MICRO issued in July 1980
In "A Self-diagnosing minicomputer" described on pages 90 to 94 of SYSTEMS/July 1980,
When a hardware reset is applied, a single board with hard core (including 32K bytes of RAM)
It is stated that the computer should be checked.

However, improvements in the speed of processors have lagged behind the increase in memory capacity due to advances in semiconductor technology, and as a result, at startup (such as when the power is turned on, the program is loaded into the main memory and executed from a certain address). ), there is a problem that automatic self-diagnosis takes a long time. For example, when checking main memory, a 2 MIPS processor uses 8 Mbytes (8 byte access width).
It takes a few seconds to check the memory of , but when the memory is expanded to 32MB it takes about 20 seconds. If the system startup frequency is about once/day, 20 seconds is no problem, but when debugging the system, it becomes necessary to start up many times, which becomes a problem.

There is also a method in which the main memory is checked only when necessary based on a command from the operator. This method is convenient because unnecessary memory check operations are omitted during debugging, but
In order to guarantee the reliability of the system, the operator must start a memory check every time during normal operations other than debugging, which is cumbersome.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a startup control method for a processing device that performs automatic self-diagnosis at startup, which reduces startup time and eliminates the need for troublesome operations by an operator to ensure reliability.

[Summary of the invention]

The present invention has means for storing whether the processing device is in a debugging state or in a normal state, and means for changing the stored contents, and when the stored contents indicate a debugging state, the processor is diagnosed. The system is characterized in that it performs processor diagnostics and main memory diagnostics during normal times.

[Embodiments of the invention]

Examples of the present invention will be described below. As embodiments of the invention, a first embodiment in which a mechanical switch is used as means for storing two states and a second embodiment in which a semiconductor memory is used will be described.

FIG. 3 shows an example of the overall configuration of a processing device system that is the background of the present invention. The processing device 1 includes a display device 2 for the operator such as a character display.
and an input device 3 from the operator such as a keyboard.
are connected. The processing device 1 also has an auxiliary storage device 4 and an operator panel 5. The operator panel 5 has a reset switch 6 (push button type) and an auto switch 7 (on/off selection type).
and is provided.

FIG. 4 shows the internal configuration of the processing device 1. The processor 11 uses the ROM via the system bus 14.
12 or the program in the main memory 13 is read and executed. In addition, the processor 11 uses the same bus 14.
The contents of the power-on flag 18 and auto switch 7, which will be described later, can be read through the gate 15. Further, the processor 11 communicates with the display device 2 for the operator and the input device 3 from the operator via the same bus 14, the console input/output device connection mechanism 16, and the interface cable 8. Further, the processor 11 can activate the auxiliary storage connection mechanism 17 via the same bus 14, and the activated mechanism 17 transfers data between the auxiliary storage device 4 and the main memory 13. The output of the reset switch 6 is input to the processor 11, and when the switch is on, the output of the reset switch 6 is input to the processor 11.
resets each connector mechanism connected to the internal and system bus 14, starting at a particular address (eg, address 0) when the switch is turned off. The address corresponds to an address in the ROM 12, and the processor 11 sequentially reads programs from the ROM 12 and executes them. The program activated by this reset is hereinafter referred to as a reset program. The output of the reset switch 6 is also input to a power-on flag 18 (a flag indicating that the reset program has been started upon power restoration), and when the reset switch 6 is turned on, this flag becomes "0". The power restoration control unit 19 outputs a pulse for a certain period of time when power is restored to the processing device. This output is input to the processor 11, which performs a hardware reset in the same way as when the reset switch 6 is turned on, and starts the reset program. The same output is also input to the power-on flag 18, and the power-on flag 18 is set to "1" when the power is restored.

Figure 5 shows the power-on flag 18 and the power recovery control unit 1.
9 shows the detailed configuration of No. 9. At the time of power restoration, while charging the capacitor 21 through the resistor 22, the output of the power restoration control unit 19 becomes "1" and the power-on flag 18 becomes "1". On the other hand, when the reset switch 6 is turned on, the power-on flag 18 becomes "0".

FIG. 1 shows a flowchart of a reset program according to a first embodiment of the present invention. When the reset switch of the processing device is pressed, the hardware within the processing device is reset and then linked to the reset program. This program first determines the power-on flag 18, and if the flag is "1", clears all areas of the main memory to 0 and releases the parity state, then performs a self-diagnosis around the processor and checks the main memory, and then When auto switch 7 is set to OFF state, WAIT state (state that stops processing and waits for operator input)
When the switch is set to the on state, IPL (loading the program from the auxiliary storage device) is performed and the program starts.

On the other hand, when the power-on flag is "0", the processor peripheral self-diagnosis is performed, and when the auto switch of the processing unit is set to "0", which means debugging, it is in the WAIT state, and "1", which means normal operation. ”, the main memory is checked and the program starts.

FIG. 6 shows a flowchart of a program in the WAIT state according to the first embodiment of the present invention. This program, like the reset program, is also in ROM1.
This is a program stored in 2. The program waits until input data from the operator is sent to the console input/output connection mechanism 16.
When input data is sent, it judges the data, and if it means IPL, performs IPL and starts. If the same data means start, start.

The operator sets the auto switch 7 to "1" during normal use. When the reset switch 6 is turned on for startup, the system starts after performing a main memory check, as shown in the flowchart of FIG. On the other hand, during debugging, the auto switch 7 is set to "0".
When the reset switch 6 is turned on for startup, a hardware reset and a self-diagnosis around the processor are performed, but the processing unit immediately enters the WAIT state without checking the main memory. After entering the WAIT state, the operator can immediately start the processing device by inputting data specifying start from the input device 3.

FIG. 2 shows a flowchart of a reset program according to a second embodiment of the present invention. When the reset button on the processing device is pressed, the hardware within the processing device is reset and then linked to the reset program. This program first determines the power-on flag 18, and when the flag is "1", all areas of the main memory 13 are cleared to 0, and when the flag is "0", the main memory is not cleared to 0.
Next, perform a self-diagnosis around the processor. Next, determine the check prohibition flag of a specific address on main memory,
When the flag is "0", the main memory is checked, and when the flag is "1", the main memory is not checked. Next, when the auto switch 7 is set to the OFF state, it enters the WAIT state, and when the auto switch 7 is set to the ON state and the power-on flag 18 is "1", IPL is performed and starts, and when the auto switch 7 is set to the on state and the power-on flag 18 is set to "1", the IPL is started. When 18 is "0", IPL is not performed and starts immediately.

FIG. 7 shows a flowchart of a program in the WAIT state according to the second embodiment of the present invention. The program waits until input data from the operator is sent to the console input/output connection mechanism 16. When input data is sent, it judges the data, and if it means IPL, it performs IPL and enters the state. If the same data means start, start. If it means setting a check prohibition flag, the check prohibition flag at a specific address on the main memory is set to "1" and the program returns to the beginning of the WAIT program. Also, if you want to clear the check prohibition flag, set the check prohibition flag at a specific address on the main memory 13 to "0" and wait
Return to the beginning of the program.

In normal use, when the power is turned on, the power-on flag is "1", so all areas of the main memory are cleared to 0, and the check prohibition flag is also set to "0". When the flag is "0", when the operator turns on the reset switch 6 for startup, a main memory check is performed as shown in the flowchart of the same figure. On the other hand, when debugging, turn on the reset switch 6 with the auto switch 7 off and turn on the processing device.
Set to WAIT state. Thereafter, the operator inputs data specifying the check prohibition flag set from the input device 3, and sets the check prohibition flag on the main memory to "1". Once this flag is set to "1", when you want to restart the system, turn on the reset switch 6, which will perform a hardware reset and a self-diagnosis of the processor peripherals, but will not check the main memory and will restart the processor. Immediately enters WAIT state.

After entering the WAIT state, the operator can immediately start the processing device by inputting data specifying start from the input device 3.

〔Effect of the invention〕

According to the present invention, the restart time during debugging is shortened, and troublesome operations by an operator for guaranteeing reliability are not required. The restart time during debugging can be reduced from, for example, conventionally about 20 seconds to 2 to 3 seconds.

[Brief explanation of drawings]

FIG. 1 is a flowchart of a first embodiment of the present invention, FIG. 2 is a flowchart of a second embodiment of the present invention, and FIG. 3 is an example of the overall configuration of a processing device system that is the background of the present invention. 4 is an internal configuration diagram of the processing device, FIG. 5 is a detailed configuration diagram of the power-on flag and power recovery control unit, and FIG. 6 is a diagram of the first embodiment.
Flowchart when in WAIT state FIG. 7 is a flowchart when in WAIT state of the second embodiment. DESCRIPTION OF SYMBOLS 1... Processing device, 2... Display device, 3... Input device, 4... Auxiliary storage device, 5... Operator panel, 6... Reset switch, 7... Auto switch, 11... Processor, 13... ...Main memory, 18...Power-on flag, 19...Power recovery control unit.

Claims (1)

[Scope of Claims] 1. A processing device comprising means for issuing a command for automatic self-diagnosis, and means for receiving the command and performing automatic self-diagnosis of predetermined items within the processing device including a processor and main memory. comprising a storage means capable of taking two states of activation at normal times and activation at other normal times, and means for changing the state of the storage means,
When the above-mentioned command is received when the memory content of the memory means is in a first state indicating startup during debugging, the processor is diagnosed, and when the memory content of the memory means is in a second state indicating normal startup. A start-up control method for a processing device, characterized in that upon receiving the above command, diagnosis of the processor and diagnosis of the main memory are performed. 2. A start-up control system for a processing device according to claim 1, wherein the means for issuing a diagnostic command is a reset switch that can be operated by an operator. 3. In claim 1, the means for issuing a diagnostic command is a processing device such as a reset switch that can be operated by an operator and a circuit that automatically notifies the processing device that the power has just been restored. startup control method. 4. A start-up control system for a processing device according to claim 1, wherein the storage means is a mechanical switch. 5. A start-up control system for a processing device according to claim 1, wherein the storage means is a semiconductor memory. 6 In claim 1, the storage means is set to either the first or second state by a command from the operator, and is set to the second state on the condition that it is in the state immediately after power restoration. A start-up control method for processing equipment.