JPH0395799A - Sample-and-hold circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sample and hold circuit, and particularly to a circuit system for realizing a highly accurate sample and hold circuit.

[Conventional technology]

Conventionally, regarding sample and hold circuits, Gendai Kogakusha ``
As shown in Switched Capacitor Circuit J (pp.56-57), switch 2 and capacitor 3 as shown in Fig.
A circuit consisting of a buffer amplifier 7 and a buffer amplifier 7 is used.

[Problem to be solved by the invention]

The above conventional technology does not take into consideration the feedthrough caused by charge injection generated by the sample switch, and an offset voltage is generated due to the feedthrough, so the input voltage and the held voltage differ by the amount of this offset voltage. There was a problem with the difference.

That is, in the conventional sample-and-hold circuit shown in FIG. 2, when switch 2 is turned off to hold the input, a portion (approximately half) of the channel charge stored under the gate of transistor switch 2 qrv flows into the capacitor 3. Therefore, capacitor 3
The voltage stored in is not the input voltage Vln? Therefore, it deviates from the original value Vln by qit/C.

(Here, C is the capacitance value of the capacitor 3.) This is called an offset voltage.

An object of the present invention is to provide a sample-and-hold circuit to which a circuit for reducing offset voltage is added.

In order to realize this purpose, the author has already filed a patent application in 1983.
- In No. 304099, a method for reducing offset voltage due to feedthrough was proposed. However, the above method does not take into account the input voltage dependence of the channel charge q■, and the offset voltage cannot be reduced completely.

An object of the present invention is to propose a circuit that reduces the offset voltage including the input voltage dependence of the channel charge qtt.

[Means to solve the problem]

The above purpose is to provide a differential input terminal for correction in the buffer amplifier of the sample and hold circuit, and to apply a voltage sufficient to cancel out the offset voltage of qit/C generated in the sample and hold circuit to the differential input terminal for correction. It is achieved by applying

To generate a correction voltage, for example, connect a sample-and-hold circuit that samples and holds the input voltage to the positive and negative sides of the correction input terminal, and double the size of the sample-and-hold switch on the negative side. This can be achieved by doing this.

[Effect]

A differential amplifier with a correction input converts the sum of the voltage difference (VIP VIN) applied to the differential input and the voltage difference (V 2P - V 2N) applied to the correction differential input into a high gain A.
The output voltage V out is amplified by the output voltage V out .

In other words, ? out”A((Vtp VIN)+(VZF V
zN))■=(2).

Here, from the output V out to the negative input VI of the differential input
When negative feedback is applied to N, V IN = V in equation (2).
out, A Vout= (VIP+(V2P V2N)
) −(3)1+A. If the gain A of the amplifier is large enough, Vout=
V1p+(Vzp V2N) −(4)
becomes. In other words, the output V out of this amplifier with negative feedback applied to the differential input is equal to the voltage VI applied to the positive input.
P and the voltage difference applied to the corrected differential input (V2P-Vz
N) is added.

Therefore, by connecting a sample hold circuit to the positive input and applying a correction voltage to the correction input, the error can be canceled out. In other words, in the positive input sample and hold circuit. An offset of qtt/C occurs. Therefore, the voltage vtp of the positive input is C2.

The correction voltage is generated by connecting sample and hold circuits to the positive and negative sides of the correction input terminal to sample and hold the input voltage. At this time, if the switch size of the negative side sample and hold circuit is doubled, the amount of channel charge will be doubled, and the offset will be doubled.
It will be doubled. That is, the voltage V2P on the positive side and the voltage V2N on the negative side of the correction terminal are each C. Therefore, the output voltage of this circuit is expressed as (5) in equation (4).
) ~ (7) Substituting the formula? Vt■...(8). In other words, the offset voltage of the input voltage q tt/C
is canceled by the correction input voltage difference -Cltt/C, and an output voltage without offset voltage is obtained.

This offset voltage qz+ changes depending on the input voltage, but according to the present invention, since all offset voltages are offsets that occur when the input voltage v1n is the same, the offsets are also equal and it is not possible to completely cancel the offset. can. In Japanese Patent Application No. 63-304099, the offset voltage for correction is generated from a fixed voltage V r e Z that is unrelated to the input voltage, so the offset voltages are not completely equal, and it is impossible to completely cancel the offset. There wasn't.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. The configuration of this circuit is as follows. First, the differential input terminal 4-1,
A differential correction input terminal 4-2 is connected in parallel to the differential input terminal 4-1 to a differential amplifier with a current mirror load (5-1.5-2). Then connect the output terminal 6 of the amplifier to the differential input terminal 4-? Connect to the negative terminal of By doing this, it is possible to create an amplifier with a correction input in which negative feedback is applied to the differential input. Next, three sample and hold circuits are connected to the input terminal L-1. The first sample and hold circuit consists of a switch 2-1 and a capacitor 3-1, the output of which is connected to the positive input of the differential input 4-1. The second sample and hold circuit consists of switch 2-2 and capacitor 3.
-2, and the output is connected to the negative side of the corrected differential input 4-2. Further, the third sample and hold circuit includes a switch 2-3 and a capacitor 3-3, and its output is connected to the positive side of the corrected differential input 4-2.

Next, the operation of this circuit will be explained. When the first sample-and-hold circuit (2-1.3-1) samples and holds the input voltage VIn, an offset of Δ■ (=q■/C) occurs at point ■ due to charge injection. At the same time, the second and third sample and hold circuits (2-2.3-2,
2-3.3-3) samples and holds the input voltage vtn. Here, the second sample hold circuit (2-2.
The switch 2-2 in 2-3) is twice the size of the other switches (that is, the channel width of the MOS transistor constituting the switch 2-2 is twice). Then, due to charge injection, offsets 1~(= q tt/C
, 2 q tt/C) occurs.

As explained in equation (4), the output voltage of an amplifier with correction input that applies negative feedback to the differential input is the voltage (V, n+ΔV) applied to the positive input and the voltage applied to the correction differential input. voltage difference (v+i+ΔV)-(V,n+2ΔV)=-
ΔV) is added, so Vout ” V
tn+ΔV-ΔV=V+n (9), and an output with offset voltage canceled is obtained. In this way, a sample and hold circuit without offset voltage is obtained.

Next, a second embodiment will be explained with reference to FIG.

In FIG. 3, the amplifier with correction input is represented by a triangular symbol 7. Assume that the lower triangle represents the corrected differential input terminal. Also in this embodiment, the lth (main) sample and hold circuit (switch 2-■ and capacitor 3-1)
There is no change in the fact that the offset ΔV generated by the correction input is canceled by the offset difference -ΔV generated by the correction input. However, the way in which the offset difference occurs is changing. That is, the second
Third sample and hold circuit (respectively switch 2-
2 and capacitor 3-2; instead of doubling the size of sample switch 2-2 in the second sample-and-hold circuit, the size of capacitor 3-2 is The size of the other half is set to C/2.

By doing this, the offset generated in the second sample and hold circuit is doubled by 2 q ft/C = 2
ΔV, and the effect of offset cancellation can be obtained.

Next, third and fourth embodiments are shown in FIGS. 4 and 5.

These are some examples of configurations of the amplifier with correction input. FIG. 4 shows an amplifier in which the gain is increased by using a cascode type output stage, and FIG. 5 shows an amplifier in which the gain is increased by using a cascode stage after the current is folded back by a current mirror.

A fifth embodiment is shown in FIG. In this embodiment, the method of adding currents is different from that in the first to fourth embodiments. In the fourth to fourth methods, a correction differential input is provided in parallel to the differential input, and the correction current is added to the differential input current. In this embodiment, the current of the differential input circuit is controlled by current mirrors (5-1-al, 5-1-a2 pair and 5-1-b
The same current is produced to the output stage by the current mirror (5-2-a 1. 5-2-a 2 pair, 5-2 - b
1, 5-2-b2 pair) to the output stage, and the current is added at the output stage. This method also provides the effect of an amplifier with a correction terminal.

Further, in the first to fifth embodiments, the same effect can be obtained even if a circuit is created in which the PMOS and NMOS are inverted.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain a sample-and-hold circuit that cancels out the offset voltage caused by charge injection of the switch, and it is possible to improve the accuracy of the sample-and-hold circuit.

[Brief explanation of drawings]

FIG. 1 shows a high precision sample and hold circuit according to an embodiment of the present invention, FIG. 2 shows a conventional sample and hold circuit, FIG. 3 shows a high precision sample and hold circuit according to an embodiment of the present invention, and FIGS. 6 and 6 respectively show high precision sample and hold circuits according to other embodiments of the present invention. 1...Input terminal, 2...Sample switch, 3...Sample capacitance, 4-1...Differential input terminal, 4-2...Correction %+ National number 3 Figure 2 Lacquer'''3- 3 j2”t 17’+Jiji 4 Yamasashi 5 Figure b

Claims (1)

[Claims] 1. In a sample and hold circuit in which a buffer amplifier is connected to a basic sample and hold circuit consisting of a switch and a capacitor, (1) a new differential input for correction is added in parallel to the differential input of the buffer amplifier; (2) A basic sample and hold circuit that samples and holds an input voltage is provided at each of the positive side and negative side input terminals of the corrected differential input. 2. The sample and hold circuit according to claim 1, wherein the switch size of the basic sample and hold circuit provided at the negative input terminal of the corrected differential input is twice that of the positive side. 3. The sample-and-hold circuit according to claim 1, wherein the value of the capacitor of the basic sample-and-hold circuit provided at the negative input terminal of the corrected differential input is set to 1/2 of the value of the other capacitor.