JPH0395773A - Recorded data reproducing device and window forming circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a recorded data reproducing device that decodes and reproduces data signals recorded on a recording medium such as a magnetic disk, and in particular, relates to a recorded data reproducing device that decodes and reproduces data signals recorded on a recording medium such as a magnetic disk. The present invention relates to a recorded data reproducing device that decodes a data signal using a window formed by the above.

[Prior Art] A phase synchronization circuit used for reproducing and demodulating a recorded signal in a magnetic disk device, etc. has conventionally been a fifth phase synchronization circuit.
The block configuration shown in the figure is common.

The phase synchronization circuit 1 includes a phase comparator 51 and a charge pump 5.
2. Loop filter 53 and voltage controlled oscillator (hereinafter referred to as V
C○) ltr& at 54 and synchronized with data signal 8■
Generates CO clock 9.

The vCO clock 9 is frequency-divided by the frequency divider circuit 2 and becomes a window 10. When the window 10 is open (in this case, at the "H" level), the input data signal 8 is received by the decoder 7 and demodulated.

In general, in a magnetic disk drive, a peak shift phenomenon of the data signal 8 occurs due to magnetic interference on the disk, etc. The range in which this peak shift I-phenomenon can be tolerated is called the wind margin. It becomes a factor. In order to maximize this window margin, the delay amount of the delay line 55 should be set to half the period of the CO clock 9 so that the data signal 8 input to the decoder 7 rises at the center of the window 10.

[Problem to be solved by the invention] However. , Actually, depending on the performance of the phase-locked circuit 1, ■C
○The clock 9 and the data signal 8 may not be completely synchronized, causing a phase shift, which may result in a loss of wind margin.

On the other hand, in order to correct this phase shift, it is conceivable to use a tapped delay line 55 and adjust the amount of delay.

However, the above technique requires a tapped delay line and has the problem of high cost due to adjustment.

Furthermore, since it is greatly affected by the accuracy of the delay line used, an expensive and highly accurate one must be used. Moreover, even with high precision, there is a problem in that the effects of aging cannot be avoided.

Incidentally, Japanese Patent Application Laid-Open No. 63-107231 discloses a digital phase-locked loop circuit configured to select the optimum one among a plurality of types of delay clock signals from a delay line circuit.

However, this technique merely selects a clock, and does not take into consideration automatic adjustment of phase shifts so as to maximize the window margin. Therefore,
This technique cannot solve the problems mentioned above.

The purpose of the present invention is to automatically adjust the phase shift so that the wint margin is always maximized without using a delay line, or even when using a delay line, without being affected by accuracy or aging. An object of the present invention is to provide a recorded data reproducing device.

Another object of the present invention is to provide a window forming circuit suitable for an i'Iif recording data reproducing apparatus.

[Means for Solving the Problems] In order to achieve the above object, the present invention decodes and reproduces a data signal recorded on a recording medium using a wint formed by an output from a phase synchronization circuit. In the recorded data reproducing device, a multiphase window forming means for forming a multiphase window from the formed windows, and a window for selecting a window having an optimal phase difference with a data signal from among the multiphase windows. and a selection means, and the data signal is decoded using the selected window.

Further, the present invention includes a phase-locked circuit as a window forming circuit that can be suitably used to achieve the above object, and forms a polyphase window from the window formed by the output from the phase-locked circuit. A window forming circuit is provided, comprising a multiphase window forming means and a window selection means for selecting and outputting a window having an optimum phase difference with a data signal from among the multiphase windows.

The multiphase window forming means can be configured using, for example, a delay circuit that delays an input signal by n stages and outputs a delayed signal as a window for each stage. One example is one in which inverters are connected in series.

The window selection means has a function of detecting an open/closed state of a multiphase window outputted from the window forming means using a data signal, and a function of detecting a window in which the data signal rises at the center from the detection result. It can be configured with

Further, the window selection means may include an average calculation circuit that averages the windows sequentially detected by the window detection function and selects an optimal window using the obtained average value. preferable. This average calculation circuit can be configured to include, for example, a counter that counts the number of selections of windows that are sequentially selected in a corresponding manner, and an arithmetic circuit that averages the counts of the 3-counter.

[Operation] In the present invention, the polyphase window forming circuit creates polyphase windows whose phases are slightly shifted.

Further, the window selection means detects the open/closed state of each window at the timing of the rising edge of the data signal, for example, and detects the window in which the data signal is in the center. Then, based on this detection, the optimal window is selected.

It is preferable to use an average calculation circuit when selecting this optimal window. In this case, the average calculation circuit averages the number of detections of the windows detected by the wind center detection circuit, calculates which window is optimal, and outputs the result to a selector that specifically selects a window.

Through these actions, the phase of the data signal and the window can be adjusted so that the window margin is maximized.

[Example code] An embodiment of the present invention will be described below with reference to the drawings.

In addition, the same components are given the same reference numerals, including the above-mentioned FIG. 5, and will not be described repeatedly.

FIG. 1 is a schematic configuration diagram of a phase locked circuit according to the present invention.

This embodiment includes a phase synchronized circuit 1, a frequency divider circuit 2, and a delay circuit 3.
, a wind center detection circuit 4, an average calculation circuit 5, and a selector 6.

The delay circuit 3 is composed of, for example, a buffer amplifier, an inverter, etc. connected in series in n stages, and delays the window 10 output from the frequency divider circuit 2 by n stages, and outputs the output in parallel for each stage from n to n. Polyphase window 1 with terminals
1-1 to 11-n are output.

For example, as shown in FIG. 2, the wind center detection circuit 4 includes an edge detection circuit 21 that detects the rising edge of the data signal 8 and outputs an edge signal 27;
Gate circuits 22-1 to 22-n corresponding to signals 1-1 to 11-n and receiving the edge signals 27 at the timing of the edge signal 27;
latch circuits 23-1 to 23-n that latch the outputs of the gate circuits 22-1 to 22-n, registers 24 that hold the outputs of the latch circuits 23-1 to 23-n, and a window. Which of the windows 11-1 to 11-n corresponds to the center of the rising edge of the data signal 8? A table storage device 25 that calculates in advance based on the open/closed states of these windows 11-1 to 11-n, stores the results as a table, and outputs a center window signal.
and a comparator 26 that compares the contents of the register 24 and the table.

When the table storage device 25 receives the coincidence signal 28 from the comparator 26, the table storage device 25 outputs the center wind signal l.
The configuration is such that a signal is output for any corresponding window among windows 2-1 to 12-n.

For example, as shown in FIG. 4, the average calculation circuit 5 is provided for the center wind signals l2-1 to 12-n output from the wind center detection circuit 4, and includes a counter that counts each of these outputs. 4-1 to 41-n, and an arithmetic circuit 42 that performs average calculation using each count value of the counters 41-1 to 41-n, selects an optimal window, and outputs a selection signal. It is a matter of concern.

The arithmetic circuit 42 can be configured by combining adders, multipliers, dividers, etc., for example. Alternatively, a microprocessor equipped with an arithmetic program may be used.

The selector 6 selects one of the windows 1A1 to 11-n output from the delay circuit 3 based on the selection signal 13 output from the average calculation circuit 5, and selects one of the windows 1 to 1.1. The configuration is such that the signal is output to the decoder 7 as a signal.

Next, the operation of this embodiment will be explained with reference to each of the above-mentioned figures and FIG. 3.

The ■C○ clock 9 synchronized with the data signal 8 by the phase synchronization circuit 1 is frequency-divided by the frequency divider circuit 2, and
becomes. This window 10 is formed by the delay circuit 3 into polyphase windows 11-1 to 11-n (
When there are n windows).

The wind center detection circuit 4 detects the windows 11-1 to 11-1.
11-n and the phase of the data signal 8 are compared to detect a wint in which the data signal 8 is in the center, and the average calculation circuit 5 receives a signal that is the centerwind among the centerwind signals l2-1 to 12-n. Output.

That is, as shown in FIG. 3, an edge signal 27 is generated by an edge detection circuit 21 that detects the rising edge of the data signal 8. At the timing of this Etsujiiko No. 27, the opening/closing status of windows 11-1 to l↓-n is determined by game 1-circuit 2.
2-1 to 22-n, and the latch circuit 23-1
.about.23-n to the register 24.

The data taken into the register 24 is compared with a table prepared in advance in the table storage device 25 by a controller 26. Here, if there is a match table, the comparator 26 notifies the table storage device 25 of this using a match signal 28.

In response to this, the table storage device 25 outputs a signal corresponding to the window for which the coincidence signal has been outputted, for any one of the center window signals 12-1 to 12-n.

The average calculation circuit 5 calculates the average of the center wind signals successively inputted from the wind center detection circuit 4 to find an optimal window, and outputs a selection signal 13 to the selector 6. This selection signal ↓3 causes the selector 6 to output the optimal window 14.

That is, the average calculation circuit 5 has counters 41-1 to 41-41.
-n is used to count the number of times each window is detected for the center wind signals 12-n to 2-n from the wind center detection circuit 4. The calculation circuit 42 calculates the average of the counting results of this counter, determines which window is the optimum window, and outputs the selection signal 13.

An example of average calculation is as follows, where M is the total count value of all counters.

In the average calculation using this formula, each counter is multiplied by the weight m for each stage, so the obtained average value indicates the optimal window.

For example, if three counters are used, and the count value of the first counter is 1, the count value of the second counter is 2, and the count value of the third counter is 1, then M=4, and the above formula is According to the following, an average value of 2 is obtained, and it can be seen that the window corresponding to the counter 2 is optimal.

Note that an appropriate method can be applied to this averaging, such as a method of performing the averaging at an appropriate period, sampling data within this period and calculating the data, or a method of taking a moving average at a constant period.

The decoder 7 uses the window 14 from the selector 6 to demodulate data from the data signal 8.

In this embodiment, since the optimal window is selected from the polyphase windows, it is not affected by the accuracy of the delay circuit and aging. Furthermore, by selecting the optimal window, the wind margin can be maximized.

Furthermore, since this embodiment is not easily affected by accuracy as described above, the delay circuit can be carefully designed without using an expensive delay line. Therefore, the window forming circuit can be constructed at low cost. However, the delay circuit may be constructed using a delay line.

In the embodiment described above, the wind center detection circuit 4 and the average calculation circuit S are constructed of digital circuits consisting only of hardware. However, these can also be configured by software using a microcomputer or the like.

Furthermore, although this embodiment is suitable for signal reproduction in a magnetic recording device, it may also be applied to data reproduction from other recording media.

In the embodiment described above, the center wind signal is obtained using a table storage device, but it may be realized by other means. For example, the center window signal may be determined by calculation using data latched in the latch circuits 23-{ to 23-n.

[Effects of the Invention] According to the present invention, the windows to be delayed only need to be shifted in phase at relatively equal intervals, so there is no need to use an expensive delay line that requires absolute accuracy. In addition, automatic adjustment allows the wind margin to be maximized, and can also accommodate changes over time.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention, Fig. 2 is a block diagram showing an example of the configuration of a wind center detection circuit used in an embodiment of the invention, and Fig. 3 is a block diagram showing a configuration example of a wind center detection circuit used in an embodiment of the present invention. A timing chart showing the operation of the circuit, FIG. 4 is a block diagram showing an example of the configuration of an average calculation circuit used in an embodiment of the present invention, FIG. 5 is a block diagram showing the configuration of a conventional phase synchronization circuit, and FIG. is a timing chart showing the operation of a conventional phase locked circuit. DESCRIPTION OF SYMBOLS 1... Phase synchronization circuit, 2... Frequency division circuit, 3... Delay circuit, 4... Wind center detection circuit, 5... Average calculation circuit, 6... Selector, 7... Decoder, 2
l...Edge detection circuit. 22-1 to 22-n...gate circuit, 23-1 to 23-n...latch circuit, 24.
...Register, 25...Table storage device. 26...
・Comparator, 41-1 to 41-n...counter,
42... Arithmetic circuit. Figure 1 1

Claims (1)

[Scope of Claims] 1. In a recorded data reproducing device that decodes and reproduces a data signal recorded on a recording medium using a window formed by an output from a phase synchronization circuit, a multiphase window forming means for forming a phase window;
1. A recorded data reproducing apparatus comprising: window selection means for selecting a window having an optimal phase difference with a data signal, and decoding the data signal using the selected window. 2. In a window forming circuit that includes a phase-locked circuit and forms a window used when decoding a data signal recorded on a recording medium, a multiphase window is generated from the window formed by the output from the phase-locked circuit. 1. A window forming circuit comprising: a multiphase window forming means for forming a multiphase window; and a window selection means for selecting and outputting a window having an optimum phase difference with a data signal from among the multiphase windows. 3. The recorded data reproducing apparatus according to claim 1, wherein the multiphase window forming means is configured using a delay circuit that delays the input signal by n stages and outputs the delayed signal as a window for each stage, or The window forming circuit according to claim 2. 4. The window selection means has a function of detecting the open/closed state of the multiphase window output from the window forming means using the data signal, and detects a window in which the data signal rises at the center from the detection result. 3. The recorded data reproducing device according to claim 1, or the window forming circuit according to claim 2, wherein the recording data reproducing device is configured to include a function. 5. The window selection means comprises an average calculation circuit that averages the windows successively detected by the window detection function and selects the optimal window using the obtained average value. The recorded data reproducing device according to item 4 or the window forming circuit according to the same item.