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JPH0393905U - - Google Patents

Info

Publication number
JPH0393905U
JPH0393905U JP45290U JP45290U JPH0393905U JP H0393905 U JPH0393905 U JP H0393905U JP 45290 U JP45290 U JP 45290U JP 45290 U JP45290 U JP 45290U JP H0393905 U JPH0393905 U JP H0393905U
Authority
JP
Japan
Prior art keywords
sequence program
programmable controller
sequence
memory
sequence programs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP45290U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP45290U priority Critical patent/JPH0393905U/ja
Publication of JPH0393905U publication Critical patent/JPH0393905U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Programmable Controllers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例および従来の方法
によるプログラマブルコントローラの動作を示す
図、第2図はこの考案の一実施例によるシーケン
スプログラムをシーケンスプログラムメモリへ登
録する方法を示す図、第3図は従来の方法による
シーケンスプログラムをシーケンスプログラムメ
モリへ登録する方法を示す図である。 図において、1はシーケンス切換データ、2は
入力回路、3はCPU、4はチツプセレクト回路
、5は内部データメモリ、6はデコーダ、7はメ
モリ選択信号、8〜10はシーケンスプログラム
メモリ、11はチツプセレクト信号、12はシス
テムメモリ、13はI/Oバスインタフエース、
14は入力部、15は出力部、16はアドレスバ
ス、17はデータバス、18はI/Oバス、19
はシーケンスプログラム格納領域、20はシーケ
ンスプログラムの転送先切換手段、21はシーケ
ンスプログラム転送手段、22は複数のシーケン
スプログラムを格納しているFD、23はシーケ
ンスプログラムの転送指令、24はROM書込み
装置である。なお、図中、同一符号は同一、また
は相当部分を示す。
FIG. 1 is a diagram showing the operation of a programmable controller according to an embodiment of this invention and a conventional method; FIG. 2 is a diagram showing a method of registering a sequence program into a sequence program memory according to an embodiment of this invention; The figure shows a conventional method for registering a sequence program into a sequence program memory. In the figure, 1 is sequence switching data, 2 is an input circuit, 3 is a CPU, 4 is a chip select circuit, 5 is an internal data memory, 6 is a decoder, 7 is a memory selection signal, 8 to 10 are sequence program memories, and 11 is a Chip select signal, 12 is system memory, 13 is I/O bus interface,
14 is an input section, 15 is an output section, 16 is an address bus, 17 is a data bus, 18 is an I/O bus, 19
2 is a sequence program storage area, 20 is a sequence program transfer destination switching means, 21 is a sequence program transfer means, 22 is an FD storing a plurality of sequence programs, 23 is a sequence program transfer command, and 24 is a ROM writing device. be. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数の異なるシーケンスプログラムの選択実行
機能を備えたプログラマブルコントローラにおい
て、シーケンスプログラムを格納する手段にRA
Mを用いたことを特徴とするプログラマブルコン
トローラ。
In a programmable controller equipped with a function of selecting and executing a plurality of different sequence programs, RA is used as a means for storing sequence programs.
A programmable controller characterized by using M.
JP45290U 1990-01-08 1990-01-08 Pending JPH0393905U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP45290U JPH0393905U (en) 1990-01-08 1990-01-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP45290U JPH0393905U (en) 1990-01-08 1990-01-08

Publications (1)

Publication Number Publication Date
JPH0393905U true JPH0393905U (en) 1991-09-25

Family

ID=31504399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP45290U Pending JPH0393905U (en) 1990-01-08 1990-01-08

Country Status (1)

Country Link
JP (1) JPH0393905U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010204737A (en) * 2009-02-27 2010-09-16 Fuji Electric Systems Co Ltd Control system for programmable controller and control program execution method for programmable controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010204737A (en) * 2009-02-27 2010-09-16 Fuji Electric Systems Co Ltd Control system for programmable controller and control program execution method for programmable controller

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