JPH0391339A - Communication controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a communication control device that achieves high-speed data transmission using simpler hardware in a packet-format data transmission system.

[Conventional technology]

An example of the configuration of a conventional communication control device is shown in FIG.

Here, an example is shown in which a shared memory is used as an area for storing communication data.

According to FIG. 2, there is a method in which three computers, a host computer 1, a transmission control computer 2, and a communication control computer, are used to connect the shared memo 1J19, 6゜7 in order to communicate between each computer 17. is adopted.

In this method, the host computer 1 stores the packet information data in the shared memory 6 connected between the host computer 1 and the communication control computer 17, so that there is no need to transfer the packet information data between the shared memories. becomes. Therefore, since the transmission control computer 2 that processes the header of the transmission protocol and the communication control computer 17 that handles the transmission data operate independently, high-speed processing can be achieved. An example of this method is JP-A-62-6
It is stated in the No. 0043 publication.

[Problem to be solved by the invention]

However, the above conventional technology has the following problems. In other words, since three computer systems are used, three shared memories 6゜7.19 and three contention control circuits 8, 9, and 20 are required to connect shared memories between these computers. , the hardware becomes more complex. Further, the communication control computer 17 is used to control the communication control circuit 11 and the DMA control circuit 10, but since it performs the control based on instructions from the transmission control computer 2, it is positioned as a sub-processor of the transmission control computer 2, and is functionally It only has a small role. Furthermore, the bus 15 of the communication control computer 17 is
Since there are two bus masters, the communication control computer 17 and the DMA control circuit 10, the bus load becomes heavy and it is not suitable for high speed.

An object of the present invention is to provide a means for realizing a communication control device for high-speed transmission using simpler hardware.

[Means to solve the problem]

In order to achieve the above object, the present invention provides D
Focusing on the fact that the MA control circuit is controlled by instructions from the transmission control computer, the transmission control computer and the communication control computer are made into one computer, and the D
By making the control bus and memory access bus of the MA control circuit independent, the role of the communication control computer can be shared between the DMA control circuit and the transmission control computer, reducing the number of computers and simplifying the hardware. This is what we aim to do.

In other words, the present invention provides a communication control device that is connected to a computer and performs packet transmission, which includes a first computer (host computer) as a host computer, and a second computer (host computer) that executes a protocol such as an overcontrol procedure. a transmission control computer), a communication control circuit and a DMA control circuit for transmitting data,
A communication means is provided between the host computer and the transmission control computer, a first shared memory is provided between the host computer and the communication control circuit, and a second shared memory is provided between the transmission control computer and the communication control circuit. It is set up.

Further, the control bus of the DMA control circuit is connected to the bus of the transmission control computer, and the memory access bus of the DMA control circuit is connected to the buses of the two shared memories mentioned above.

Therefore, the information data of the packet to be transmitted is given from the host computer to the DMA control circuit via the first shared memory, and the control data of the packet to be transmitted is given from the host computer to the transmission control computer via the communication means. . The transmission control computer generates header data based on the supplied control data, and supplies the generated header data to the DMA control circuit via the second shared memory. After the DMA control circuit combines the given information data and header data into one, the communication control circuit transmits it.

[Effect]

In the present invention having the above configuration, the host computer stores the information data of the packet in the first shared memory,
Also, the control data of the packet is given to the transmission control computer via the communication means (above). The transmission control computer creates header data in the second shared memory based on control data from the host computer, and provides addresses of the header data and information data to the DMA control circuit. The DMA control circuit reads the ladder data from the second shared memory, reads the information data from the first shared memory, and sequentially provides these to the communication control circuit, based on the address from the transmission control computer. It becomes possible to perform transmission.

Therefore, unlike the conventional example, there is no need to send control data to the communication control computer, so the hardware can be simplified and the speed can be increased.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a communication control device according to an embodiment of the present invention.

In the figure, 1 is a host computer, 2 is a transmission control computer, 3.4 is a program memory of the host computer 1 and transmission control computer 2, and 5 is for exchanging control data between the host computer 1 and the transmission control computer 2. This is a FIFO.

Further, 6 is a shared memory for exchanging data between the host computer 1 and the communication control circuit 11, 7 is a shared memory for exchanging data between the transmission control computer 2 and the communication control circuit 11, and 8 is a shared memory 6 9 is a contention control circuit for the shared memory 7, 10 is a DMA control circuit for accessing communication data, and 11 is a communication control circuit for transmitting and receiving communication data.

Further, 12 is a bus of the host computer 1, 13 is a bus of the transmission control computer 2, 14 is a DMA control circuit l side control data bus, and 15 is a memory access bus of the DMA control circuit 10. The control data bus 14 is connected to the bus 13
is connected to.

In the communication control device shown in FIG. 1, the communication control computer is omitted from the conventional example shown in FIG. The difference is that the connection has been changed from shared memory to FIFO5.

Next, a control method during packet data transmission will be described based on this figure.

First, when the host computer 1 generates transmission data, it stores the transmission data in the shared memory 6 and issues a transmission request to the transmission control computer 2 via the FIFO 5.

Based on the transmission request from the host computer l given via the FIFO 5, the transmission control computer 2
Header data is generated according to the HDLC protocol and stored in the shared memory 7.

After storing the header data in the shared memory 7, the transmission control computer 2 sends the address of the header data and the address of the information data to an address control register (not shown) of the DMA control circuit 10 via the control data bus 14. settings and activates the DMA control circuit 10.

The DMA control circuit 10 realizes data transmission by sequentially passing header data and information data to the communication control circuit 11 according to the contents of the address control register.

The communication control circuit 11 converts the data given from the DMA control circuit 10 into serial data according to the HDLC procedure and sends it to the transmission line 16.

As explained above, the host computer 1 only stores the generated data in the shared memory 6, and the rest is controlled by the transmission control computer 2, so there is no extra overhead.

Further, the transmission control computer 2 generates a header according to HDLC transmission protocol processing, and transmits the header to the DMA control circuit 1.
Just set the address to 0, as in the conventional example,
Transmission processing can be accomplished by simply issuing a transmission instruction to a communication control computer. Therefore, no special overhead is generated in transmission processing, so high-speed transmission can be achieved.

Furthermore, data exchange between the host computer l and the transmission control computer 2 uses FIFO5, and while in contention control there is a wait for access to obtain the right to use both buses, FIFO5 connection So,
Since an access wait occurs only when both computers are accessing the FIFO 5, data exchange between the host computer 1 and the transmission control computer 2 can also be speeded up.

〔Effect of the invention〕

As explained above, according to the present invention, there are two computers: a computer that processes data, and a computer that controls transmission.
Since data transmission can be realized with less transmission control overhead, it is possible to realize high-speed data transmission with less hardware.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a communication control device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional communication control device. 1... Host computer 2... Transmission control computer 3.4... Program memory 5... FIFO 8, 9... Competition control circuit 11... Communication control circuit 12, 13, 14, 15. ...Bus 6.7...
Shared memory 10...DMA control circuit 16...Transmission line

Claims (1)

[Claims] 1. A communication control device connected to a computer to perform packet transmission, comprising: a first computer as a host computer; a second computer executing a protocol such as a transmission control procedure; and a communication control circuit and a DMA control circuit for transmitting the first
A communication means is provided between the computer and the second computer, a first shared memory is provided between the first computer and the communication control circuit, and a first shared memory is provided between the second computer and the communication control circuit. A second shared memory is provided between the first and second shared memories, a control bus of the DMA control circuit is connected to a bus of the second computer, and a memory access bus of the DMA control circuit is connected to the first and second shared memories. A communication control device characterized by being connected to a bus. 2. The first computer transmits the information data of the packet to be transmitted to the DM via the first shared memory.
The control data of the packet to be given to the A control circuit and to be transmitted is given to the second computer via the communication means, and the second computer converts the header data based on the given control data. The generated header data is provided to the DMA control circuit via the second shared memory, and the DMA control circuit combines the provided information data and header data into one packet data, and provides the generated header data to the DMA control circuit via the second shared memory. 2. The communication control device according to claim 1, wherein the communication control circuit transmits the information.