JPH0385044A - Delay detection and demodulation circuit - Google Patents

Abstract

PURPOSE:To attain high speed compensation for a frequency drift by correcting the phase of a complex number delay detection output so as to minimize the displacement of two outputs on a complex number plane. CONSTITUTION:A received phase modulation wave from an input terminal 1 is inputted to a delay detection circuit 2, in which the received phase modulation wave is detected by using a phase of one preceding time slot as a reference. Two received waves are multiplied as they are to obtain a sinusoidal delay detection output. A delay circuit 5, a complex number conjugation circuit 6, a complex number multiplication circuit 7 and a moving mean circuit 8 obtain a compensation coefficient to apply sign decision with the calculation of a complex number multiplier circuit 9. Thus, the phase rotation of the delay detection output due to the frequency drift is corrected to compensate a carrier frequency drift at a high speed.

Description

[Detailed description of the invention] [Industrial application field] The present invention is utilized in digital mobile radio communications.

In particular, it relates to improving the deterioration of error rate characteristics of a differential detection demodulation circuit due to carrier frequency drift.

In a differential detection demodulation circuit, the present invention regards the differential detection output and its sign judgment output as complex numbers, and corrects the phase error on the complex plane of the complex differential detection output with respect to the complex judgment output, which is caused by carrier frequency drift. This corrects phase rotation and improves error rate characteristics.

[Conventional technology]

In a phase modulation method such as PSK, synchronous detection or delayed detection is used for demodulation. Using synchronous detection provides superior error characteristics compared to delayed detection. However, in order to perform coherent detection, it is necessary to regenerate the carrier wave. A long preamble signal is required for this carrier wave regeneration, and if used in a burst transmission method, the transmission efficiency will decrease.

On the other hand, delayed detection does not require carrier wave recovery and is therefore suitable for burst transmission.

[Problem to be solved by the invention]

However, delayed detection has the disadvantage that error rate characteristics tend to deteriorate when the carrier frequency changes. Especially in mobile radio communications,
In order to make mobile devices smaller and cheaper, frequency oscillators that are less stable than base station radios are used. For this reason, it has been practically difficult to utilize delayed detection in mobile radio communications.

For carrier frequency fluctuations, we measure the distortion of the delayed detection output due to carrier frequency drift (frequency shift),
A method of controlling the frequency of the receiver local oscillator using the measured value has been considered. However, in the case of random access communication where many subscribers share the same channel,
This frequency control method cannot handle the frequency drifts of each burst arriving from different mobile stations.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and provide a differential detection demodulation circuit that can quickly compensate for carrier frequency drift.

[Means to solve the problem]

A delay detection demodulation circuit of the present invention includes a delay detection circuit that performs delay detection on a received phase modulated wave to generate a complex delay detection output in which a cosine delay detection output is regarded as a real number and a sine detection output is regarded as an imaginary number.
In a differential detection demodulation circuit equipped with a sign determination circuit that determines the sign of the real part and imaginary part of the complex differential detection output and generates a complex determination output, The present invention is characterized by comprising means for obtaining a complex compensation coefficient for compensating the amount of displacement, and means for multiplying the complex differential detection output by the complex compensation coefficient.

It is preferable that the present invention further includes means for detecting a specific pattern included in the received phase modulated wave, and means for correcting the phase uncertainty of the complex determination output using the output of this means.

[For production]

If there is a carrier frequency drift in the received phase modulated wave, the complex differential detection output will rotate on the complex plane. In such a case, the complex differential detection output on the complex plane deviates from the correct complex sign determination output. Therefore, the amount of displacement of the two outputs on the complex plane is determined, and the phase of the complex differential detection output is corrected so that this amount of displacement is minimized.

Generally, the amount of displacement of two complex numbers on a complex plane is obtained by dividing the - side by the other. This is equivalent to multiplying one complex number by the conjugate of the other complex number and dividing by the square of the absolute value of the other complex number. moreover,
The value obtained by multiplying the other complex number by this displacement amount is equal to the one complex number.

Therefore, the complex decision output is multiplied by the conjugate value of the complex differential detection output, averaged, the multiplied value is divided by the average value of the squares of the absolute values of the complex differential detection output, and the complex differential detection output is multiplied by this.

The reason for averaging is to remove the influence of "fluctuations" in the complex differential detection output caused by thermal noise and the like.

Furthermore, if the frequency drift is large (4), the phase error on the complex plane of the complex differential detection output may exceed the phase of half the signal point arrangement interval. In such a case, the symbol is determined to be a different code, and the phase of the complex differential detection output is corrected so that the phase error with this code is reduced. To prevent this, a specific pattern of symbol sequences included in the synchronization word is detected, and the output of the code determination circuit is converted into a correct code.

〔Example〕

FIG. 1 is a block diagram of a differential detection demodulation circuit according to a first embodiment of the present invention.

A delay detection circuit 2 that generates a complex delay detection output by delay-detecting a received phase modulated wave and treating the cosine delay detection output as a real number and the sine detection output as an imaginary number, and a delay detection circuit 2 that generates a complex delay detection output in which a cosine delay detection output is regarded as a real number and a sine delay detection output as an imaginary number, and a real part and an imaginary part of this complex delay detection output are respectively detected. and a sign determination circuit 3 that performs sign determination and generates a complex determination output.

Here, the features of this embodiment include a delay circuit 5, a complex conjugate circuit 6, and a complex multiplication circuit as means for obtaining a complex compensation coefficient for compensating the amount of displacement on the complex plane between the complex delay detection output and the complex judgment output. 7 and a moving average circuit 8, and a complex multiplication circuit 9 as means for multiplying the complex differential detection output by the complex compensation coefficient.

A received phase modulated wave is supplied to an input terminal 1, and this modulated wave is inputted to a delay detection circuit 2. Generally, the phase modulated wave is expressed as s (t) = A cos [2πfct+φ(t) using the phase φ(1) that changes depending on the digital signal.
] , (1). Here, A is the amplitude and fe is the carrier frequency.

The delay detection circuit 2 detects the received phase modulated wave using the phase one time slot before as a reference phase.

For example, in order to detect the received wave s (t,) at time t7, time t. The received wave s (t, -T) at -T is used.

However, T is the symbol length.

If we multiply the two received waves together, we get s (t,)
・s (t, -T) = ACOS[2πfct+φ(1,l)]X ACO9
[2πfct+φ(tI,-T)]=(A”/2
) [cos[4πfet+φ(1,,)+φ(t,
−T)]+cosΔφ(1,)]−−(2), and by removing the frequency 2fc component with a low-pass filter, a cosine delay detection output CO9Δφ(1n) is obtained. However, Δφ(1,) =φ(t7)−φ(t,−T) −
-(3).

Also, if the received wave s (t, -T) is shifted by -π/2 and then multiplied by the signal wave s (t,), the ACO
8[2πfct+φ(11,)]X (-A)sin[
2πfct +φ(tr, -T) co= (A'/2)
[:sin[4πfct+φ(1n)+φ(t,-T
]+sinΔφ(1,):]·(4) By removing the frequency of 2 fct with a low-pass filter, the sine delay detection output sinΔφ(1,) is obtained.

Here, if we consider the cosine delayed detection output cosΔφ(1,) to be the real part and the sine delayed detection output sinΔφ(t,) to be the imaginary part, the delayed detection output is υ. = cosΔφ(tn) + j sinΔφ(1
n) (5) It can be treated as a complex number.

Figure 2 shows the delayed detection output υ on the complex plane. As an example of the signal point arrangement, the signal point arrangement of four-phase differential phase keying (QDPSK>) is shown.

In delayed detection, the detection output is a function of the phase difference Δφ(1,), so differential phase keying (DPSK), which expresses information by the phase difference Δφ(1,), is suitable as a modulation method. For example, in four-phase differential phase modulation, 2 bits (anSbn> and n
represents the th symbol.

The sign determination circuit 3 determines cos for the nth symbol.
Determine i=±1 based on the sign of Δφ(1,), and calculate sin△
=±1 is also determined depending on the sign of φ(1,).

For these judgment values, as well as for the differential detection output, u”
, ='a, +J also... ・- [6)
It is expressed as a complex number. This complex judgment value is output from the output terminal 4.

If the complex differential detection output υ contains a frequency drift component, use some method to find the compensation coefficient w, and on the complex plane, U, , = υ, × □r ・・−−−(7
), and the value U at this time. The sign can be determined by

In this embodiment, the delay circuit 5, the complex conjugate circuit 6, the complex multiplication circuit 7, and the moving average circuit 8 calculate the compensation coefficient wnI, and the complex multiplication circuit 9 calculates the equation (7).

The optimal value of the compensation coefficient wo' is the value that minimizes the mean square error of e, , =u, -u. This solution becomes. E
[ ] represents the average. In equation (8), the numerator is the complex judgment value U' output from the sign judgment circuit 3.

This corresponds to finding the average phase difference between the complex delay detection output vn output from the delay detection circuit 2, and the denominator corresponds to normalizing the value. For the denominator, On tJn”= (an +J bn) (ar+
Since J bj=a,,2 +bh2 −・・・−・・・(9), it becomes a constant value.

The configuration for calculating equation (8) will be explained.

The delay circuit 5 delays the complex delay detection output υ7 and synchronizes it with the complex judgment output U'. The complex conjugate circuit 6 obtains the complex conjugate υI of the complex delayed detection output υ by inverting the sign of the sine detection output. The complex multiplication circuit 7 calculates i7υ,°. The moving average circuit 8 averages the output of the complex multiplication circuit 7 by the following calculations and outputs the compensation coefficient WfiI. The calculation of the moving average circuit 8 is driven by a recovered clock having the same period T as the sign determination.

Here, as a simple example, the case of QDPSK will be explained.

When there is a frequency drift of Δf in the received phase modulated wave, the signal point at that time rotates by 2πΔfT as shown in FIG. T is the symbol length as described above. At this time, the delayed detection output υ, is υ, = (an+jbn)
exp(j2πΔfT)...αD. an and bh are data series of ±1.

In this case, the denominator of equation (8) is E[υ. u,,”] =E (a,2 +b,,”)
=2 − (2). Also, when the bit error rate is small, in most cases, 2,=ah % Sh = bh −-””
”-α, in = a,, + j b,, -・
・-α becomes one. Therefore, the numerator of formula (8) is E (
u', a,") = E C(a, +jb,) (an-jbn) exp
(-J2nΔfT))=E (a, 2 +bn")-
eXI](-j2nΔfT)=2-eXp(-j2
nΔfT) α, tnll” =exp(-j2nΔfT)
It becomes αO. (company) formula and 00 formula (7)
Substituting into the formula, ul,=a,+jbl.

Therefore, a delayed detection output without frequency drift can be obtained.

FIG. 3 is a block diagram of a differential detection demodulation circuit according to a second embodiment of the present invention.

In the first embodiment, when the frequency drift reaches a certain level, accurate drift correction cannot be performed. For example, Q
In the case of DPSK, if the frequency drift exceeds 1/8 of the symbol rate, a different code will be determined, and the system will operate to minimize the square error with that code.

This will be explained with reference to FIG. In the case of QDPSK, the signal point arrangement is (±1, ±j〉. For example, when the delayed detection output υ is in the first quadrant, 2, = 1
, B=1. However, if there is a carrier frequency drift, the signal point rotates by 2πΔfT. 12πΔ
When fTI>π/4, that is, Δfl>1/(8T), and Δf exceeds the symbol rate of 178, the differential detection output υ.

falls into the judgment area of another code, resulting in an incorrect correction coefficient being obtained. If the drift is smaller than 1/(8T), such a code error is small and a correct correction coefficient can be obtained.

The second embodiment enables accurate drift correction even when the frequency drift becomes large, and includes pattern detection circuits 11 to 14 as means for detecting a specific pattern included in the received phase modulated wave. A maximum value detection circuit 15 and a sign conversion circuit 16 are provided as means for correcting the phase uncertainty of the complex judgment output using the output of the means.

In digital communication, a synchronization word is transmitted at regular intervals, or in burst transmission, a synchronization word is transmitted at the beginning of a data burst. Since such a synchronization word signal has a specific pattern, phase uncertainty can be detected by detecting such a specific pattern.

For example, the symbol sequence of the synchronization word is α. Assume that +jβ7. At this time, the pattern detection circuits 11 to 14 detect four types of patterns α, +jβ9, jα, −β9, αo−jβ9, −jα, and +β7, and the maximum value detection circuit 15 determines the absolute value of which detected output. Detect if the value is maximum. α, +
If the detection output of the pattern jβ is maximum, it is 0 radian, and if the detection output of the pattern jα7−β9 is maximum, it is π.
/2 radian, -α, jβ, if the detection output of the pattern is maximum, π radian, -jα. +β. If the detection output of the pattern is the maximum, it means that the correction has been made with a deviation of 1 π/2 radian.

Therefore, the code conversion circuit 16 converts the complex judgment output u from the sign judgment circuit 3 into other complex codes U'','.Q
To explain the case of DPSK, ■ α. +jB0
When the pattern detection output is maximum, Uo,” (a r+
+ b,,) −ua′=(ko,,E),)■jα,
−β. t when the pattern detection output is maximum. =(λn=
b n ) -un' = (-'b n, Mi.) ■
−α1jβゎWhen the detection output of the pattern is maximum, Uo, =
(a,,,moj −un' =(-5°,-6,,)■
−jcX, +β, Uo when the pattern detection output is maximum
, = (2,, El,) -u',' = (S,, -S,). This will give you correct data.

In the above embodiment, an example was shown in which the output of the delay detection circuit 2 is processed by a separate circuit, but the present invention can be similarly implemented using a signal processing processor.

〔Effect of the invention〕

As explained above, the differential detection demodulation circuit of the present invention can correct the phase rotation of the differential detection output due to frequency drift, so even in the case of mobile communication using a frequency oscillator with low stability, it can be used even when there is no frequency drift. The effect is that similar transmission characteristics can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a differential detection demodulation circuit according to a first embodiment of the present invention. FIG. 2 is a diagram showing the signal point arrangement of QDPSK. FIG. 3 is a block diagram of a differential detection demodulation circuit according to a second embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Input terminal, 2... Delay detection circuit, 3... Sign determination circuit, 4... Output terminal, 5... Delay circuit, 6
...Complex conjugate circuit, 7.9...Complex multiplication circuit, 8.
. . . Moving average circuit, ■1 to 14 . . . Pattern detection circuit, 15 . . . Maximum value detection circuit, 16 . . . Code conversion circuit.

Claims (1)

[Claims] 1. A delay detection circuit that performs delay detection on a received phase modulated wave to generate a complex delay detection output in which the cosine delay detection output is regarded as a real number and the sine detection output as an imaginary number; In a differential detection demodulation circuit comprising a sign determination circuit that determines the sign of a real part and an imaginary part and generates a complex determination output, the amount of displacement on a complex plane between the complex differential detection output and the complex determination output is compensated. A differential detection demodulation circuit comprising: means for obtaining a complex compensation coefficient; and means for multiplying the complex differential detection output by the complex compensation coefficient.