JPH038140B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization circuit for a Viterbi decoder.

In digital communications, one of the methods for reducing transmission errors is a Viterbi decoder. The operation of the Viterbi decoder was reported in March 1973 by the U.S. I.I.
The paper described on pages 268 to 278 of Volume 61, No. 3 of Proceedings of the IEEE, published by IEEE. The Viterbi Algorithm
Algorithm).

In order to operate the Viterbi decoder, on the transmitting side, a transmission code is encoded using a predetermined method and then transmitted as a code word. On the receiving side, codewords are extracted in synchronization with the encoding on the transmitting side and input to the Viterbi decoder. Conventionally, a synchronization signal from an external system, such as a PCM frame synchronization signal, has been used for this synchronization. however,
This conventional method has a disadvantage in that the format of the synchronization signal differs from system to system, and therefore the synchronization circuit must be designed for each system. Furthermore, it has been difficult to apply the Viterbi decoder to systems where it is difficult to obtain a frame synchronization signal.

An object of the present invention is to eliminate the drawbacks of the conventional method and provide a synchronization circuit that can synchronize code words in the Viterbi decoder itself.

The configuration and operating principle of the present invention will be explained in detail below using the drawings.

FIG. 1 is a block diagram showing an embodiment of a Viterbi decoder to which an embodiment of the synchronization circuit of the present invention is added. The decoded signal input to the terminal 100 is applied to the decoded signal input terminal 104 of the Viterbi decoder 200 through the phase shifter 102 . A decoded signal is output to the terminal 101. The metric value of the Viterbi decoder 200 is input to the metric increment calculation circuit 20 of the synchronization circuit of the present invention. The metric increments are applied to an integrator 30 and integrated. The integrated output of the integrator 30 is applied to a threshold circuit 40, which outputs an identification signal when the integrated output becomes less than or more than a predetermined value. The control circuit 50 receives this identification signal and supplies a signal to the phase shift amount control terminal 103 of the phase shifter 10.

As shown in the example below, the transmission code for Viterbi decoding is such that for each information bit that is sequentially input to the transmitter, multiple bits that depend on multiple past information bits are sequentially output as output bits. A synchronization signal (hereinafter referred to as a single word synchronization signal) is applied to the terminal 102 to indicate the delimitation of the plurality of bits. The word synchronization signal is supplied to a Viterbi decoder 200 through a phase shifter 10 and output to a terminal 105.

A portion 200 surrounded by a broken line in FIG. 1 shows the basic configuration of a Viterbi decoder. Terminal 1
The decoded signal applied to 04 is applied to a branch metric calculator 201, and a metric increment is calculated for each possible branch. Adder 202 adds the metric increment for each branch to the metric value for each state read from metric store 204 . The branch selector 203 selects a branch showing a large metric for each state from the metric values of each branch inputted from the adder 202, supplies the selected metric to the metric storage 204, and also sends it to the synchronization circuit 20. Output. The branches selected by the branch selector 203 are stored in the path memory 205, and converged branches are output to the terminal 101.

FIG. 2 is a block diagram showing an example of an encoder for a Viterbi decoder, with a constraint length of 3 and a coding rate of 1/2.
2 shows a convolutional encoder. Digital signals applied to the terminal 301 are sequentially stored in shift registers 302 to 304 for each input signal. The outputs of the shift registers 302, 303, and 304 are applied to a first exclusive OR circuit 305, and its output is output to a terminal 306. shift register 302,
The output of 304 is applied to a second exclusive OR circuit 307, and its output is output to a terminal 308.
The signals at terminals 306 and 308 become convolutional codes.
This convolutional code may be transmitted as is as a two-column digital signal, or may be converted into a serial signal by a parallel serial converter 401 shown in the block diagram of FIG. 3 and then transmitted. Signals at terminals 306 and 308 in FIG. 2 are respectively applied to terminals 403 and 404 in FIG.
is output to.

Figures 4a, b, and c show how synchronization occurs when transmitted as a serial signal. A in the figure shows a signal applied to the terminal 301, and a new digital signal is applied every 2T. FIG. 3b shows a signal at the terminal 402 that has been convolutionally encoded and converted into a serial signal by the parallel/serial converter shown in FIG. Since the coding rate is 1/2, a digital signal is output every T.
On the receiving side, the signal b must be correctly applied to the Viterbi decoder as one word every 2T. If the boundaries of one word are shifted by T as shown in figure c, each word becomes (1', 2), (2', 3), etc., and the original words (1, 1'), (2, 2′) Because Viterbi decoding is performed using a word structure different from that of the following, correct decoding results cannot be obtained. In addition, the terminals 306, 3 in Figure 2
Even when 08 signals are transmitted in parallel, they are not correctly received by the pair (terminal 306, terminal 308) on the receiving side, and cannot be decoded correctly if the pair (terminal 308, terminal 306) is received.

In the embodiment of FIG. 1, when synchronization is started, the metric increment calculation circuit 20 calculates the maximum metric increment from the new metric value selected by the branch selection circuit 203. First, the maximum metric value is determined by the maximum metric determination circuit 21 which determines the maximum metric, and the difference from the maximum metric stored in the register 23 one time slot (2T) before is calculated by the subtracter 22. Since this value is the maximum metric increase, this value is output to the integrator 30. Thereafter, the contents of the maximum metric determination circuit 21 are transferred to the register 23 in preparation for the next calculation. The fact that synchronization can be determined by observing the increase in the maximum metric as in the present invention will be explained using a case where the signal-to-noise ratio is good as an example.

Figures 5a and 5b show trellis diagrams of the Viterbi decoder. FIG. 5a is an example of a trellis diagram in the case of synchronization, and FIG. 5b is an example of the trellis diagram in the case of non-synchronization.

In FIG. 5, black dots indicate the state with the maximum metric, and thick lines indicate the path selected with respect to the maximum metric. If synchronized, see Figure 5 a.
As shown in Figure 2, the trellis of paths regarding the maximum metric is continuous, and the maximum metric is the maximum value that the branch metric can take. On the other hand, if they are not synchronized, this is almost equivalent to a case where the error in the transmission path is 50%, and the maximum metric trellis may not be continuous, as shown in FIG. 5b. If the trellis is not continuous in this way, it means that the metric connected to the non-maximum metric becomes the maximum in the next time slot, and in this case, the amount of increase in the maximum metric value is equal to the maximum value of the branch metrics. It is often a smaller value. Also, if the trellis is continuous, the branch metric between them is not necessarily the maximum. Therefore, the amount of increase in the maximum metric when synchronized is large, and the amount of increase in the maximum metric when not synchronized is small. Therefore, if the output of the metric increment calculation circuit 20 is integrated by the integrator 30 and the fluctuation component is removed, synchronization or non-synchronization can be determined by the threshold circuit 40 having an appropriate threshold value. That is, in the threshold circuit 40, the threshold Vth
When the output of the integrating circuit is smaller than , the threshold circuit 40 outputs an identification signal. When the identification signal is output, the control circuit 50 outputs a phase shift signal to the phase shifter 10 to change the output phase of the phase shifter 10.

FIGS. 6 and 7 are block diagrams showing first and second embodiments of phase shifter 10, respectively.
In FIG. 6, the decoded signal at terminal 100 is transmitted to phase shift element 7.
01 and output to terminal 104. The word synchronization signal at terminal 102 is sent directly to terminal 10.
5, and the relative time relationship between the decoded signal and the word synchronization signal is adjusted. In Figure 7, terminal 100
The decoded signal of is output as is to the terminal 104,
The word synchronization signal at terminal 102 is phase-shifted by phase shift element 801 and output to terminal 105.

Although the above description has proceeded on the assumption that the signal to be decoded is a serial signal, there are cases where the Viterbi decoder receives parallel signals as input.

FIG. 8 is a block diagram showing an example of a phase shifter when the input signals to the Viterbi decoder are parallel.
Switch the signals of terminals 901 and 902 to switches 903 and 9
04, terminals 906 and 90 can be replaced.
Equivalent phase shifting can be performed by outputting to 7. The switching signal of the switch is applied to terminal 905.

In this embodiment, the increase in the maximum metric was explained as being determined by the metric increment calculation circuit 20, but when the increase in the maximum metric is large, the increases in other metrics are also large, so the increase in the maximum metric is not necessarily the same. It is not necessary to determine synchronization based on the amount; the same effect can be obtained by determining synchronization based on the amount of increase in the second largest metric, third largest metric, or generally the Nth largest metric. It is also clear that the time interval for calculating the increment may also be longer. Furthermore, if a certain value is subtracted from each metric value to prevent metric overflow, it is necessary to supply the metric value before subtraction to the metric increment calculation circuit in order to correctly calculate the amount of metric increase. There is.

Furthermore, although the present embodiment has been described as synchronizing with a convolutional code having a coding rate of 1/2, it is clear that the present invention can also be applied to cases of other coding rates. Furthermore, when an encoded signal is transmitted after being subjected to polyphase phase modulation, even if there is uncertainty in the carrier phase, the uncertainty in the carrier phase can be reduced by finding the carrier phase with a large increase in the metric. can be excluded.

As described above in detail, the Viterbi decoder synchronization circuit according to the present invention enables word synchronization in the Viterbi decoder itself without using a synchronization signal from an external system.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a synchronization circuit according to the present invention and a Viterbi decoder to which the same is added, Fig. 2 is a block diagram showing an example of a convolutional encoder, and Fig. 3 is a parallel-to-serial converter. FIGS. 4a, b, and c show input and output signals of the convolutional encoder, and FIGS. 5a and b show trellis diagrams of paths.
6 to 8 show examples of phase shifters, respectively. In the figure, 10 is a phase shifter, 20 is a metric increment calculation circuit, 30 is an integrator, 40 is a threshold circuit, and 50 is a metric increment calculation circuit.
1 represents a control circuit, and 103 represents a phase shift amount control terminal.

Claims (1)

[Claims] 1 A decoded signal input terminal, a first output terminal for decoded signals, and a second
A synchronous circuit for a Viterbi decoder having an output terminal, the phase shifter having a phase shift amount control terminal and changing the phase of a decoded signal input to a decoded signal input terminal of the Viterbi decoder; Input the metrics of each internal state output from the second output terminal of the decoder, count from the largest one to determine the Nth metric of a constant natural number, and calculate the difference between the Nth metric at different times. a metric increment calculation circuit; an integrator that receives the output of the metric increment calculation circuit; a threshold circuit that outputs an identification signal when the output of the integrator is above or below a predetermined value; and a control circuit for supplying a phase shift amount control signal to a phase shift amount control terminal of the phase shifter according to a signal.