JPH0376404A - Semiconductor device - Google Patents

Abstract

PURPOSE:To attain stable oscillation over a wide power voltage range with low power consumption by providing a switching circuit to an inverter section of an oscillation circuit and controlling the drive capability of the inverter section with a change in the power voltage or the time from the oscillation start. CONSTITUTION:In the case of a power supply voltage V>V3, only an output Q1 of a power voltage detection circuit 12 goes to 'H', and in the case of an elapsed time T>T4, only an output Y1 of a time detection circuit 14 goes to 'H' only an output X1 of a multiplexer 13 goes to H and only PMOS 9a and NMOS 11a are turned on. when the power supply voltage is decreased to be in the relation of V2<V<V3, an output Q2 of the detection circuit 12 goes to 'H' in addition to the, 'H' level of the output Q1 and outputs X1, X2 of the multiplexer 13 go to 'H' and PMOS 9a, 9b and NMOS 11a, 11b are turned on. Then since the relation of V>V3 exists at the oscillation start, only the output Q1 of the detection circuit 12 goes to 'H' and since the outputs Y1-Y4 of the time detection circuit 14 go to 'H' because of the relation of T<T1 and the outputs X1-X4 of the multiplexer 13 go to 'H'.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an oscillation circuit for a semiconductor device.

[Conventional technology]

FIG. 6 is a circuit diagram of an oscillation circuit of a conventional semiconductor device. In the figure, (1) is a P channel) L? MO5 field effect transistor (hereinafter referred to as PMO5), (21 is an N-channel MO8 field effect transistor (hereinafter referred to as NMO8), and this PMOS (1) and NMO3t21 form a CMOS inverter. (3) is a feedback resistor, (4) is the output resistance, (5) is the crystal oscillator, (6) is the input side oscillation capacitance,
(7) is the output side oscillation capacitance.

FIG. 7 is a circuit diagram of a conventional oscillation circuit composed of three stages of inverters, and has three stages of CMOS inverters of PMO8+11 and NMO3 (21).

Next, the operation will be explained.

When using the one-stage inverter amplifier circuit shown in Fig. 6, P
MOS (11) and NMO9 (21) are both ON for a long time, so there is a lot of through current, and therefore the oscillation consumption current is large. Figure 7 shows a circuit using a three-stage inverter amplifier circuit to compensate for this drawback. Since the drive capability of the crystal oscillator (5) is small, the through current is reduced, but since the gain in the amplification stage is too high, a parasitic CR oscillation is formed using the parasitic capacitance (151) as a feedback loop, and the resonance frequency deviates from the resonant frequency of the crystal oscillator (5). oscillates.

[Problem to be solved by the invention]

Since the oscillation circuit of the conventional semiconductor device was constructed as described above, there was a problem in that it was difficult to achieve stable oscillation with an accurate resonance frequency and low power consumption.

This invention was made to solve the above-mentioned problems, and its purpose is to provide a semiconductor device that can stably oscillate over a wide range of power supply voltages, prevent parasitic oscillations, and achieve low power consumption. shall be.

[Means to solve the problem]

In the semiconductor device according to the present invention, a switching circuit is provided in the inverter section of the oscillation circuit, and the driving capacity of the inverter section (
(hereinafter referred to as the mark) can be controlled by changes in the power supply voltage, time from the start of oscillation, etc.

[Effect]

The oscillation drive inverter of the oscillation circuit according to the present invention has a switching circuit, and by controlling the switching, GM is changed to obtain stable oscillation characteristics.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (8a) to (8d) are P-channel MO8 field effect transistors (J2 is referred to as lower PMO8) (9a
) to (9d) are 2MO5s that control (8a) to (8d), respectively, and (10a) to (10d) are N-channel MO8s.
Field effect transistor (hereinafter referred to as NMOS), (ll
a)-(11d) are NMOS (10a)-(
10d), a is a power supply voltage detection circuit that detects the power supply voltage, 0 is a multiplexer, and circle is a time detection circuit that detects the passage of time from the start of oscillation.

Next, the operation will be explained.

Considering a sufficiently stable state from the start of oscillation, since oscillation starts with a high power supply voltage: V > Vs (see Figure 3), the output of power supply voltage detection circuit 0 is only Ql 'H'.
% Also, elapsed time: T>T4 (see Figure 4), so the output of the time detection circuit (14) is only Yl becomes ``H#'', and the output of multiplexer 0 is only ``H'' of Xt,
PMOS (9a) and NMOS (lla) are turned on
#do. Now, here, NMOS (10a) and NMOS
The sum of GM of (lla) is βNl, similarly NMOS (1
0b) and NMOS (llb) as βN, NMOS (1
0c) and NMOS (llc) as βN3, NMOS (10
d) and NMOS (lid) as βN Also, (8a) and (9
The sum of GM in d) is βP0, similarly (8b) and (9b) are βp, , PMOS (8c) and E'MO8 (9C) are βPs, PMOS (8d) and PMOS (9d) are β
P4, the GM of the oscillation inverter section at this time is
is βN1 on the N channel side and βP on the P channel side! becomes.

Here, when the power supply voltage drops to Vl<V<V3, the output of the power supply voltage detection circuit O2 becomes not only Ql but also Q2. Therefore, the output of multiplexer [3 is
S (lla).

(llb) does 4QN#. At this time, the GM on the N channel side is βN + βN - P channel side force (βP1 + β1.
So, 2 The GM of the inverter increases due to the voltage drop. Similarly, when Vl<V<Vl, βN, +βN2+βN, (Cc
h side).

βP1+βP2+βp, (Pch side), when V<Vl, βN1+βN.

+βN, +βN4 (Nch side), βP1+βP2+βP
, +βP4 (Pch side).

Next, consider the passage of time. At the start of oscillation, V>Vs
Therefore, the output of the power supply voltage detection circuit (13 is 4H# only for Ql)
, the output of the time detection circuit αω becomes Y1 to Y4 'H' because Tl (see Figure 4), and the multiplexer a
The output of 3 is 'H#' for xl to x4. Therefore, the GM of the inverter section is βN, +βN2 + βN3 + βN4 (Nc
h side), βP, +βP, +βP3+βp, (Pch side). Similarly, when T1<T<'h, βN1+
βN2+βN5 (Nch side), βP1+βP, +βp,
(Pch side), T2 (T (T's when βN, +βN
2 (Nch side), βP1 + βp2 (Pch side), T)T
βN when s.

(Nch side) and βp1 (Pch side), and as the oscillation stabilizes over time, the GM will decrease.

Although the above embodiment shows the case where the multiplexer (13) is used to control the switching of the inverter section, the switching circuit is configured as shown in FIG. 5 without the multiplexer.

Direct control using the output from the detection circuit also produces similar effects.

〔Effect of the invention〕

As described above, according to the present invention, since the driving ability of the oscillation section is controlled depending on the state of the semiconductor device, stable oscillation can be obtained over a wide power supply voltage range with low power consumption. This has the effect of improving performance.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an oscillation circuit of a semiconductor device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the configuration of multiplexer α3 of FIG. 1, and FIG. 3 is an illustration of the power supply voltage detection circuit of FIG. 4 is a graph showing the relationship between the input and output of the time detection circuit (141) of FIG. 1; FIG. 5 is a circuit diagram of the oscillation circuit showing the embodiment of this invention; Fig. 6 is a circuit diagram of an oscillation circuit of a conventional semiconductor device, and Fig. 7 is a circuit diagram of a conventional oscillation circuit configured with a three-stage inverter.In the figure, (3) is a feedback resistor, and (4) is a Output resistance, (5) is crystal oscillator, (6) is input side oscillation capacitance, (
7) is the output side oscillation capacitor, (8a) to (8d) are PMO8
, (9a) to (9d) are PMO9(8a) to (9d), respectively.
8d) is controlled by PMO8, (10a) to (10d) are NMOS, and (lla) to (lid) are each NMO3.
(10a) to (10d), α is a power supply voltage detection circuit, (1 is a multiplexer, Q41 is a time detection circuit that detects the passage of time from the start of oscillation, (1
Reference numeral 61 indicates a NOR gate constituting a multiplexer. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In an oscillation circuit of a semiconductor device, a plurality of switching transistors connected in series to a drive transistor,
“ON” and “OF” of this switching transistor
In order to control F'', a detection section is provided that generates signals corresponding to changes in power supply voltage, oscillation start, oscillation stop, and steady oscillation state, and the drive capacity of the oscillation inverter section is controlled by the signal generated from the detection section. A semiconductor device characterized by being able to operate stably at all times through controlled operation.