JPH0374984B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a received signal processing device that receives and processes, by majority vote, repeated digital signals of the same information sent from a transmitting side by a radio.

(Prior art) A method of repeatedly transmitting the same information and correcting errors by majority voting on the receiving side to increase the reliability of the information is the easiest method to process compared to other error correction methods. It is used. An important issue with this majority decision method is how to detect errors.

Conventional error detection methods include determining whether the same pattern is repeated and, if they match, recognizing the received signal as correct and processing it, and another method of determining the transmission quality of the signal. There is a method of determining the electric field strength of the received signal and performing majority voting if it is at a sufficient level.

(Problems to be Solved by the Invention) However, in each case, there were the following problems, and the results were not necessarily satisfactory.

First, in the former method, when the error rate is very low, for example, when the bit error rate is 10 ^-2 or higher and one information pattern has 50 to 100 bits, the probability of recognizing the received signal as correct decreases rapidly. ,
The probability of not detecting a signal, that is, the non-detection rate increases.

In addition, in the latter method, for example, when there is an interference wave, it is determined that the electric field is sufficient, so it is impossible to detect errors even when there are errors in the signal, and changes in environmental conditions such as temperature may cause errors. However, since the correspondence between the measured value of electric field information and the bit error rate of the received digital signal is not always constant, there are disadvantages such as deviations occurring, making it impossible to obtain satisfactory signal deterioration information. Nakatsuta.

The purpose of the present invention is to achieve a very high probability of false detection.
An object of the present invention is to provide a received signal processing device based on the principle of majority voting.

(Means for Solving the Problems) In order to achieve the above object, a received signal processing device according to the present invention includes a start pattern detection circuit that detects a start pattern added prior to repeatedly transmitting M information patterns. and information pattern receiving means for receiving the M information patterns in synchronization with the time point when the start pattern is detected by the start pattern detection circuit, and storing the M information patterns received by the information pattern receiving means. a memory circuit that performs a majority decision on each bit representing the same information among the M information patterns stored in the memory circuit, and finally decides on one pattern; a mismatch number addition circuit that calculates and adds the number of bits that are mismatched between the pattern and each of the M information patterns stored in the storage circuit;
a determination circuit that determines that the pattern determined by the majority circuit can be processed when the addition result by the mismatch addition circuit is smaller than a predetermined value; and a signal processing means for processing the determined pattern.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a received signal processing device according to the present invention. FIG. 2 is a diagram showing a signal format for explaining the embodiment of FIG. 1.

In the figure, part A is the transmitting side, and part B is the receiving side. A predetermined digital signal created on the transmitting side is transmitted by a transmitter 13 and received by a receiver 17. On the transmitting side, the signal generator 10 generates K-bit information patterns ^A =a ¹ , a ² .
Repeatedly send M pieces (M≧2). Reference numeral 14 denotes a start pattern generating section, which generates a start pattern ST= with fixed R bits under the control of the control section 16.
Output S ¹ , S ² . . . S ^R before information patterns A, A . . . A. The outputs of the signal generating section 10 and the start pattern generating section 14 are combined by a combining circuit 11,
Start pattern ST is information pattern A, A...A
The information signal sequence _X11 added before is output.

Figures 2a and 2b show the format of this information signal sequence _X11 .

15 is a random number generator that generates random number X ₁₅ ,
The random number X ₁₅ and the information signal sequence X ₁₁ are added by the adder 12 under the control of the control section 16 .

The output of the adder 12 is then transmitted from the transmitter 13.

Note that the reason why random numbers are added to the information signal sequence _X11 here is as follows. That is, since X ₁₁ is a repetition of the same pattern A, the low frequency component fluctuates synchronously, and if inputted as is to the transmitter 13, it would adversely affect the modulation characteristics.
Therefore, the random number X ₁₅ is X ₁₁ repeating pattern A,
A...Added to A.

Reference numeral 16 denotes a control unit, which, as described above, performs time control such as generation of a signal in the signal generation unit 10, generation of a start pattern in the start pattern generation unit 14, generation of random numbers in the random number generator 15, and transmission control of the transmitter 13. is being carried out.

Next, the configuration and operation of the receiving side will be explained.

Regarding the signal X ₁₇ received by the receiver 17,
A detection circuit 1 detects a start pattern for ST.

In synchronization with the detection of the start pattern, the information pattern receiving means 2 receives subsequent information patterns.

The information pattern receiving means 2 includes a random number generator 18 that generates a random number X ₁₈ that is the same as the random number X ₁₅ on the transmitting side, an adder 19, and a serial-parallel conversion circuit 20, and is capable of adding the receiver output X ₁₇ and the random number X ₁₈ . The signal string corresponding to the transmitting side _X11 is then reproduced, and then the reproduced serial information is converted into parallel information by the conversion circuit 20, thereby facilitating the next stage of processing.

Here, the playback information output from the adder 19
Let me explain about _X19 .

In Fig. 2, c and d are playback information _X19 ,
Since the start pattern ST and the M information patterns A, A...A on the transmitting side contain errors due to noise in the transmission path, they are different from each other in this way.
ST ₁ , A ₁ , A ₂ ... has changed to _AM .

Here, ST ₁ =S ¹ ₁ , S ² ₁ ...S ^R ₁ A _n =a ¹ _n , a ² _n ...a ^K _n (m=1, 2, ..., M), respectively.

In each pattern, if no error occurs in the transmission path, each bit is S ¹ ₁ , S ² ₁ ...S ^R ₁ = S ¹ , S ² ...S ^R a ¹ _n , a ² _n ...a ^K _n = a ¹ , a ² …a ^K
(m=1, 2, . . . , M) Therefore, ST ₁ =ST A _n =A (m = 1, 2, . . . , M) holds true.

The output received by the information pattern receiving means 2 and converted into parallel information is stored in the recording circuit 3.
The contents of the recording circuit 3 are A ₁ , A ₂ , . . . , _AM .
The contents of this recording circuit 3 are read out, and a majority decision circuit 4 makes a majority decision for each bit representing the same information in A ₁ , A ₂ , ..., _AM .
Two patterns D=d ¹ , d ² . . . d ^K are determined.

For example, d ^K is the result of taking a majority vote among a ^K ₁ , a ^K ₂ , ..., a ^K _M , and the number of 1s among a ^K ₁ , a ^K ₂ , ..., a ^K _M is greater than the number of 0s. If there are many, d ^K =1.

Pattern D determined by majority vote (Figure 2 f)
The quality of is measured by the following mismatch number adding circuit 5.

Letting the number of bits that do not match between pattern D and pattern A _n be e _n (m = 1, 2, ..., M), the mismatch number adding circuit 5 calculates E = e ₁ + e ₂ + ... + e _M. (Figure 2e).

This means that the larger E is, the more errors occur in the transmission path, and the quality of D is worse. A determination circuit 6 determines whether or not the calculation result E of the mismatch number adding circuit 5 is smaller than a predetermined value ρ. If it is determined that E<ρ, D is considered suitable for signal processing and can be processed by the signal processing means 9.

On the other hand, the pattern D determined by the majority circuit 14 is checked by the parity check circuit 7. In this method, a parity check bit is included in the information pattern A in advance, and the receiving side performs a parity check on the majority result D.

When the parity check circuit 7 determines that the signal is normal and the determination circuit 6 determines that processing is possible, the signal processing section 8 performs pattern D processing.

The parity check of pattern D has a very large error detection effect because the error rate of each bit constituting D is small.

(Effects of the Invention) As explained above, the device according to the present invention has the following features:
The signal pattern D with the lowest error rate is determined by performing majority voting processing, and the number of bits that are inconsistent with each of the repeatedly received patterns A ₁ , A ₂ , ..., _AM is counted, and the value is determined as a predetermined value. When it is smaller than the value, signal pattern D can be processed. That is, D is processed by equivalently measuring the bit error rate of the transmission path using D as a reference. In this method, the higher the number of bits in pattern A, the more accurately the bit error rate can be measured, which has the effect of alleviating the drawback of the conventional method in which the non-detection rate increases as the number of bits increases.

Circuits 3 to 8 in FIG. 1 can be easily created by installing the respective functions (software) on a microcomputer. Also, circuits 1 and 2 can all be realized with digital circuits, so
It is easy to convert into an IC, and is suitable for miniaturization and economicalization.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a received signal processing apparatus according to the present invention, and FIG. 2 is a diagram showing signal formats in each circuit section of FIG. 1. DESCRIPTION OF SYMBOLS 1...Start pattern detection circuit, 2...Information pattern receiving means, 3...Storage circuit, 4...Majority circuit, 5...Disagreement number addition circuit, 6...Determination circuit, 7...Parity check circuit, 8...Signal processing unit, 9...Signal processing means, 10...Signal generation unit, 11...Synthesizing circuit, 12...Adder, 13...
...Transmitter, 14...Start pattern generator, 1
5...Random number generator, 16...Control unit, 17...Receiver, 18...Random number generator, 19...Adder, 2
0...SP converter.

Claims (1)

[Claims] 1. A start pattern detection circuit that detects a start pattern added prior to repeatedly transmitting M information patterns, and a start pattern detection circuit that detects a start pattern added in advance of repeatedly transmitting M information patterns; information pattern receiving means for receiving the M information patterns, a storage circuit for storing the M information patterns received by the information pattern receiving means, and the M information patterns stored in the storage circuit; a majority circuit that performs a majority vote on each bit representing the same information and finally determines one pattern;
A mismatch number addition circuit calculates and adds up the number of bits that are inconsistent with each of the information patterns, and when the addition result by the mismatch number addition circuit is smaller than a predetermined value, the pattern determined by the majority decision circuit can be processed. 1. A received signal processing device comprising: a determination circuit that determines that there is a pattern; and a signal processing means that processes the pattern determined by the majority circuit when the determination circuit determines that the pattern can be processed. 2. The information pattern has a parity bit added thereto, and the signal processing means includes a parity check circuit that performs a parity check on the pattern determined by the majority circuit, and a parity check circuit that performs a parity check on the pattern determined by the majority circuit, and a parity bit when the pattern is determined to be processable by the judgment circuit. and a signal processing section that performs signal processing based on the pattern determined by the majority circuit when the result of the parity check in the parity check circuit is determined to be normal. A received signal processing device according to claim 1.