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JPH0372680A - Semiconductor material, photoelectric integrated circuit element, and crystal growth method of material - Google Patents

Semiconductor material, photoelectric integrated circuit element, and crystal growth method of material

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Publication number
JPH0372680A
JPH0372680A JP2059442A JP5944290A JPH0372680A JP H0372680 A JPH0372680 A JP H0372680A JP 2059442 A JP2059442 A JP 2059442A JP 5944290 A JP5944290 A JP 5944290A JP H0372680 A JPH0372680 A JP H0372680A
Authority
JP
Japan
Prior art keywords
substrate
crystal layer
gaas
inp
semiconductor material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2059442A
Other languages
Japanese (ja)
Inventor
Shinichi Watabe
信一 渡部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Cable Industries Ltd
Original Assignee
Mitsubishi Cable Industries Ltd
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Filing date
Publication date
Application filed by Mitsubishi Cable Industries Ltd filed Critical Mitsubishi Cable Industries Ltd
Publication of JPH0372680A publication Critical patent/JPH0372680A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain semiconductor material wherein a GaAs or InP crystal layer of high quality is formed on an Si substrate, by arranging, directly or via a buffer layer, an Si or Si-Ge crystal layer on a GaAs or InP substrate. CONSTITUTION:GaAs based semiconductor material is formed as follows; an Si buffer layer 2 for lattice matching is formed on a GaAs substrate 1 by MOCJD and the like, and an Si crystal layer 3 is epitaxially grown on the buffer layer 2 by yo-yo solute supplying method. When a semiconductor device is constituted from said semiconductor material, the Si crystal layer 3 is used as an Si substrate, and the GaAs substrate 1 is used as a GaAs crystal layer. InP based semiconductor material is formed as follows; an Si buffer layer 2 is formed on an InP substrate 1, and further an Si crystal layer 3 is epitaxially grown by yo-yo solute supplying method. When a semiconductor device is made also from said material, an inverse mode is applied wherein the Si crystal layer 3 is used as an Si substrate, and the InP substrate 1 is used as an InP crystal layer.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、GaAsまたi;l:InP払板上板上iま
たはSiGe(以下、単にSlという)結晶層を設けた
半導体材料、当該材料上に光素子と電子素子を集積した
光電子集積回路素子、並びに材料の結晶成長法に関する
Detailed Description of the Invention [Industrial Application Field] The present invention relates to a semiconductor material provided with a GaAs, i;l:InP or SiGe (hereinafter simply referred to as Sl) crystal layer on a top plate; The present invention relates to an optoelectronic integrated circuit device on which an optical device and an electronic device are integrated, and a crystal growth method of the material.

〔従来の技術〕[Conventional technology]

■−V族二元合金の化合物半導体利料の代表であるGa
AsまたはInPは、レーザダイオード、発光ダイオー
ド、ICなど、実に様々な半導体デバイスとして製品化
または開発が進められている。
■-Ga, which is a representative compound semiconductor material for group V binary alloys
As or InP is being commercialized or developed as a wide variety of semiconductor devices such as laser diodes, light emitting diodes, and ICs.

例えばGaAsを用いたデバイスとして、第4図に示す
如<Si基板51上にGaAs結晶層53を成長させた
半導体材料が提供されている。なお、Si基板51とG
aAs結晶層53との間には格子定数の不整合を緩和す
るためにバッファ層52を介在させることがある。
For example, as a device using GaAs, a semiconductor material is provided in which a GaAs crystal layer 53 is grown on a Si substrate 51 as shown in FIG. Note that the Si substrate 51 and G
A buffer layer 52 may be interposed between the aAs crystal layer 53 and the aAs crystal layer 53 in order to alleviate lattice constant mismatch.

InPの場合も同様に第4図に示すように、Si基板5
1上に直接もしくはバッファ層52を介してInP結晶
層53を成長させた半導体材料が提供されている。
In the case of InP, as shown in FIG.
A semiconductor material is provided in which an InP crystal layer 53 is grown directly or through a buffer layer 52 on the semiconductor material.

この神の半導体材料上、土にG a /l s系また4
:1lnP系太陽電池を始めとする各種デバイスに採用
されているが、デバイスの一層の性能向上のためにはG
aAsまたはInP結晶が高品質であることが望ましい
On this divine semiconductor material, there is also a Ga/l s system in the soil.
: It is used in various devices including 1lnP solar cells, but in order to further improve device performance, G
It is desirable that the aAs or InP crystal be of high quality.

特に、最近は高度情報化社会において光通信システムの
大機能化、高性能化が益々重要性を帯びてきており、特
に光通信システムに有望視されている光電子集積回路素
子(OBIC)においても高品質GaAsまたはInP
結晶が必要とされる。
In particular, in recent years, in the highly information-oriented society, it has become increasingly important to increase the functionality and performance of optical communication systems, and optoelectronic integrated circuit devices (OBICs), which are seen as promising for optical communication systems, are also becoming more and more highly functional. Quality GaAs or InP
Crystals are required.

0EICは、受光素子や発光素子などの光素子と電界効
果トランジスタなどの電子素子とを半導体基板上にモノ
リシンク集積したものである。例えば、光通信システム
における中継器は、光信号を受光素子で電気信号に変換
し、電気信号を電子素子により増幅・整形処理し、処理
された電気信号を発光素子に印加し、そこで光信号に再
度変換する機能を有する。−船釣に、モノリシンク集積
することにより、大機能化、高性能化、低価格化を実現
できる。0RICの高度化を達成するための一つの重要
な要素として、0Etc用基板及び光素子用エピタキシ
ャル膜を高品質化することである。
An 0EIC is one in which optical elements such as a light receiving element and a light emitting element, and electronic elements such as a field effect transistor are monolithically integrated on a semiconductor substrate. For example, a repeater in an optical communication system converts an optical signal into an electrical signal using a light-receiving element, amplifies and shapes the electrical signal using an electronic element, applies the processed electrical signal to a light-emitting element, and converts it into an optical signal. Has the ability to convert again. - By integrating monolithic in boat fishing, it is possible to achieve greater functionality, higher performance, and lower costs. One important element for achieving higher levels of 0RIC is to improve the quality of the 0Etc substrate and the epitaxial film for optical devices.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記第4図に示す如き構造のGaAs系半導体材料では
、GaAs結晶層53は通常はMOVPEなどによって
エピタキシャル成長させており、さらにGaAsの結晶
性向上を計るためSi基板51とGaAs結晶層53と
の間に歪超格子などのバッファ層52を介しているが、
現在のところSi基板に対するGaAs結晶層のエッチ
ピット密度(EPD)は106/cJ程度であり、在来
のMOVPEなどではGaAs結晶層の高品質化には限
度がある。
In the GaAs-based semiconductor material having the structure shown in FIG. Although a buffer layer 52 such as a strained superlattice is interposed,
At present, the etch pit density (EPD) of a GaAs crystal layer with respect to a Si substrate is about 106/cJ, and there is a limit to the high quality of the GaAs crystal layer using conventional MOVPE.

上記の事柄はInPの場合にも当て嵌まり、Si基板に
対するInP結晶層のEPDは106/cJ程度である
The above also applies to the case of InP, and the EPD of an InP crystal layer with respect to a Si substrate is about 106/cJ.

先にも述べたように、0EICを始めとする半導体デバ
イスの高性能化には結晶の高品質化が不可欠であり、換
言するとEPDの数値を低減すること(少なくとも10
’/c−+i程度以下)が必要であり、これに基づきよ
り一層高品質なGaAsまたはInP結晶層を得る試み
がなされているのが現状である。
As mentioned earlier, it is essential to improve the quality of the crystal to improve the performance of semiconductor devices such as 0EIC.In other words, it is essential to reduce the EPD value (at least 10
'/c-+i or less), and based on this, attempts are currently being made to obtain even higher quality GaAs or InP crystal layers.

従って、本発明の目的は、Si基板上に高品質のGaA
sまたはInP結晶層を設けた半導体材料、当該材料を
用いて作製したOBIC1並びに前記材料の結晶成長法
を提供することにある。
Therefore, the object of the present invention is to produce high quality GaA on a Si substrate.
An object of the present invention is to provide a semiconductor material provided with a S or InP crystal layer, an OBIC 1 manufactured using the material, and a method for growing crystals of the material.

〔課題を解決するための手段〕[Means to solve the problem]

本発明者らは、Si基板上に対して高品質なGaAsま
たはTnP結晶層を得るべく、種々の検討を重ねた結果
、通常のMOVPEなとの薄膜結晶成長技術によるGa
AsまたはInP結晶層の高品質化には限度があるが、
GaAsまたはInP基板には高品質結晶のもの(Ga
As基板: EPD=I O’ /cd程度以下、In
P基板:EPD=IO:I/C−程度以下)が既に提供
されており、この高品質なGaAsまたは1nP結晶基
板を結晶層として使用すれば、結果としてGaAsまた
はInP結晶層の高品質化になるではないかということ
に先ず着眼した。
In order to obtain a high-quality GaAs or TnP crystal layer on a Si substrate, the present inventors have conducted various studies and found that GaAs or TnP crystal layers can be grown using thin film crystal growth techniques such as ordinary MOVPE.
Although there is a limit to the quality improvement of As or InP crystal layers,
GaAs or InP substrates are made of high quality crystals (Ga
As substrate: EPD=IO'/cd or less, In
P substrate:EPD=IO:I/C-) is already available, and if this high quality GaAs or 1nP crystal substrate is used as a crystal layer, it will result in high quality GaAs or InP crystal layer. The first thing I focused on was whether it would be possible.

この観点に基づき、本発明者らは、従来のSi基板上に
GaAsまたはlnP結晶層を設けるのとは逆に、Ga
AsまたはInP基板(特に高品質単結晶基板)上にS
iまたは5tGe(以下、単にSiという)結晶層を成
長させ〔必要ならばバッファ層を両者間に入れる(第1
図参照) ) 、GaAs系またはInP系半導体デバ
イスとしては作製された半導体材料を逆様にして使用す
ればいいこと、すなわちGaAs系ではSi結晶層をS
i基板、GaAs基板をGaAs結晶層として、InP
系ではSi結晶層をSi基板、InP基板をInP結晶
層として用いることを着想した。
Based on this viewpoint, the present inventors proposed that, contrary to providing a GaAs or lnP crystal layer on a conventional Si substrate,
S on As or InP substrate (especially high quality single crystal substrate)
i or 5tGe (hereinafter simply referred to as Si) crystal layer [if necessary, insert a buffer layer between the two (first
), for GaAs-based or InP-based semiconductor devices, the fabricated semiconductor material can be used upside down; in other words, for GaAs-based devices, the Si crystal layer is
i-substrate, GaAs substrate as GaAs crystal layer, InP
In the system, the idea was to use a Si crystal layer as a Si substrate and an InP substrate as an InP crystal layer.

ところで、半導体デバイスを作製する際に基板は一般に
は最低でも200μm程度以上の厚さが必要であり、S
i結晶層をSi基板とするにはSi結晶層を少なくとも
その厚さまで成長さセる必要がある。しかしながら、G
aAsまたはInP基板上にSi結晶層を成長させるの
に通常のVPE、LPEなどを用いた場合、厚さは高々
数十ミクロン程度が限度であり、それ以上にSr結晶層
を厚くするのは至極困難である。そのため、GaAsま
たはInP基板上にSi結晶層を成長させても、Si結
晶層を基板として用いるには無理がある。
By the way, when manufacturing semiconductor devices, the substrate generally needs to have a thickness of at least about 200 μm or more, and S
In order to use the Si substrate as the i-crystal layer, it is necessary to grow the Si crystal layer to at least that thickness. However, G
When ordinary VPE, LPE, etc. are used to grow a Si crystal layer on an aAs or InP substrate, the thickness is limited to a few tens of microns at most, and it is extremely difficult to make the Sr crystal layer thicker than that. Have difficulty. Therefore, even if a Si crystal layer is grown on a GaAs or InP substrate, it is difficult to use the Si crystal layer as a substrate.

そこで、本発明者らはさらに鋭意研究に勤しんだ結果、
GaAsまたはInP基板上にSi結晶層をy。
Therefore, as a result of further intensive research, the present inventors found that
A Si crystal layer is placed on a GaAs or InP substrate.

yO溶質供給法(詳細は後述する)によってエピタキシ
ャル成長させれば、Si結晶層を少なくとも200μm
程度以上と厚く形成でき、Si結晶層をSi基板として
使用することが可能となり、高品質な単結晶GaAsま
たはInP基板をそのまま高品質なGaAsまたはIn
P結晶層に転換できることを見出し、本発明を完成する
に至った。
If epitaxial growth is performed using the yO solute supply method (details will be described later), the Si crystal layer will be at least 200 μm thick.
This makes it possible to use a Si crystal layer as a Si substrate.
It was discovered that it could be converted to a P crystal layer, and the present invention was completed.

すなわち、本発明は、GaAsまたはInP基板上に直
接もしくはバッファ層を介してSi結晶層を設けた半導
体材料、当該半導体材料上に光素子と電子素子を集積し
た光電子集積回路素子(OBIC)、並びにGaAsま
たはInP基板上に直接もしくはバッファ層を成長させ
た後にyo−yo溶質供給法を用いてSi結晶層を成長
させる半導体材料の結晶成長法である。
That is, the present invention relates to a semiconductor material in which a Si crystal layer is provided directly or via a buffer layer on a GaAs or InP substrate, an optoelectronic integrated circuit element (OBIC) in which an optical element and an electronic element are integrated on the semiconductor material, and This is a crystal growth method for semiconductor materials in which a Si crystal layer is grown using a yo-yo solute supply method either directly on a GaAs or InP substrate or after growing a buffer layer.

本発明では、GaAsまたはInP基板に対してy。In the present invention, y for GaAs or InP substrates.

yO溶質供給法を用いることでSi結晶層を厚く(20
0μm程度以上)形威できるようになったわけで、Si
結晶層をSi基板、GaAsまたはInP基板をGaA
sまたはInP結晶層として使用することで、0BIC
や半導体デバイスの高品質化を実現できる。特に、本発
明の半導体材料を用いて作製したOBICは、当該材料
上に集積させる電子素子(FETなと)のSi系LSI
作製プロセス及び光素子(LD、フォトダイオードなど
)の作製プロセスをそのまま利用でき、0EICの実現
が容易である。
By using the yO solute supply method, the Si crystal layer can be made thick (20
This means that Si
The crystal layer is a Si substrate, and the GaAs or InP substrate is a GaA substrate.
0BIC by using it as S or InP crystal layer
It is possible to achieve higher quality of semiconductor devices. In particular, the OBIC manufactured using the semiconductor material of the present invention is a Si-based LSI with electronic elements (FET etc.) integrated on the material.
The manufacturing process and the manufacturing process of optical elements (LD, photodiode, etc.) can be used as they are, making it easy to realize 0EIC.

しかして、yo−yo溶質供給法は、その具体的詳細は
以下の実施例で述べるが、「発光素子用材料およびその
製作方法」 (特開昭63−81989M公報、特願昭
61−226275号)に開示の製作方法のことであり
、重力場と溶液の比重が溶液中に含まれる溶質の濃度に
依存することを利用したものであり、所望の結晶成長層
(本発明ではSi結晶層)を得るのに温度を周期的に上
下させることからそう命名されたのである。
The specific details of the yo-yo solute supply method will be described in the examples below, but the method is described in "Materials for Light-emitting Elements and Manufacturing Methods Therefor" (Japanese Patent Laid-Open No. 63-81989M, Japanese Patent Application No. 61-226275). ), which utilizes the fact that the gravitational field and the specific gravity of the solution depend on the concentration of solute contained in the solution, to form a desired crystal growth layer (Si crystal layer in the present invention). The name comes from the fact that the temperature is raised and lowered periodically to achieve this.

このyo−yo溶質供給法によるSi結晶層の成長につ
いて略述すると、GaAsまたはInP 5板を上方に
、原料となるSi多結晶を下方に配置し、その間をSi
より比重が大きい溶媒(例えばIn、 Sn、またはB
iなど)にSiを飽和させた溶液で満たす。さらに、温
度を周期的に上下させることで、下方のSi多結晶が溶
液中に供給され、GaAsまたはInP基板側にはSi
結晶層が成長することになる。
To briefly describe the growth of a Si crystal layer using this yo-yo solute supply method, a GaAs or InP 5 plate is placed above and a raw material Si polycrystal below.
Solvents with higher specific gravity (e.g. In, Sn, or B
(e.g.) is filled with a solution saturated with Si. Furthermore, by periodically raising and lowering the temperature, the lower Si polycrystals are supplied into the solution, and the GaAs or InP substrate side is provided with Si polycrystals.
A crystal layer will grow.

なお、yo−yo溶質供給法でGaAsまたはInP基
板上にSi結晶層を成長させるに当たり、GaAsまた
はInP基板のメルトバックを防ぐ場合、または格子不
整合を緩和した方がよい場合には、MOCVD、MBE
、VPEなどによってバッファ層を設けておくことが好
ましい。この場合のバッファ層は、SiSSi −Ge
、 GaAsでもよいし、それ以外の材料でもよい。
When growing a Si crystal layer on a GaAs or InP substrate using the yo-yo solute supply method, MOCVD, M.B.E.
It is preferable to provide a buffer layer using , VPE, or the like. The buffer layer in this case is SiSSi-Ge
, GaAs, or other materials may be used.

〔実施例〕〔Example〕

以下、本発明の半導体材料、0EIC1並びに材料の結
晶成長法を実施例に基づいて詳細に説明する。
Hereinafter, the semiconductor material of the present invention, 0EIC1, and the crystal growth method of the material will be explained in detail based on Examples.

GaAs系半導体材料は、第1図に示すように、GaA
s基板1上に格子整合のためのStバッファ層2をMO
CVDなどにて形威し、バッファ層2上にSi結晶層3
をyo−yo溶質供給法によりエピタキシャル成長させ
たものである。
GaAs-based semiconductor materials are GaAs-based semiconductor materials, as shown in FIG.
A St buffer layer 2 for lattice matching is formed on a MO substrate 1.
Formed by CVD etc., a Si crystal layer 3 is formed on the buffer layer 2.
was epitaxially grown using the yo-yo solute supply method.

かかる半導体材料は、半導体デバイス化には第4図に示
す従来の材料のように、Si結晶層3をSi基板、Ga
As基板lをGaAs結晶層として用いることは、前述
した通りである。特に、GaAs基板として高品質単結
晶基板を用いれば、当該基板が高品質結晶層となるので
、結果的に高品質なGaAs結晶層が得られたのと同し
になる。
Such a semiconductor material is used to fabricate a semiconductor device by forming the Si crystal layer 3 on a Si substrate or a Ga substrate, as in the conventional material shown in FIG.
As described above, the As substrate 1 is used as the GaAs crystal layer. In particular, if a high-quality single-crystal substrate is used as the GaAs substrate, the substrate will become a high-quality crystal layer, and the result will be the same as a high-quality GaAs crystal layer.

InP系半導体材料は、第1図において、InP基板1
上にStバッファ層2を設け、さらにSi結晶層3をy
o−yo溶質供給法によりエピタキシャル成長させたも
のである。当該材料もデバイス化に際しては、Si結晶
層3をSi基板、InP基板1をInP結晶層として逆
様にして供する。
InP-based semiconductor material is an InP substrate 1 in FIG.
A St buffer layer 2 is provided on top, and a Si crystal layer 3 is provided on top.
This was epitaxially grown using the o-yo solute supply method. When this material is made into a device, the Si crystal layer 3 is used as a Si substrate and the InP substrate 1 is used as an InP crystal layer in an inverted manner.

しかして、第1図に示した構造を有するGaAs系半導
体材料の結晶成長法は、yo−yo溶質供給法を用いて
次の如く行う。
The crystal growth method of the GaAs-based semiconductor material having the structure shown in FIG. 1 is carried out as follows using the yo-yo solute supply method.

まず、基板には現在市販されている高品質n型GaAs
基板(EPD= 10″/c+fl程度)を用い、これ
に気相成長(MOVPE、MBEまたはVPE)でバッ
ファ層を成長させる。バッファ層には、MOVPE、M
BE法による歪超格子構造または通常のVPE法による
Si薄膜を用いる。
First, the substrate is made of high-quality n-type GaAs that is currently commercially available.
Using a substrate (about EPD = 10''/c+fl), a buffer layer is grown on it by vapor phase epitaxy (MOVPE, MBE or VPE).The buffer layer includes MOVPE, MBE, or VPE.
A strained superlattice structure formed by BE method or a Si thin film formed by ordinary VPE method is used.

続いて、この基板上にyo−yo溶質供給法によりSi
結晶層を成長させる。溶媒に成長温度(900〜800
°C)より10°C程度高い温度で飽和するだけのSi
@溶解させ、これを成長溶液とする。y。
Next, Si was deposited on this substrate by the yo-yo solute supply method.
Grow a crystal layer. Growth temperature (900-800
Si saturates at a temperature approximately 10°C higher than
@Dissolve and use this as a growth solution. y.

−yo溶質供給法による第一層目の成長では基板のメル
トバックを防ぐため、10°C程度の過飽和をつけて成
長を開始し、0.2〜1.0 ’C/ minの降温速
度で50°C程度降温する。
-yo When growing the first layer using the solute supply method, in order to prevent meltback of the substrate, growth was started with supersaturation of about 10 °C, and the temperature was lowered at a cooling rate of 0.2 to 1.0 °C/min. The temperature will drop by about 50°C.

その後、再び成長開始温度まで昇温し、同様の温度サイ
クルを30〜50回程度繰り返すことにより、所望の厚
み(200μm程度)のSi結晶層を成長させる。
Thereafter, the temperature is raised again to the growth start temperature and the same temperature cycle is repeated about 30 to 50 times to grow a Si crystal layer of a desired thickness (about 200 μm).

rnP系半種半導体材料合もyo−yo溶質供給法を用
いて略同様に行えばよい。
The rnP semi-semiconductor material may be prepared in substantially the same manner using the yo-yo solute supply method.

次に、本発明の半導体材料を用いた0EICの一例を第
2図及び第3図に基づいて説明する。
Next, an example of 0EIC using the semiconductor material of the present invention will be explained based on FIGS. 2 and 3.

まず、高品質GaAs基板S′を用意し〔第2図(a)
参照〕、当該GaAsに格子整合する異種接合のAlG
aAs層10及びGaAs層11をLPEなどによって
GaAs基板S′上りエピタキシャル成長させる〔第2
図(1))参照〕。ここに、AlGaAs層10は後の
工程(e)で基板S′をエツチングにより除去する際の
エソチンゲストツバとして作用するものである。次に、
キャリア濃度が可及的に小さいSi (またはSi −
G(!混晶)層12を好適にはVPEによりエピタキシ
ャル成長させる〔第2図(C)参照〕。当該S1層12
はバッファ層として作用する。
First, a high-quality GaAs substrate S' is prepared [Fig. 2 (a)
], a heterojunction AlG lattice-matched to the GaAs
The aAs layer 10 and the GaAs layer 11 are grown epitaxially on the GaAs substrate S' by LPE or the like [Second
See Figure (1))]. Here, the AlGaAs layer 10 acts as an etching guest rib when the substrate S' is removed by etching in a later step (e). next,
Si (or Si −
The G (!mixed crystal) layer 12 is grown epitaxially, preferably by VPE [see FIG. 2(C)]. The S1 layer 12
acts as a buffer layer.

その後、前述の半導体材料の製作例の如<y。Thereafter, as in the example of manufacturing the semiconductor material described above.

yo溶質供給法によりSi層12上にSi (またはS
i−Ge)結晶層Sを、少なくとも200μm程度の厚
みに成長させる〔第2図(d)参照〕。これにより、第
1図に示す如き本発明の半導体材料が得られる。かかる
半導体材料において、Si結晶層SをSi基基板上して
用い0BICを作製すべく当該材料を逆様にし、例えば
Nl1nOH: 1120□系のエッチャントによりG
aAs基板S′をエツチング除去する〔第2図(e)参
照〕。さらに、AlGaAs層10を同様に1 フッ酸系エッチャントにより除去する〔第2図(f)参
照〕。
Si (or S
i-Ge) The crystal layer S is grown to a thickness of at least about 200 μm [see FIG. 2(d)]. As a result, the semiconductor material of the present invention as shown in FIG. 1 is obtained. In such a semiconductor material, in order to fabricate an 0BIC using a Si crystal layer S on a Si base substrate, the material is turned upside down and etched with G by, for example, an Nl1nOH: 1120□-based etchant.
The aAs substrate S' is removed by etching [see FIG. 2(e)]. Furthermore, the AlGaAs layer 10 is similarly removed using a 1-hydrofluoric acid etchant [see FIG. 2(f)].

この後は、既知の0BIC製作技術により半導体材料上
に光素子と電子素子を集積すればよい。
Thereafter, optical and electronic components may be integrated on the semiconductor material using known OBIC fabrication techniques.

例えば、基本的には露出させたS+基板上にFET部分
を、GaAs (またはGaP )層上にLDやフォト
ダイオード部分を形威することになる。この際、光素子
部分が電子素子部分よりも嵩高になり段差が生しるが、
この問題点を解消するには、当初から光素子部分を凹状
にしておく、或いは電子素子部分となるSin出部分上
にさらにS3を成長させておくなどの手段を用いればよ
い。
For example, basically the FET part is formed on the exposed S+ substrate, and the LD or photodiode part is formed on the GaAs (or GaP) layer. At this time, the optical element part becomes bulkier than the electronic element part, creating a step.
In order to solve this problem, it is possible to use means such as making the optical element part concave from the beginning or growing S3 on the Sine out part which becomes the electronic element part.

第2図(f)に示す半導体材料を用いて作製した0EI
Cの一例を第3図に示す。当該材料においてデバイス化
に先立ち電子素子部分のGaAs層11及び54層12
を適当なエツチング処理により除去し、Si結晶を露出
させておく。本0EIGは、GaAs層ll上に少なく
ともクランド層(AIGaAsなと)20、活性層(G
aAs、 ’AlGaAsなど)21、及びクラッド層
(AIGaAsなど)22を含んだ多層をエピタキシ2 ャル成長させ、さらにストライプ構造の電極(n型)2
3などを形威した後、襞間などの処理により共振器構造
となしたLDと、露出Si基板S上にイオン打ち込みな
どの既存の技術によりn型領域30(ドーパントとして
は5tXTeなど)及びp4型領域31 (ドーパント
としてはCd、 Znなと)を形威し、電極(n型、n
型、n型)32.33.34を設けてなるFETとを有
している。なお、S+基板Sの下面にも電極(n型)4
0が設けられている。
0EI manufactured using the semiconductor material shown in Figure 2(f)
An example of C is shown in FIG. In this material, GaAs layers 11 and 54 layers 12 of the electronic element portion are formed before device formation.
is removed by a suitable etching process to expose the Si crystal. This 0EIG has at least a ground layer (AIGaAs) 20 and an active layer (G
A multilayer including aAs, 'AlGaAs, etc.) 21 and a cladding layer (AIGaAs, etc.) 22 is epitaxially grown, and a striped electrode (n-type) 2 is further grown.
3, etc., the LD is made into a resonator structure by processing such as between the folds, and the n-type region 30 (the dopant is 5tXTe, etc.) and p4 are formed by existing techniques such as ion implantation on the exposed Si substrate S. A type region 31 (dopants such as Cd and Zn) is formed, and an electrode (n type, n
type, n-type) 32, 33, and 34. Note that an electrode (n type) 4 is also provided on the bottom surface of the S+ substrate S.
0 is set.

上記○EICは材料製作の当初からGaAs基板を用い
た例であるが、InPの場合も構造的には略同様である
。例えば、InPを基板S′に用いた場合に第2図に示
す製作工程図では、エツチングストッパ層10がGa1
nPAs、 GaAs層11がInP、クラッド層20
.22がGa1nPAs、活性層21がJlGaPAs
に置き換えるとよい。
The above EIC is an example in which a GaAs substrate was used from the beginning of material production, but the structure is almost the same in the case of InP. For example, in the manufacturing process diagram shown in FIG. 2 when InP is used for the substrate S', the etching stopper layer 10 is made of Ga1.
nPAs, GaAs layer 11 is InP, cladding layer 20
.. 22 is Ga1nPAs, active layer 21 is JlGaPAs
It is recommended to replace it with

なお、上記0BICは本の一例に過ぎず、本発明の0E
ICはこれに限定されないことはいうまでもない。
Note that the above 0BIC is only an example of the book, and the 0E of the present invention
It goes without saying that the IC is not limited to this.

〔発明の効果〕〔Effect of the invention〕

本発明の半導体材料、0EIC1並びに材料の結晶成長
法は、以上説明したように構成されているので、以下に
記載される如き効果を奏する。
Since the semiconductor material, 0EIC1, and the crystal growth method of the material of the present invention are configured as described above, they produce the effects described below.

yo−yo溶質供給法を用いてGaAsまたはInP基
板上にSi (またはSi−Ge)結晶層を成長させる
ことから、Si結晶層を厚く形成でき、半導体デバイス
作製時にSi結晶層をSi基板として使用することが可
能となり、特にGaAsまたはInP基板に高品質単結
晶基板を採用することで、デバイス化には当言亥GaA
sまたはInP基板をそのままGaAsまたはInP結
晶層として用いることができるので、極めて容易に高品
質なGaAsまたはInP結晶層が得られる。
Since a Si (or Si-Ge) crystal layer is grown on a GaAs or InP substrate using the yo-yo solute supply method, a thick Si crystal layer can be formed, and the Si crystal layer can be used as a Si substrate when manufacturing semiconductor devices. In particular, by using a high-quality single crystal substrate as a GaAs or InP substrate, it is possible to use GaAs for device fabrication.
Since the S or InP substrate can be used as it is as the GaAs or InP crystal layer, a high quality GaAs or InP crystal layer can be obtained very easily.

また、本発明の半導体材料を用いて作製した0BICは
、材料上に集積させる電子素子(FETなと)のSt系
LSI作製プロセス及び光素子(LD、フォトダイオー
ドなど)の作製プロセスをそのまま利用でき、0EIC
の実現が容易である。
Furthermore, the 0BIC fabricated using the semiconductor material of the present invention can be used as is in the St-based LSI fabrication process for electronic elements (FET etc.) integrated on the material and the fabrication process for optical elements (LD, photodiode, etc.). ,0EIC
is easy to realize.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はyo−yo溶質供給法によって作製した本発明
の半導体材料の一実施例を示す断面図、第2図(a)〜
(f)は半導体材料の製作例を示す工程流れ図、第3図
は第2図(f)の半導体祠料を用いた0EICの一例を
示す断面図、第4図は通常のMOVPEによって作製し
た従来の半導体材料の断面図である。 S′ : GaAsまたはInP基板 :バッファ層 :Si(またはSi−Ge)結晶層 :Si結晶層(基板) : GaAs基板(結晶層) 5 6 (a) (C) (e) 第2図 (b) (d) (f)
FIG. 1 is a cross-sectional view showing an example of the semiconductor material of the present invention produced by the yo-yo solute supply method, and FIG.
(f) is a process flow diagram showing an example of manufacturing a semiconductor material, FIG. 3 is a cross-sectional view showing an example of 0EIC using the semiconductor abrasive material of FIG. 2(f), and FIG. FIG. S': GaAs or InP substrate: Buffer layer: Si (or Si-Ge) crystal layer: Si crystal layer (substrate): GaAs substrate (crystal layer) 5 6 (a) (C) (e) Figure 2 (b) ) (d) (f)

Claims (3)

【特許請求の範囲】[Claims] (1)GaAsまたはInP基板上に直接もしくはバッ
ファ層を介してSiまたはSi−Ge結晶層を設けたこ
とを特徴とする半導体材料。
(1) A semiconductor material characterized in that a Si or Si-Ge crystal layer is provided on a GaAs or InP substrate directly or via a buffer layer.
(2)請求項(1)記載の半導体材料上に光素子と電子
素子を集積したことを特徴とする光電子集積回路素子。
(2) An optoelectronic integrated circuit device, characterized in that an optical device and an electronic device are integrated on the semiconductor material according to claim (1).
(3)GaAsまたはInP基板上に直接もしくはバッ
ファ層を成長させた後にyo−yo溶質供給法を用いて
SiまたはSi−Ge結晶層を成長させることを特徴と
する半導体材料の結晶成長法。
(3) A crystal growth method for a semiconductor material, which comprises growing a Si or Si-Ge crystal layer on a GaAs or InP substrate directly or after growing a buffer layer using a yo-yo solute supply method.
JP2059442A 1989-05-26 1990-03-09 Semiconductor material, photoelectric integrated circuit element, and crystal growth method of material Pending JPH0372680A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1-133946 1989-05-26
JP13394689 1989-05-26

Publications (1)

Publication Number Publication Date
JPH0372680A true JPH0372680A (en) 1991-03-27

Family

ID=15116765

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2059442A Pending JPH0372680A (en) 1989-05-26 1990-03-09 Semiconductor material, photoelectric integrated circuit element, and crystal growth method of material

Country Status (1)

Country Link
JP (1) JPH0372680A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6074892A (en) * 1996-05-07 2000-06-13 Ciena Corporation Semiconductor hetero-interface photodetector
US6147391A (en) * 1996-05-07 2000-11-14 The Regents Of The University Of California Semiconductor hetero-interface photodetector
JP2002308355A (en) * 2001-04-12 2002-10-23 Daizo:Kk Dispenser apparatus
KR20030058571A (en) * 2001-12-31 2003-07-07 주식회사 하이닉스반도체 A method for manufacturing a semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6074892A (en) * 1996-05-07 2000-06-13 Ciena Corporation Semiconductor hetero-interface photodetector
US6130441A (en) * 1996-05-07 2000-10-10 The Regents Of The University Of California Semiconductor hetero-interface photodetector
US6147391A (en) * 1996-05-07 2000-11-14 The Regents Of The University Of California Semiconductor hetero-interface photodetector
US6465803B1 (en) 1996-05-07 2002-10-15 The Regents Of The University Of California Semiconductor hetero-interface photodetector
JP2002308355A (en) * 2001-04-12 2002-10-23 Daizo:Kk Dispenser apparatus
KR20030058571A (en) * 2001-12-31 2003-07-07 주식회사 하이닉스반도체 A method for manufacturing a semiconductor device

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