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JPH0372617A - Improvement of characteristic of polycrystalline silicon thin film - Google Patents

Improvement of characteristic of polycrystalline silicon thin film

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Publication number
JPH0372617A
JPH0372617A JP1208539A JP20853989A JPH0372617A JP H0372617 A JPH0372617 A JP H0372617A JP 1208539 A JP1208539 A JP 1208539A JP 20853989 A JP20853989 A JP 20853989A JP H0372617 A JPH0372617 A JP H0372617A
Authority
JP
Japan
Prior art keywords
thin film
polycrystalline silicon
silicon thin
scanned
energy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1208539A
Other languages
Japanese (ja)
Other versions
JP3210313B2 (en
Inventor
Takashi Noguchi
隆 野口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP20853989A priority Critical patent/JP3210313B2/en
Publication of JPH0372617A publication Critical patent/JPH0372617A/en
Priority to JP10236993A priority patent/JPH11121379A/en
Priority to JP10236992A priority patent/JPH11121765A/en
Application granted granted Critical
Publication of JP3210313B2 publication Critical patent/JP3210313B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10Energy storage using batteries

Landscapes

  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To improve the electrical characteristics of a polycrystalline silicon thin film having a large area without forming a discontinuous part on the thin film by a method wherein an energy beam controlled in its energy is scanned on the thin film in such a way that irradiation regions are superposed on the thin film. CONSTITUTION:A beam 7 from an Excimer laser light source 8 is irradiated on a polycrystalline silicon thin film on a wafer placed on a stage 14 through a beam homogenizer 13. At this time, if the stage 14 or the homogenizer 13 is moved and a beam spot 7S is scanned, an annealing of the polycrystalline silicon thin film having a large area can be performed. In the scanning, the beam spot is scanned on a cell 5 (the polycrystalline silicon thin film) in the order of No. 1 to No. 5, for example, then, is scanned in the order of No. 5 to No. 8 and moreover, a central part 9 is irradiated to eliminate completely an unirradiated part. As the energy beam 7, a beam which performs a pulse oscillation in a short wavelength is used and it is desirable that the energy density of the beam 7 is set so as to satisfy the condition that the irradiation temperature of the beam is higher than the melting point of an amorphous silicon film and is lower than the melting point of a single crystal silicon film. Thereby, the crystal of a region 17, where irradiation regions are superposed, is not fused and the microdefect only of the crystal is improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、多結晶シリコン薄膜の特性改善方法、特に液
晶表示装置やラインセンサ等に組込まれる大面積(大容
量)LSIを製造する際の能動領域となる多結晶シリコ
ン薄膜の特性を改善するのに好適な多結晶シリコン薄膜
の特性改善方法に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for improving the characteristics of polycrystalline silicon thin films, particularly for manufacturing large-area (large-capacity) LSIs incorporated into liquid crystal display devices, line sensors, etc. The present invention relates to a method for improving the characteristics of a polycrystalline silicon thin film that is suitable for improving the characteristics of a polycrystalline silicon thin film that becomes an active region.

〔発明のヰ既要〕[Existing necessity of invention]

本発明は、例えばLSI等を製造する際に適用される多
結晶シリコン薄膜の特性改善方法において、エネルギ制
御されたエネルギビームを多結晶シリコン薄膜に照射領
域が重なるように上記エネルギビームを走査することに
より、大面積を有する多結晶シリコン薄膜に対して不連
続な部分を形成させることなく電気的特性の改善を目的
としたアニールが行なえるようにしたものである。
The present invention provides a method for improving the characteristics of a polycrystalline silicon thin film, which is applied, for example, when manufacturing LSIs, etc., in which the energy beam is scanned so that the irradiation area overlaps the polycrystalline silicon thin film. This makes it possible to perform annealing for the purpose of improving the electrical characteristics of a polycrystalline silicon thin film having a large area without forming discontinuous portions.

〔従来の技術〕[Conventional technology]

一般に、薄膜トランジスタは、石英ガラス等の絶縁基板
上に、多結晶シリコン等の半導体薄膜を被着形成し、こ
の薄膜半導体層に例えばチャネルが形成される活性領域
や低抵抗のソース領域、ドレイン領域を夫々懲戒して電
界効果型トランジスタを構成するようにしている。
In general, thin film transistors are made by depositing a semiconductor thin film such as polycrystalline silicon on an insulating substrate such as quartz glass, and this thin film semiconductor layer has an active region where a channel is formed, a low resistance source region, and a drain region. Each of them is adapted to form a field effect transistor.

ところで、薄膜トランジスタの基板としては、従来より
高融点の石英ガラスが一般に用いられているが、材料費
が嵩み高価となるため、石英ガラスより低融点の通常の
耐熱ガラスを基板に用いることが臨まれている、このよ
うな比較的低融点の耐熱ガラスを基板に用いる場合には
、薄膜トランジスタの製造工程中の基板上の上限温度を
基板ガラスの歪点以下とするような低温プロセスが必要
となる。
By the way, silica glass with a high melting point has been generally used as a substrate for thin film transistors, but since the material costs are high and expensive, it is important to use ordinary heat-resistant glass with a lower melting point than quartz glass for the substrate. When using heat-resistant glass with a relatively low melting point as a substrate, a low-temperature process is required to keep the upper limit temperature on the substrate during the manufacturing process of thin film transistors below the strain point of the substrate glass. .

しかしながら、このような低温プロセスにおいては、特
性の良好な活性領域を得ることは困難である。即ち、基
板上に例えばCVD (化学気相成長)法等でシリコン
を被着形成したのみでは、結晶粒径の小さなトラップ密
度の高い多結晶シリコン層が形成され、電気的特性、特
にしきい値電圧vth、  サブスレッショルド特性、
移動度μ、リーク電流の点で良好なものが得られない。
However, in such a low temperature process, it is difficult to obtain an active region with good characteristics. That is, if silicon is simply deposited on a substrate by, for example, CVD (chemical vapor deposition), a polycrystalline silicon layer with a small crystal grain size and high trap density will be formed, which will affect the electrical characteristics, especially the threshold voltage. Voltage vth, subthreshold characteristics,
Good mobility μ and leakage current cannot be obtained.

そのため、基板上に多結晶シリコン層を形成した後、シ
リコンイオンS1+を注入して非晶質化し、次いで低温
アニール(600℃程度)して結晶粒径を大きくした多
結晶シリコン層を得る方法が考えられている。
Therefore, after forming a polycrystalline silicon layer on a substrate, silicon ions S1+ are implanted to make it amorphous, and then low-temperature annealing (approximately 600°C) is performed to obtain a polycrystalline silicon layer with increased crystal grain size. It is considered.

この場合には、比較的高性能の薄膜トランジスタが得ら
れるが、1000℃の高温プロセスで製造された薄膜ト
ランジスタには及ばない。この原因は、多結晶シリコン
層の結晶粒径でなく、その粒界トラップ密度が600℃
では充分改善されないからである。
In this case, a relatively high performance thin film transistor can be obtained, but it is not as good as a thin film transistor manufactured by a high temperature process of 1000°C. The cause of this is not the crystal grain size of the polycrystalline silicon layer, but the grain boundary trap density at 600°C.
This is because the improvement is not sufficient.

そこで、上記低温アニール後、Arレーザで短時間のア
ニールを施して多結晶シリコン層のトラ・ソプ密度を低
減させる方法が考えられるが、このArレーザは、波長
が長く、連続発振(CW)のため、面による照射が困難
であり、大面積を有する膜厚1000人未満の多結晶シ
リコン薄膜には適さない。
Therefore, after the above-mentioned low-temperature annealing, it is possible to perform short-time annealing with an Ar laser to reduce the trasop density of the polycrystalline silicon layer, but this Ar laser has a long wavelength and is a continuous wave (CW). Therefore, surface irradiation is difficult, and it is not suitable for polycrystalline silicon thin films having a large area and a film thickness of less than 1,000.

ところが、最近、短波長のパルスを発振するエキシマレ
ーザ′によるパルスレーザアニールが注目され、実用化
されている。
However, recently, pulsed laser annealing using an excimer laser that emits short-wavelength pulses has attracted attention and has been put into practical use.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、従来のエキシマレーザによるパルスレー
ザアニールは、照射領域を瞬時に溶融して行っているた
め、特に大面積の多結晶シリコン薄膜に対してアニール
した場合、不連続面が形成され、その後のデバイス作製
に影響を及ぼすという不都合があった。
However, since conventional pulsed laser annealing using an excimer laser instantaneously melts the irradiated area, discontinuous surfaces are formed, especially when annealing a large area of polycrystalline silicon thin film, resulting in subsequent device devices. There was an inconvenience in that it affected the manufacturing process.

即ち、エキシマレーザビームを光学的ホモジナイザを介
して多結晶シリコン薄膜に照射すると、10mm角の照
射面積を得ることができ、これを走査することによって
、大面積アニールが可能となるが、上述の如く、照射領
域を溶融する程度のエネルギ密度(約IJ/cnf)で
行なうため、各照射領域間で未溶融領域が形成されるの
を防止する目的で照射領域を1部重ねて走査した場合、
照射領域の重なった部分が更に溶融し、結果的に多結晶
シリコン薄膜表面が不連続面、即ち凹凸面となってしま
い、その後のデバイス作製に支障を来すという不都合が
あった。
That is, when an excimer laser beam is irradiated onto a polycrystalline silicon thin film through an optical homogenizer, an irradiation area of 10 mm square can be obtained, and by scanning this, large area annealing is possible. , since scanning is carried out at an energy density (approximately IJ/cnf) that melts the irradiated area, if the irradiated areas are partially overlapped and scanned in order to prevent the formation of unmelted areas between each irradiated area,
The overlapping portions of the irradiated areas are further melted, resulting in the surface of the polycrystalline silicon thin film becoming discontinuous, that is, an uneven surface, which poses an inconvenience in subsequent device fabrication.

本発明は、このような点に鑑み威されたもので、その目
的とするところは、大面積を有する多結晶シリコン薄膜
に対して、不連続面を形成することとなく、均一にトラ
ップ密度の低減を目的としたアニールを行なうことがで
きる多結晶シリコン薄膜の特性改善方法を提供すること
にある。
The present invention was developed in view of these points, and its purpose is to uniformly increase the trap density in a polycrystalline silicon thin film having a large area without forming discontinuous surfaces. It is an object of the present invention to provide a method for improving the characteristics of a polycrystalline silicon thin film by which annealing can be performed for the purpose of reduction.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の多結晶シリコン薄膜の改善方法は、エネルギ制
御されたエネルギビーム(7)を多結晶シリコン薄膜(
5)にその照射領域(15)が重なるように、上記エネ
ルギビーム(7)を走査する。
The method for improving a polycrystalline silicon thin film of the present invention is to apply a controlled energy beam (7) to a polycrystalline silicon thin film (
5), the energy beam (7) is scanned so that the irradiation area (15) overlaps with the energy beam (7).

上記エネルギビーム(7)は、短波長でパルス発振する
もの、例えばエキシマレーザを用いるを可とする。また
エネルギビーム(7)のエネルギ密度は、照射温度が非
晶質シリコンの融点よりも高く、かつ単結晶シリコンの
融点よりも低い条件になるように設定するを可とする。
The energy beam (7) may be one that generates pulses at a short wavelength, such as an excimer laser. The energy density of the energy beam (7) can be set so that the irradiation temperature is higher than the melting point of amorphous silicon and lower than the melting point of single crystal silicon.

〔作用〕[Effect]

上述の本発明の方法によれば、エネルギビーム(7)の
照射温度が例えば非晶質シリコンの融点よりも高く、か
つ単結晶シリコンの融点よりも低くなるようにエネルギ
密度を制御してエネルギビーム(7)をその照射領域(
15)が一部(17)で重なるように多結晶シリコン薄
膜(5)に走査するので、大面積を有する多結晶シリコ
ン薄膜(5)中の結晶部分は溶融せずに微小欠陥のみ改
善される。従って、大面積を有する多結晶シリコン薄膜
(5)表面に不連続面(凹凸面)を形成することなく、
多結晶シリコン薄膜(5)のトラップ密度を低減するこ
とができる。
According to the method of the present invention described above, the energy density is controlled such that the irradiation temperature of the energy beam (7) is higher than the melting point of amorphous silicon and lower than the melting point of single crystal silicon, for example. (7) to its irradiation area (
15) is scanned over the polycrystalline silicon thin film (5) so that it partially overlaps (17), so the crystalline part in the polycrystalline silicon thin film (5), which has a large area, is not melted and only minute defects are improved. . Therefore, without forming a discontinuous surface (uneven surface) on the surface of the polycrystalline silicon thin film (5) having a large area,
The trap density of the polycrystalline silicon thin film (5) can be reduced.

このことは、従来達成できなかった大面積を有する多結
晶シリコン薄膜(5)に対する膜質向上を目的としたア
ニールを実現させることができ、液晶表示装置やライン
センサ等に用いられる大容量メモリ (メガビット級D
RAMやSRAM等)の形成をより効率よく、かつ特性
の劣化を招来させることなく行なうことができる。
This makes it possible to achieve annealing for the purpose of improving the film quality of polycrystalline silicon thin films (5) that have large areas, which was previously unachievable. Class D
RAM, SRAM, etc.) can be formed more efficiently and without causing deterioration of characteristics.

〔実施例〕〔Example〕

以下、第1図〜第4図を参照しながら本発明の詳細な説
明する。
Hereinafter, the present invention will be explained in detail with reference to FIGS. 1 to 4.

第1図は、本実施例に係る多結晶シリコン薄膜の特性改
善方法を示す工程図である。以下順を追ってその工程を
説明する。
FIG. 1 is a process diagram showing a method for improving the characteristics of a polycrystalline silicon thin film according to this embodiment. The steps will be explained step by step below.

まず、第1図Aに示すように、例えば耐熱ガラスより成
る絶縁基板(1)上に膜厚1000 A程度の5102
膜(2)を形成したのち、該3102膜(2)土に膜厚
800人程0の多結晶シリコン薄膜(3)を例えばCV
D法等で被着形成する。
First, as shown in FIG.
After forming the film (2), a polycrystalline silicon thin film (3) with a film thickness of about 800 mm is applied to the 3102 film (2) by CVD, for example.
Adhesion is formed using the D method or the like.

次に、第1図Bに示すように、多結晶シリコン薄膜(3
)に対してシリコンイオンSi+をイオン注入して多結
晶シリコン薄膜(3)を非晶質シリコン薄膜(4)に変
化させる。このときのSi+のイオン注入条件としては
、例えば打込みエネルギ約40KeV とし、打込みド
ーズ量を1.5 X 10− ” cm−2程度とする
Next, as shown in FIG. 1B, a polycrystalline silicon thin film (3
) to transform the polycrystalline silicon thin film (3) into an amorphous silicon thin film (4). The Si+ ion implantation conditions at this time are, for example, an implantation energy of approximately 40 KeV and an implantation dose of approximately 1.5 x 10-'' cm-2.

次に、第↓図Cに示すように、非晶質シリコン薄膜(4
)に対して例えば600℃、3時間の低温熱処理を施し
て結晶成長させ、図示する如く結晶粒の大きな多結晶シ
リコン薄膜(5)を形成する。このとき、多結晶シリコ
ン薄膜(5)は、粒径は成長するが、粒界のトラップ密
度は悪い(高い)。
Next, as shown in Figure C, an amorphous silicon thin film (4
) is subjected to low-temperature heat treatment at, for example, 600° C. for 3 hours to grow crystals, thereby forming a polycrystalline silicon thin film (5) with large crystal grains as shown in the figure. At this time, the grain size of the polycrystalline silicon thin film (5) grows, but the trap density at grain boundaries is poor (high).

次に、第1図りに示すように、多結晶シリコン薄膜(5
)上に膜厚500人程0の5102膜(6)を例えばC
VD法等で被着形成する。
Next, as shown in the first diagram, a polycrystalline silicon thin film (5
) on top of the 5102 film (6) with a thickness of about 500 mm
Adhesion is formed using a VD method or the like.

次に、第1図Eに示すように、多結晶シリコン薄膜(5
)に対して希ガス・ハライドエキシマレーザビーム(7
)を照射してトラップ密度の低減化を目的としたアニー
ルを行なう。本例では、第2図に示すように、希ガス・
ハライドエキシマレーザ光源(8)として波長308n
mのXeαエキシマレーザ光源を用い、該レーザ光源(
8)からのビーム(7)をワークステーション、図示の
例では、ミラー(9)、アッテネータ(10〉、ミラー
(11)及び(12)、ビームホモジナイザ〈13〉を
介してステージ(14)上に載置されたウェハ(図示せ
ず)上の多結晶シリコン薄膜(5)に照射する。このと
き、ビームホモジナイザ(13)を経て照射されたビー
ム(7)は、そのビームプロファイルが広範囲にわたり
極めて均一となり、ビームスボッ) (7S)の形状が
第2図の拡大図で示すように、10mm角の矩形状の照
射面積を有するものとなる。
Next, as shown in FIG. 1E, a polycrystalline silicon thin film (5
) to a rare gas halide excimer laser beam (7
) to perform annealing for the purpose of reducing the trap density. In this example, as shown in Figure 2, rare gas
Wavelength 308n as halide excimer laser light source (8)
m Xeα excimer laser light source is used, and the laser light source (
8) onto a stage (14) via a workstation, in the example shown, a mirror (9), an attenuator (10>, mirrors (11) and (12), and a beam homogenizer <13>). The polycrystalline silicon thin film (5) on the mounted wafer (not shown) is irradiated.At this time, the beam (7) irradiated via the beam homogenizer (13) has an extremely uniform beam profile over a wide range. As shown in the enlarged view of FIG. 2, the shape of the beam sub-box (7S) has a rectangular irradiation area of 10 mm square.

また、ビーム(7)は、その照射温度が、多結晶シリコ
ン薄膜(5)を溶融させない程度の温度、即ち非晶質シ
リコンの融点より高く、単結晶シリコンの融点より低く
なるようにそのエネルギ密度を設定する。本例(800
人厚0多結晶シリコン薄膜(5)、500人厚人厚in
2膜(6))では、300m J / cntより近い
密度に設定する。
The energy density of the beam (7) is such that the irradiation temperature is high enough not to melt the polycrystalline silicon thin film (5), that is, higher than the melting point of amorphous silicon and lower than the melting point of single crystal silicon. Set. This example (800
Thickness of 0 polycrystalline silicon (5), thickness of 500 in
2 membrane (6)), the density is set to closer than 300 mJ/cnt.

そして、本例では、ステージ(14)又はビームホモジ
ナイザ(13)を相対的に移動させてビームスボッ) 
(7S)をステージ(■4)上の多結晶シリコン薄膜(
5)に対して走査させる。このようにすれば、大面積を
有する多結晶シリコン薄膜(5)に対しレーザビーム(
7)による大面積アニールを行なうことができる。
In this example, the stage (14) or the beam homogenizer (13) is moved relatively to
(7S) on the stage (■4) with a polycrystalline silicon thin film (
5) Scan. In this way, the laser beam (
7) can be performed over a large area.

第3図は、2Qmm角の矩形状セル(多結晶シリコン薄
膜)(5)に対し、10mm角のビームスポットを走査
させる例を示したもので、まず、第3図Aに示すように
、ビームスポットをセル(5)に対し番号12、3.4
の順に走査させる。このときはまだ照射領域(15)の
境界(16〉において未照射部分が存在し、セル(5)
表面は不連続となっている。
Figure 3 shows an example in which a 10 mm square beam spot is scanned on a 2Q mm square rectangular cell (polycrystalline silicon thin film) (5). Spot number 12, 3.4 for cell (5)
scan in this order. At this time, there is still an unirradiated area at the boundary (16) of the irradiated area (15), and the cell (5)
The surface is discontinuous.

次に、第3図Bに示すように、ビームスポットをセル(
5)に対し番号5.6..7.8の順に走査し、更に、
第3図Cの番号9で示すように、セル(5)の中央部分
を照射する。この段階で完全に未照射部分がなくなりセ
ル(5)表面に存していた不連続部分は消失する。また
、ビーム(7)のエネルギ密度を上述の如く設定したの
で、最初の照射領域(番号1,23.4で示す領域) 
(15)及び照射領域(15)が重な0 った領域(番号5.6.7.8.9で示す領域> (1
7)における結晶部分は溶けず微小欠陥のみ改善され、
多結晶シリコン薄膜(5)中の結晶の溶融に伴う不連続
面は形成されない。上記の例は、エネルギ密度を一定に
してビーム(7)を照射したが、番号5,6゜7、8.
9で示す領域(17)を照射する際のエネルギ密度を番
号1,2.3.4で示す領域(15)を照射する際のエ
ネルギ密度より低く設定してもよい。また、走査順序と
しては、上記の例のほか、第4図に示すように行っても
よい。この場合においても、照射領域及び照射領域が重
なった領域における結晶部分は溶けず微小欠陥のみ改善
され、不連続面は形成されない。
Next, as shown in Figure 3B, the beam spot is placed in the cell (
5) for number 5.6. .. 7. Scan in the order of 8, and further,
The central part of the cell (5) is irradiated as indicated by number 9 in Figure 3C. At this stage, the unirradiated area is completely eliminated and the discontinuous area existing on the surface of the cell (5) disappears. In addition, since the energy density of beam (7) was set as described above, the first irradiation area (area indicated by number 1, 23.4)
(15) and the irradiation area (15) overlap (area indicated by number 5.6.7.8.9)> (1
The crystal part in 7) did not melt and only the micro defects were improved.
No discontinuous surfaces are formed due to melting of the crystals in the polycrystalline silicon thin film (5). In the above example, the beam (7) was irradiated with a constant energy density, but the numbers 5, 6°7, 8.
The energy density when irradiating the region (17) indicated by number 9 may be set lower than the energy density when irradiating the region (15) indicated by numbers 1, 2, 3, and 4. In addition to the above example, the scanning order may be as shown in FIG. 4. Even in this case, the crystal portions in the irradiated areas and the area where the irradiated areas overlap are not melted and only minute defects are improved, and no discontinuous surfaces are formed.

この工程以降は、素子形成領域の分離、素子形成領域へ
のデバイス作製等が行なわれて本例に係る電気的特性が
改善されたLSIを得る。
After this step, separation of the element formation region, device fabrication in the element formation region, etc. are performed to obtain an LSI with improved electrical characteristics according to this example.

上述の如く本例によれば、第1図Eにおいて、XeCJ
!エキシマレーザビーム(7)によるアニール処理時、
ビーム(7)の照射温度が多結晶シリコン薄膜(5)中
の結晶の溶融温度より低くなるように、即ち非晶質シリ
コンの融点より高く、単結晶シリコンの融点より低くな
るようにビーム(7)のエネルギ密度を設定し、更にビ
ームホモジナイザ(13)によりビームスボッ) (7
S)の形状を例えば19mm角の矩形状にし、そしてこ
のビームスポット(7S)を多結晶シリコン薄膜(5)
に対し、一部が重なるように走査するようにしたので、
ビーム(7)の照射領域(15)及び照射領域(15)
が重なった領域(17)における結晶部分は溶けず微小
欠陥のみ改善される。その結果、大面積を有する多結晶
シリコン薄膜(5)表面に未照射及び結晶部分の溶融に
伴う不連続面(凹凸面)を形成することなく、多結晶シ
リコン薄膜(5)のトラップ密度を低減することができ
、従来達成できなかった大面積を有する多結晶シリコン
薄膜(5)の膜質向上を目的としたアニールを実現させ
ることができ、液晶表示装置やラインセンサ等に用いら
れる大容量メモリ 〈メガビット級DRAMやSRAM
等〉の形成をより効率よく、かつ特性の劣化を招来させ
ることなく行なうことができる。
As described above, according to this example, in FIG. 1E, XeCJ
! During annealing treatment with excimer laser beam (7),
The beam (7) is applied so that the irradiation temperature of the beam (7) is lower than the melting temperature of the crystal in the polycrystalline silicon thin film (5), that is, higher than the melting point of amorphous silicon and lower than the melting point of single crystal silicon. ), and then the beam homogenizer (13) is used to set the energy density of the beam (7).
For example, the shape of S) is made into a rectangular shape of 19 mm square, and this beam spot (7S) is placed on a polycrystalline silicon thin film (5).
However, since we scanned so that some parts overlapped,
Irradiation area (15) and irradiation area (15) of beam (7)
The crystal part in the overlapping region (17) is not melted and only minute defects are improved. As a result, the trap density of the polycrystalline silicon thin film (5) is reduced without forming discontinuous surfaces (uneven surfaces) due to unirradiated and melted crystal parts on the surface of the polycrystalline silicon thin film (5), which has a large area. It is possible to achieve annealing for the purpose of improving the film quality of polycrystalline silicon thin films (5) with large areas, which could not be achieved conventionally. Megabit class DRAM and SRAM
etc.) can be formed more efficiently and without causing deterioration of characteristics.

また、ビーム(7)のエネルギ密度を上述の如く多層1 2 結晶シリコン薄膜(5)中の結晶が溶融しない程度の照
射温度となるように設定したので、レーザ出力に関する
負担を軽減することができると共に、多層構造のメモリ
セルを作製する場合、下部のトランジスタの特性を劣化
させることなく、即ち不純物領域を必要以上に拡散させ
ることなく上部のトランジスタを形成することができる
In addition, the energy density of the beam (7) is set at a temperature that does not melt the crystals in the multilayer 1 2 crystalline silicon thin film (5) as described above, so the burden on laser output can be reduced. In addition, when manufacturing a memory cell with a multilayer structure, the upper transistor can be formed without deteriorating the characteristics of the lower transistor, that is, without unnecessarily diffusing the impurity region.

また、エキシマレーザビーム(7)による多結晶シリコ
ン薄膜(5)へのアニール処理時、第1図Eに示すよう
に、多結晶シリコン薄膜(5)上に5102膜(6)を
形成してから行なうようにしたので、8102膜(6)
が一種の反射防止膜となり(即ち、多結晶シリコン薄膜
(5)に直接XeC#エキシマレーザビーム(7)を照
射すると、表面において約70%が反射されてしまうが
、5in2膜(6)を介して照射するとほとんど反射さ
れない)、多結晶シリコン薄膜(5)へのアニール効率
をより高めることができ、膜中のトラップ密度の低減化
をより一層図ることができる。
In addition, when annealing the polycrystalline silicon thin film (5) using the excimer laser beam (7), as shown in FIG. 8102 membrane (6)
becomes a kind of anti-reflection film (i.e., when the polycrystalline silicon thin film (5) is directly irradiated with the XeC# excimer laser beam (7), approximately 70% of it is reflected at the surface, but it is reflected through the 5in2 film (6)). (When irradiated with light, there is almost no reflection), the annealing efficiency of the polycrystalline silicon thin film (5) can be further increased, and the trap density in the film can be further reduced.

〔発明の効果〕〔Effect of the invention〕

本発明に係る多結晶シリコン薄膜の特性改善方法は、エ
ネルギ制御されたエネルギビームを多結晶シリコン薄膜
に照射領域が重なるように上記エネルギビームを走査す
るようにしたので、大面積を有する多結晶シリコン薄膜
に対して不連続な部分を形成することなく上記多結晶シ
リコン薄膜の電気的特性を改善することができる。
In the method for improving the characteristics of a polycrystalline silicon thin film according to the present invention, the energy beam is scanned so that the irradiation area overlaps the polycrystalline silicon thin film, so that the polycrystalline silicon film has a large area. The electrical characteristics of the polycrystalline silicon thin film can be improved without forming discontinuous portions in the thin film.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本実施例に係る多結晶シリコン薄膜の特性改善
方法を示す工程図、第2図は本実施例に係るレーザアニ
ール処理を示す構成図、第3図は本実施例に係る走査順
序を示す工程図、第4図は他の走査順序を示す工程図で
ある。 (1)は絶縁基板、(2)、 (6)は5in2膜、(
3)、 (5)は多結晶シリコン薄膜、(4)は非晶質
シリコン薄膜、(7)はレーザビーム、(7S)はビー
ムスポット、(8)は光源、(9)、 ’(11)、(
12)はミラー、(10)はアッテネータ、(13)は
ビームホモジナイザ、(14)はステージ、(15)は
照射領域、(17)は照射領域が重なった領域である。 9 4 Cゴ ー− 123− (コ 化 の L 41すe序1 示−9′ 工享星間第4区 125
Fig. 1 is a process diagram showing a method for improving the characteristics of a polycrystalline silicon thin film according to this embodiment, Fig. 2 is a block diagram showing a laser annealing process according to this embodiment, and Fig. 3 is a scanning order according to this embodiment. FIG. 4 is a process diagram showing another scanning order. (1) is an insulating substrate, (2) and (6) are 5in2 films, (
3), (5) is a polycrystalline silicon thin film, (4) is an amorphous silicon thin film, (7) is a laser beam, (7S) is a beam spot, (8) is a light source, (9), '(11) ,(
12) is a mirror, (10) is an attenuator, (13) is a beam homogenizer, (14) is a stage, (15) is an irradiation area, and (17) is an area where the irradiation areas overlap. 9 4 C Go - 123 - (L 41 S e Introduction 1 Show - 9' Kokyo Interstellar 4th Ward 125

Claims (1)

【特許請求の範囲】[Claims] エネルギ制御されたエネルギビームを多結晶シリコン薄
膜に照射領域が重なるように上記エネルギビームを走査
することを特徴とする多結晶シリコン薄膜の特性改善方
法。
1. A method for improving the characteristics of a polycrystalline silicon thin film, comprising scanning an energy beam whose energy is controlled so that the irradiation area overlaps the polycrystalline silicon thin film.
JP20853989A 1989-08-11 1989-08-11 Method for improving characteristics of polycrystalline silicon thin film Expired - Lifetime JP3210313B2 (en)

Priority Applications (3)

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JP20853989A JP3210313B2 (en) 1989-08-11 1989-08-11 Method for improving characteristics of polycrystalline silicon thin film
JP10236993A JPH11121379A (en) 1989-08-11 1998-08-24 Method for improving properties of polycrystal silicon thin film
JP10236992A JPH11121765A (en) 1989-08-11 1998-08-24 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20853989A JP3210313B2 (en) 1989-08-11 1989-08-11 Method for improving characteristics of polycrystalline silicon thin film

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5529951A (en) * 1993-11-02 1996-06-25 Sony Corporation Method of forming polycrystalline silicon layer on substrate by large area excimer laser irradiation
US6066516A (en) * 1995-06-26 2000-05-23 Seiko Epson Corporation Method for forming crystalline semiconductor layers, a method for fabricating thin film transistors, and method for fabricating solar cells and active matrix liquid crystal devices

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001147446A (en) * 1999-11-19 2001-05-29 Hitachi Ltd Liquid crystal display device and manufacturing method thereof
JP5244274B2 (en) * 2000-04-28 2013-07-24 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5529951A (en) * 1993-11-02 1996-06-25 Sony Corporation Method of forming polycrystalline silicon layer on substrate by large area excimer laser irradiation
US6066516A (en) * 1995-06-26 2000-05-23 Seiko Epson Corporation Method for forming crystalline semiconductor layers, a method for fabricating thin film transistors, and method for fabricating solar cells and active matrix liquid crystal devices
US6455360B1 (en) 1995-06-26 2002-09-24 Seiko Epson Corporation Method for forming crystalline semiconductor layers, a method for fabricating thin film transistors, and a method for fabricating solar cells and active matrix liquid crystal devices
US6746903B2 (en) 1995-06-26 2004-06-08 Seiko Epson Corporation Method for forming crystalline semiconductor layers, a method for fabricating thin film transistors, and a method for fabricating solar cells and active matrix liquid crystal devices

Also Published As

Publication number Publication date
JPH11121765A (en) 1999-04-30
JPH11121379A (en) 1999-04-30
JP3210313B2 (en) 2001-09-17

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