JPH036843U - - Google Patents
Info
- Publication number
- JPH036843U JPH036843U JP1989066945U JP6694589U JPH036843U JP H036843 U JPH036843 U JP H036843U JP 1989066945 U JP1989066945 U JP 1989066945U JP 6694589 U JP6694589 U JP 6694589U JP H036843 U JPH036843 U JP H036843U
- Authority
- JP
- Japan
- Prior art keywords
- lead portion
- die pad
- outer lead
- insulating film
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Die Bonding (AREA)
Description
第１図は本考案にかかるリードフレームの一実
施例を示し、Ａはその平面図、ＢはＡにおける
Ｂ−Ｂ線に沿う断面図、第２図および第３図は
従来の半導体素子用リードフレームを示す図、第
４図従来の半導体素子用リードフレームにおける
各部材間の電気的接続を説明する図、第５図はダ
イパツド部に絶縁基板または絶縁性フイルムを貼
り付ける場合の説明図である。
１……リードフレーム、２……アウタリード部
、３……インナリード部、４……ダイパツド部、
４ａ……凹部、５……絶縁基板または絶縁性フイ
ルム。
FIG. 1 shows an embodiment of a lead frame according to the present invention, A is a plan view thereof, B is a sectional view taken along line B-B in A, and FIGS. 2 and 3 are conventional leads for semiconductor devices. Figure 4 is a diagram illustrating the electrical connection between each member in a conventional lead frame for semiconductor devices; Figure 5 is an explanatory diagram when an insulating substrate or insulating film is attached to the die pad. . 1... Lead frame, 2... Outer lead part, 3... Inner lead part, 4... Die pad part,
4a... recess, 5... insulating substrate or insulating film.
Claims (1)
極が形成されている絶縁基板または絶縁性フイル
ムが貼り付けられるダイパツド部と、前記アウタ
ーリード部から延長形成されると共に他端が前記
独立電極とワイヤーにより接続されるインナリー
ド部とを備えたリードフレームにおいて、 前記ダイパツド部に、前記絶縁基板または絶縁
性フイルムが嵌合し得る大きさの凹部が設けられ
ていることを特徴とするリードフレーム。[Claims for Utility Model Registration] An outer lead portion connected to a circuit, a die pad portion to which an insulating substrate or insulating film is attached on which an independent electrode is formed, and an outer lead portion extending from the outer lead portion and other parts. In the lead frame including an inner lead portion whose end is connected to the independent electrode by a wire, the die pad portion is provided with a recessed portion large enough to fit the insulating substrate or the insulating film. Characteristic lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989066945U JPH036843U (en) | 1989-06-08 | 1989-06-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989066945U JPH036843U (en) | 1989-06-08 | 1989-06-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH036843U true JPH036843U (en) | 1991-01-23 |
Family
ID=31600088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989066945U Pending JPH036843U (en) | 1989-06-08 | 1989-06-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH036843U (en) |
-
1989
- 1989-06-08 JP JP1989066945U patent/JPH036843U/ja active Pending