JPH0366220A - Oscillator circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to provide an oscillation circuit that generates a rectangular signal train of a predetermined frequency and has a function of appropriately controlling the start and stop of oscillation. Or, when a control signal that sets the oscillation stop at a voltage level is applied to one input contact, its output is applied to one input contact of the OR circuit, and the output of the OR circuit is applied to the other input contact. An AND circuit that feeds back and applies to the input contact, a delay circuit that delays and transfers the output of the OR circuit, and an inverted output of the delay circuit that feeds back to the other input contact of the OR circuit for application. With this configuration, oscillation can be started or stopped as appropriate, and the duty ratio of the rectangular signal generated during the period from the start of oscillation to the stop of oscillation is kept constant.

[Industrial Application Field] The present invention relates to an oscillation circuit that generates a rectangular signal train of a predetermined frequency, and the oscillation period can be appropriately set, and the oscillation period can be set uniformly regardless of the timing of starting or stopping oscillation. The present invention relates to an oscillation circuit that generates a rectangular signal string consisting of rectangular waves.

[Prior Art] Conventionally, a digital system incorporating a microcomputer or the like operates in synchronization with a reference clock of a predetermined frequency formed by an oscillation circuit using a crystal oscillator, a ceramic oscillator, or the like.

Such digital systems are required to be battery-powered or power-saving, such as so-called portable computers, and in order to meet these demands,
It consists of a microprocessor, memory, and logic device with an 0MO8 structure, and a method is adopted in which the oscillation of the reference clock is stopped during idling, such as when the power is simply turned on without operation.

In other words, a device with a 0MO8 structure has the characteristic that its power consumption is almost zero except during switching operations, so by stopping the reference clock, it is possible to significantly reduce power consumption during idling. .

However, conventional oscillation circuits using crystal oscillators, ceramic oscillators, etc. take time to start oscillating, so they are not suitable for stopping systems or parts of systems that require high-speed response, and these problems arise. In order to solve this problem, an attempt was made to apply a ring oscillator as shown in FIG. That is, in FIG. 6, a control signal I is applied to one input contact of a two-man powered NAND gate 2, and the output of the NAND gate 2 is delayed by passing it through a plurality of stages of gates 4 and 6, and the delayed output is signal Q to N
It is configured to feed back to the other input contact of the AND gate 2, and as shown in FIG. 7, the rectangular signal train Q as a reference clock is generated only during the period when the control signal I is at the "L" level, so that the oscillation Stopping or starting can be controlled as appropriate.

[Problems to be Solved by the Invention] However, in an oscillation circuit using a conventional ring oscillator, if the timing of stopping oscillation is off, a noisy pulse (so-called whisker-like pulse) is generated, and this is caused by a microcomputer. disrupt the operating cycle of
An abnormality may occur in the transfer of data or address data, etc.
There were problems that caused the system to run out of control. That is, as shown in the timing chart of FIG. 7, the control signal I is changed from "L" to "H" in order to set the oscillation stop.
If the timing when the level is inverted is not synchronized with the inversion point of a rectangular signal with a constant period and duty ratio,
A pulse having a width narrower than that of a regular rectangular signal is generated, leading to the above-mentioned problem.

The present invention has been made in view of these problems,
In an oscillation circuit that generates a rectangular signal used as a reference clock of a digital system, it is possible to set the oscillation start or oscillation stop arbitrarily, and the rise time from the instruction to start oscillation to the actual oscillation is fast. It is an object of the present invention to provide an oscillation circuit in which the final output when oscillation is stopped is a rectangular signal with a regular pulse width.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

First, the present invention is an oscillation circuit that generates a rectangular signal that is applied to a reference clock of a digital system, which can start and stop oscillation at any timing, and has a predetermined cycle and a predetermined duty ratio. The target is an oscillation circuit that constantly outputs a rectangular signal.

For such an oscillation circuit, the present invention provides an AND circuit 8 to which a control signal I for setting oscillation start and oscillation stop and an output S1 of the OR circuit 10 are applied, and an output 81 of the OR circuit 10. The configuration includes a delay circuit 12 that delays and transfers the data, and an inversion circuit 14 that feeds back the inverted output S2 of the delay circuit 12 to the OR circuit 10.

The delay circuit 12 may include various integrating circuits, a delay circuit formed by connecting multiple stages of gates in series, and a delay line (Del+
+y Line) etc. are suitable, and furthermore, any circuit that delays and transfers a signal can be applied.

[Function] In the oscillation circuit of the present invention having such a configuration,
When the control signal ■ is inverted to a predetermined logic level, the oscillation operation starts, and the signal S1 output from the OR circuit 10 is inverted and fed back to the input of the OR circuit 0 through the delay circuit 12. A rectangular signal string consisting of a rectangular signal having a predetermined frequency and a predetermined duty ratio with a period of one cycle is output. Further, since the delay circuit 12 functions as a low-pass filter, when the oscillation is stopped, a whisker-like narrow pulse unlike a conventional ring counter does not occur.

[Embodiment] FIG. 2 is an explanatory diagram of an embodiment configuration showing an embodiment of the present invention.

First, to explain the configuration, in FIG. 2, 8 is an AND gate, 10 is an OR gate, 12 is a delay circuit, and 14 is an NA gate.
NDAND gate.

A control signal I is applied to one input contact of the AND gate 10, an output contact is connected to one input contact of the OR gate 12, and an output contact of the OR gate 10 is connected to the AND gate 8.
is connected to the other input contact of the

The output contact of the OR gate is further connected to the human power contact of the delay circuit 120, the output contact of the delay circuit 12 is connected to the input contact of the inverter 14, and the signal appearing at the output contact of the inverter 14 is taken as the output signal Q.

It is also wired so that the output signal Q (same as signal S2) is fed back to the other input contact of the OR gate 10.

Here, in addition to using a delay line for the delay circuit 12, a third
A circuit as shown in the figure and FIG. 4 is applied.

That is, the circuit of FIG. 3 includes a resistor R connected in series between the output contact of the OR gate 10 and the input contact of the inverter 14;
It is an integrating circuit consisting of a capacitor C connected between the output side contact of a resistor R and a ground contact, and the time constant τ=RX
A delay time corresponding to C can be obtained.

Further, each circuit in FIG. 4 has a specific transfer delay time τ. i (even number) inverters N1 to Ni having Therefore, a delay time of j×τ0 is obtained.

Next, the operation of this embodiment will be explained based on the timing chart of FIG.

First, when the control signal I is set to "H" level, the oscillation operation is stopped regularly.

Next, as shown at time tl in the figure, when the control signal I is inverted to the "L" level, the output ISI of the AND gate 8 and the output S1 of the OR gate 10 also become "L" level in synchronization with this. , after the delay time by the delay circuit 12 (time t2 in the figure), an output Q inverted to "H" level is generated from the inverter 4, and the output signal Q becomes the engine signal S2 and is input to the other side of the OR gate 10. Applied to the input contacts.

Furthermore, at time t2, the output S1 of the OR gate 10 is also inverted to "H" level.

Then, the output S1 that has reached the "H" level is held for a period corresponding to the delay time of the delay circuit 12, and then, in synchronization with the feedback signal S2 becoming the "L" level, the output signal Q and the output S1 is also inverted to "L" level.

In this way, by performing a repetitive operation in which the logic level is inverted for each delay time of the delay circuit 12, a rectangular signal string with a duty ratio of 50% in which one cycle is twice the delay time is obtained as the output signal Q. .

Next, the operation when oscillation stop is set will be explained. For example, when the control signal ■ is brought to the "H" level in synchronization with the inversion of the output Q (see time t3 in FIG. 5), the output Q The rectangular signal no longer appears.

Note that at time t3, the feedback signal S2 becomes "L" level, so the final output becomes "H" level.

Further, if the oscillation is set to stop when the engine signal S2 goes to "H" level as at time t4 in the figure, it goes to "L" level at time tl after a delay time, and oscillation stops thereafter. Furthermore, when the control signal ■ is set to "H" level at time t5 when the final rectangular signal Q in the figure has finished being generated, the output Q after the next delay time becomes 0 "L" level and thereafter the oscillation operation starts. is not performed, so no rectangular signal appears after time t5 as shown in the figure.

Furthermore, if the control signal I is set to the "H" level at any time between time t3 and t4, this level change will be input to the AND circuit 8 at time t4, so as a result, as shown in the figure. Oscillation stops at time t5. Similarly, time t
If the control signal I is set to "H" level at any time between 4 and t5, this level change will be input to the AND circuit 8 at time t5, so as a result, as shown in the figure, at time t, oscillation stops.

In this way, it is possible to set the oscillation stop at any point one cycle before the oscillation stop time, making it extremely easy to control the oscillation period and eliminating pulses with noise components like in conventional ring counters. Does not occur.

Further, it is possible to obtain a rectangular signal train in which each rectangular signal has an extremely steep rise.

[Effects of the Invention] 1 As explained above, according to the present invention, the AND circuit to which the control signal for setting oscillation start and oscillation stop and the output of the OR circuit are applied, and the output of the OR circuit Since the configuration includes a transfer circuit that transfers data with a delay and an inverting circuit that feeds back the inverted output of the delay circuit to the OR circuit, it is easy to set the oscillation period, and a uniform rectangular signal string is always generated during that period. Furthermore, since each rectangular signal has a steep rise, it is possible to apply an oscillation circuit suitable for use as a reference clock of a digital system, thereby realizing a power-saving digital system. I can do it.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the principle of the present invention; Fig. 2 is an explanatory diagram of the configuration of an embodiment of the present invention; Fig. J is an explanatory diagram of the configuration of a specific example of a delay circuit in the embodiment;
Figure 5 is an explanatory diagram of the configuration of another specific example of the delay circuit in the embodiment: Figure 5 is an explanatory diagram of the operation of the embodiment; 2 Figure 6 is an explanatory diagram of the configuration of the conventional example; Figure 7 is an explanatory diagram of the operation of the conventional example. It is. Symbols in the figure: 8: AND circuit, AND gate 10: OR circuit, OR gate 12: delay circuit 14: inversion circuit, inverter R: resistor C: capacitor N1 to Ni: inverter

Claims (1)

[Claims] An AND circuit (8) to which a control signal (1) for setting oscillation start and oscillation stop and an output (IS1) of the OR circuit (10) are applied; A delay circuit (12) delays and transfers the output (IS1) of the delay circuit (10), and an OR circuit (
10) An oscillation circuit characterized by comprising an inverting circuit (14) that feeds back to the oscillation circuit.