JPH0366171A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To stabilize a characteristic and to realize a high performance by reducing an etching residue, by enhancing a yield and by enhancing an accuracy of a processed size by a method wherein a second gate insulating film whose film thickness is thinner than that of a first gate insulating film and a whole-surface etching treatment is executed in order to remove the second gate insulating film in a second region by a portion corresponding to this film thickness. CONSTITUTION:In respective formation regions of a memory cell Qm, a low-dielectric- breakdown-strength MISFET Ql and a high-breakdown-strength MISFET Qh, a p<-> type well region 2 is formed on a main face part of a p<-> type semiconductor substrate 1. In an interelement isolation region (nonactive region), a field insulating film (insulating film for element isolation use) 3 and P-type channel stopper regions 4 are formed on a main face of the well region 2. When a high voltage is applied during an information-erasing operation, a source region increases an impurity concentration in an n<+> type semiconductor region 13 so as not to be depleted, increases a diffusion amount to the side of a channel formation region by the n<+> type semiconductor region 13 of a high impurity concentration or by an n-type semiconductor region 14 of a low impurity concentration or by both, increases an overlap area with a gate electrode 8 for information storage use and increases an area of an electric current route of a tunnel current during the information-erasing operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a semiconductor integrated circuit device having a nonvolatile memory function.

[Conventional technology]

Electrically erasable non-volatile memory device
llyErasable Programmable
As a read only memory, there is a so-called flash (F1ash) type in which a memory cell is formed of one field effect transistor and information in bits or bytes can be written and erased all at once.

The memory cells are arranged at intersections of data lines and word lines within the memory cell array. A memory cell, that is, a field effect transistor has a gate electrode for information storage (floating gate electrode) and a gate electrode for control (control group 1 to electrode). The drain region of this field effect transistor is connected to the data line, the control gate electrode to the word line, and the source region to the source line.

In a memory cell employing this flash structure, information is written by injection of hot electrons, and information is erased by tunnel emission of electrons.

In the electrically erasable nonvolatile memory device configured in this way, the memory cell is configured with one field effect transistor, so the memory cell area can be reduced and high integration or capacity can be achieved. can.

The electrically erasable nonvolatile memory device has two types of field effect transistors (MISFETs) arranged in peripheral circuits such as a decoder circuit in addition to memory cells.

One MISFET is arranged for the purpose of performing a high-speed information read operation, normally operates within an operating power supply voltage range of, for example, approximately 5 [V], and has a low dielectric strength voltage.

The other MISFET is arranged for the purpose of performing an information writing operation and an information erasing operation, and is operated at a high voltage, for example, about 10 to 1
It operates in the range of 5 [V] and has high dielectric strength.

3- The gate electrode of the low dielectric breakdown voltage MISFET is formed of the same conductive layer as the control gate electrode of the field effect transistor which is the memory cell. The control gate electrode can be formed of a gate material having a lower resistance than the information storage gate electrode, such as a polycide film. In other words, the operating speed of the MISFET with low dielectric strength can be increased.

The information storage gate electrode is generally formed of a polycrystalline silicon film. A polycrystalline silicon film allows a stable and high-quality silicon oxide film with little variation in dielectric strength to be formed on its surface. That is, this silicon oxide film is used as a gate insulating film between the information storage gate electrode and the control gate electrode.

The gate electrode of the high dielectric breakdown voltage MISFET is formed of the same conductive layer as the information storage gate electrode of the field effect transistor which is the memory cell.

The information storage gate electrode is formed in a manufacturing process prior to forming the low dielectric breakdown voltage MISFET. MISFETs with high dielectric breakdown voltage require a long annealing process during the manufacturing process, such as forming a semiconductor region with a low impurity concentration that increases the pn junction breakdown voltage, especially on the drain region side. That is, a high dielectric strength MISFET is formed at the front stage of the manufacturing process for the purpose of shallowing the pn junction depth of each of the source region and the rain region of a low dielectric strength MISFET. MISFE with low dielectric strength in which the source region and drain region are each formed with a shallow pn junction depth
T can ensure a sufficient channel length and suppress short channel effects. In addition, low dielectric strength MISFET
The parasitic pn junction capacitance added to each of the source region and drain region can be reduced.

The general manufacturing method of this electrically erasable nonvolatile memory device is as follows.

First, a field insulating film (a thick device isolation insulating film) is formed on the main surface of an inactive region of a semiconductor substrate.

Next, a thick first gate insulating film is formed on the main surface of the active region of the semiconductor substrate in each of the formation regions of the memory cell, the low dielectric strength MISFET, and the high dielectric strength MISFET. This first gate insulating film has a high dielectric strength of M
It is used as a gate insulating film of ISFET, for example, 25
It is formed with a film thickness of ~40 [nm].

Next, in the memory cell formation region, the first gate insulating film is selectively removed by photolithography (including etching).

Next, in this memory cell formation region, a thin second gate insulating film is formed on the main surface of the active region of the semiconductor substrate. This second gate insulating film is used as a gate insulating film of a field effect transistor which is a memory cell. This second gate insulating film is formed as a so-called tunnel silicon oxide film with a thickness of, for example, 10 [nm].

Next, an information storage gate electrode is formed on the second gate insulating film in the memory cell formation region, and a high dielectric strength M
A layer of goo 1- is placed on the first gate insulating film in the ISFET formation region.
Form an electrode. In this step, the information storage goo 1 to electrode are processed only in the gate width direction (channel width direction).

Next, in the formation region of the low dielectric breakdown voltage MISFET,
The first gate insulating film remaining only in this region is removed. The first gate insulating film is removed by etching the entire surface of the substrate including each formation region in order to reduce the number of masks during the manufacturing process.

At this time, the second gate insulating film underlying the memory cell formation region is protected by the information storage gate electrode. Similarly, in the formation region of the high breakdown voltage MISFET, the first gate insulating film underlying the gate electrode is protected. The etching process uses isotropic etching, for example, in order to reduce damage to the main surface of the active region of the semiconductor substrate.

Next, in the formation region of this low dielectric breakdown voltage MISFET, a third gate insulating film is formed on the main surface of the active region of the semiconductor substrate. A fourth gate insulating film is formed on the surface of the information storage gate electrode in the memory cell formation region by the same process as that for forming the third gate insulating film.

Next, a control gate electrode is formed on the fourth gate insulating film in the memory cell formation region, and a gate electrode is formed on the third gate insulating film in the low supply voltage MISFET formation region. The control gate electrode is processed, for example, by anisotropic etching, and using this control gate electrode as a mask, the underlying information storage gate electrode is processed in the gate length direction. That is, each of the information storage gate electrode and the control gate electrode of a field effect type 1-transistor which is a memory cell is processed by so-called overlap cutting. The gate electrode of the low dielectric breakdown voltage MISFET is processed in a process different from the overlapping cutting.

Next, in each formation region, a source region and a drain region are formed on the main surface of the active region of the semiconductor substrate. Through this process, each of the memory cell, the low dielectric breakdown voltage MISFET, and the high dielectric breakdown voltage MISFET is completed.

Regarding non-volatile storage devices, for example, Japanese Patent Application No. 1983-
No. 284587.

[Problem to be solved by the invention]

The inventors of the present invention have discovered that the following problems occur with the above-mentioned electrically erasable nonvolatile memory device.

In the manufacturing process of the electrically erasable nonvolatile memory device, there is a step of removing the first gate insulating film in the formation region of the low breakdown voltage MISFET.

The first gate insulating film is formed of a thin Pi film which forms a gate insulating film of a high breakdown voltage MISFET, and is removed by etching the entire surface without using a mask. In other words, this entire surface etching process removes the first gate insulating film in the region where the low dielectric breakdown voltage MISFET is formed, but the information storage gate electrode and the high dielectric breakdown voltage MISFET are removed.
The surface of the field insulating film that is not covered by each of the gate electrodes of the ET is also removed by an amount corresponding to the thickness of the first gate insulating film. With this removal of the surface of the field insulating film, an overhang portion is generated on the surface of the field insulating film, particularly under the end of the information storage gate electrode in the memory cell formation region. A gate electrode material is deposited within this overhang portion when a control gate electrode is deposited. This gate electrode material is difficult to remove in the anisotropic etching process when cutting the control gate electrode and the information storage gate electrode overlappingly, so that etching residue is likely to occur.

For this reason, the control gate electrodes of memory cells arranged in the extending direction of the data lines (corresponding to the word lines) are short-circuited through the etching residue in the overhang part, which reduces the manufacturing yield. There was a problem.

Further, the etching residue on the overhang portion can be removed by increasing the amount of side etching when processing the control gate electrode.

However, an increase in the amount of side etching causes a problem in that the processing dimensional accuracy of the control gate electrode and the information storage gate electrode, which particularly require fine processing, is reduced.

Further, the increase in the amount of side etching particularly changes the cross-sectional shape of the control gate electrode, the information storage gate electrode, etc. from a rectangular shape to a shape close to a trapezoid shape.

Although not limited to this element, a field effect transistor which is a memory cell uses each of a control gate electrode and an information storage gate electrode as an impurity introduction mask, and forms a source region and a drain region in self-alignment with the control gate electrode and information storage gate electrode. do. Therefore, variations occur in the overlapping of the information storage gate electrode and the control gate electrode with the source region and the drain region, or the impurity concentration particularly on the channel forming region side of the drain region changes. In other words, a problem arises in that the electrical characteristics of the memory cell, such as information writing operations, become unstable. In addition, there may be slight variations in the channel length dimensions of field effect transistors, which are memory cells, resulting in problems such as short channel effects, which deteriorate the performance of the memory cells.

An object of the present invention is to provide a technique that can improve manufacturing yield in a semiconductor integrated circuit device having a nonvolatile memory circuit.

Another object of the present invention is to provide a technique capable of improving processing dimensional accuracy in the semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of stabilizing the characteristics of an element and improving the performance of the element in the semiconductor integrated circuit device.

Another object of the present invention is to provide a technique that can reduce the number of manufacturing steps in the semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In a method of manufacturing a semiconductor integrated circuit device having an electrically erasable or ultraviolet erasable nonvolatile memory function, a first region (memory cell), a second region (low dielectric breakdown voltage MISFET), and a third region (low dielectric breakdown voltage MISFET), which are different from each other, of a semiconductor substrate are provided. High dielectric strength MIS
forming a first gate insulating film on each main surface of the FET;
The first gate insulating film in the second region or the first region and the second region is removed, and the second region or the first gate insulating film of the semiconductor substrate is removed.
A second gate insulating film having a thickness thinner than that of the first gate insulating film is formed on the main surface of the region and the second region.
forming an information storage gate electrode on the second gate insulating film in the region or on the first gate insulating film in the first region, and forming a gate electrode on the first gate insulating film in the third region; Etching is performed on the entire surface including the first region, second region, and third region, the second gate insulating film formed in the second region is removed, and the second gate insulating film formed on the second region is removed. At the same time as forming a third gate insulating film, a fourth gate insulating film is formed on the information storage gate electrode in the first region, and a control gate electrode is formed on the fourth gate insulating film in the first region. and forming a gate electrode on the third gate insulating film in the second region.

[Function] According to the above-described means, a second gate insulating film having a thinner film thickness than the first gate insulating film is formed on the main surface of the second region (low dielectric breakdown voltage MISFET) of the semiconductor substrate. , this second
Equivalent to the thickness of the gate insulating film (based on this film thickness)
, since the entire surface etching process was performed to remove the second gate insulating film in the second region, the etching process formed on the surface of the base insulating film (field insulating film) especially at the end of the information storage gate electrode It is possible to reduce the size of the overhang caused by the processing and reduce etching residue remaining when the control gate electrode is formed in the overhang. As a result, it is possible to prevent short circuits between adjacent control gate electrodes (between word lines) due to the etching residue, thereby improving the manufacturing yield of semiconductor integrated circuit devices with non-volatile memory functions. be able to.

Further, by reducing the etching residue, it is possible to eliminate the side etching process for removing the etching residue, so that it is possible to particularly improve the processing dimensional accuracy of the control gate electrode.

Furthermore, by reducing the etching residue, it is possible to particularly improve the anisotropy of the etching process for processing the control gate electrode. By reliably and stably superimposing each of these elements, or by stably securing the channel length dimension, it is possible to stabilize the characteristics or improve the performance of the field effect transistor (memory cell).

Furthermore, since the etching residue can be reduced by simply changing the pattern of the mask for removing the first evaporation insulating film, the manufacturing process of the semiconductor integrated circuit device is The number can be reduced.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below along with an embodiment in which the present invention is applied to a semiconductor integrated circuit device equipped with an electrically erasable non-volatile memory circuit (EEPROM) employing a flash structure.

Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

The configuration of an EEPROM that is an embodiment of the present invention is shown in Figure 1 (
(Cross-sectional view of main parts) Figure 1 shows a flash type memory cell on the left, a low dielectric strength MISFET that makes up the peripheral circuit in the center, and a high dielectric strength MISFET on the right.
ET. The peripheral circuit is a complementary MI SF
Although it is composed of an ET (CMO8), only the n-channel MISFET will be explained in this embodiment.

As shown in the drawing, the EEPROM is composed of a p-type semiconductor substrate 1 made of single-crystal high silicon. Memory cell 0m,
Low dielectric strength MISFET (Ml, high dielectric strength MISFE
In each formation region of TQh, a p-type well region 2 is provided on the main surface of the ]-type semiconductor substrate 1 . Although not shown, in the p-channel MISFET formation region, p
A type 1 well region is provided on the main surface of the − type semiconductor substrate 1 .

In the element isolation region (inactive region), a field insulating film (element isolation insulating film) 3 and a p-type channel stopper region 4 are provided on the main surface of the p-type well region 2.

A memory cell 0m employing a flash structure is formed on the main surface of the p-type well region 2 within a region defined by the field insulating film 3 and the p-type channel stopper region 4. The memory cell 0m is composed of one field effect transistor and stores 1 [bitl] of information. In other words, memory cell 0m has p-type well region 2,
p° type semiconductor region 15, gate insulating film 7, gate electrode for information storage (floating gate electrode) 8, gate insulating film 1o, gate electrode for control (control gate electrode)
11. It consists of a source region and a drain region.

Each of the f-type well region 2 and the p°-type semiconductor region 15 is used as a channel forming region. Of these, the p° type semiconductor region 15 is provided mainly to increase the electric field strength near the drain region and improve the information writing efficiency.

The gate insulating film 7 is formed of a silicon oxide film formed by oxidizing the surface of the p-type well region 2. This gate insulating film 7
is used as a tunnel silicon oxide film, so for example 6
It is formed with a thin film thickness of ~12 [nm].

The information storage gate electrode 8 is formed of a polycrystalline silicon film, and an n-type impurity such as P is introduced into the polycrystalline silicon film to reduce the resistance value. This polycrystalline silicon film is deposited by, for example, a CVD method, and is formed to have a thickness of about 200 [nm].

The gate insulating film 10 is formed of, for example, a silicon oxide film obtained by oxidizing the surface of the information storage gate electrode 8 (polycrystalline silicon film). The gate insulating film 10 is formed to have a thickness of, for example, about 20 to 25 [nm].

Control gate electrode 11 is formed of a polycrystalline silicon film, and P is introduced into this polycrystalline silicon film. The polycrystalline silicon film is deposited by, for example, the CVD method, and has a film thickness of 300 nm to reduce the resistance value.
It is formed with a thick film thickness of about [nm]. Further, the control gate electrode 11 may be formed of a single layer of a high melting point metal film or a high melting point metal silicide film, or a composite film (polycide film) in which these metal films are laminated on a polycrystalline silicon film. .

The control gate electrode 11 is the control gate electrode 11 of another memory cell 0m arranged adjacent to the control gate electrode 11 in the gate width direction.
and constitutes a word line (WL).

The source region is composed of an n-type semiconductor region 13 with a high impurity concentration and an n-type semiconductor region 14 with a low impurity concentration provided along the periphery thereof. In other words, the source region has a so-called double diffusion structure. The d-type semiconductor region 13 with high impurity concentration is mainly configured to increase the impurity concentration and deepen the junction depth. The n-type semiconductor region 14 with a low impurity concentration is mainly configured to increase the junction depth. That is, the impurity concentration of the source region is increased in the d-type semiconductor region 13 so that the surface is not depleted when a high voltage is applied between the source region and the control gate electrode 11 during an information erasing operation. In addition, the source region is an n-type semiconductor region 13 with a high impurity concentration or an n-type semiconductor region 14 with a low impurity concentration.
Alternatively, by both of them, the amount of diffusion (diffusion distance) toward the channel forming region side is increased, the overlapping area with the information storage gate electrode 8 is increased, and the area of the current path of the tunnel current during the information erasing operation is increased. Each of the semiconductor regions 13 and 14 is formed in self-alignment with the information storage gate electrode 8 and the control gate electrode 9.

The drain region includes an n-type semiconductor region 19 20- region 16 with a low impurity concentration and an n-type semiconductor region 18 with a high impurity concentration. The n-type semiconductor region 16 with a low impurity concentration in the drain region can particularly control information writing characteristics. This low impurity concentration n-type semiconductor region 16 has a low impurity concentration and a shallow junction depth compared to the high impurity concentration n-type semiconductor region 13 of the source region, but hot electrons are generated during write operation. Contains a concentration that is sufficient to generate

That is, during a write operation, the drain region mainly maintains the generation of hot electrons in the n-type semiconductor region 16 with a low impurity concentration in the selected memory cell 0m, and in the vicinity of the drain region in the unselected memory cell 0m. The structure is designed to reduce the electric field strength and reduce the generation of hot holes. In addition, the drain region mainly uses the n-type semiconductor region 16 with a shallow junction depth to reduce the amount of diffusion toward the channel forming region side, reduce the overlapping area with the information storage gate electrode 8, and The coupling capacitance formed between the gate electrode 8 and the gate electrode 8 can be reduced. The n-type semiconductor region 16 serves as the information storage gate electrode 8 and the control gate electrode 1.
It is formed in self-alignment with respect to 1.

The A-shaped semiconductor region 18 is formed in self-alignment with the sidewall spacer 17, which is formed in self-alignment with the information storage gate electrode 8 and the control gate electrode 11.

This drain region is a so-called LDD (Lightly Do
It consists of a ped drain) structure.

A wiring (data line D
L) 21 is connected. The wiring 21 extends on the interlayer insulating film 19 and connects to the connection hole 20 formed in the interlayer insulating film 19.
It is connected to the square shaped semiconductor region 18 through. The wiring 21 is formed of, for example, an aluminum alloy film. The source region is connected to a source line (not shown).

Low dielectric strength MIS that constitutes peripheral circuits such as decoder circuits
FETQI2 is operated within a normal circuit operating voltage range of, for example, 5 [V]. This low dielectric strength MISFET
(L is defined by the field insulating film 3 and the p-type channel stopper region 4, and is formed on the main surface of the V-type well region 2. In other words, the low dielectric breakdown voltage MISFET Qα is defined by the p-type channel stopper region 4.
- type well region 2, gate insulating film 9, gate electrode 11.
It is composed of a pair of n-type semiconductor region 16 and d-type semiconductor region 18, which are a source region and a drain region.

The gate insulating film 9 is formed of a silicon oxide film formed by oxidizing the surface of the p-type well region 2, and has a thickness of, for example, 15 to 20
It is formed with a thin film thickness of about [nm].

The gate electrode 11 is connected to the memory cell 0 in order to increase the operating speed.
It is formed of the same conductive layer as the control gate electrode 11 of m.

The source region and drain region have an LDD structure. - A wiring 21 is connected to this d-type semiconductor region 18 of the low dielectric strength MISFET Q.

The high dielectric breakdown voltage MISFETQh used in the information write operation and information read operation has a high voltage, for example, 10 to 15 [V].
It is operated within the range of . High dielectric strength MISFETQ
h is defined by the field insulating film 3 and the P-type channel stopper region 4 and is formed on the main surface of the P-type well region 2 . In other words, the high dielectric strength MISFETQh has p
It is composed of a − type well region 2, a gate insulating film 6, a gate electrode 8, a source region, and a drain region.

The gate insulating film 6 is formed of, for example, a silicon oxide film formed by oxidizing the surface of the i-type well region 2, and has a thickness of 25 to 40[n].
It is formed with a thick film thickness of about m1.

The gate electrode 8 is an information storage gate of the memory cell 0m formed at the front stage during the manufacturing process in order to place less emphasis on high speed than the low dielectric breakdown voltage MISFET (1) and to increase the pn junction breakdown voltage of the drain region. It is formed of the same conductive layer as the electrode 8.The source region is an n-type semiconductor region 1 with a low impurity concentration.
6 and a d-type semiconductor region 18 with a high impurity concentration. In other words, the source region has an LDD structure. The drain region is composed of an n-type semiconductor region 16 with a low impurity concentration, a d-type semiconductor region 18 with a high impurity concentration, and an n-type semiconductor region 5 with a low impurity concentration. The n-type semiconductor region 5 with a low impurity concentration is provided along the periphery of the n-type semiconductor region 16 and the d-type semiconductor region 18, and is provided to increase the pn junction breakdown voltage of the drain region. This n-type semiconductor region 5 constitutes a drain region with a double diffusion structure. This high dielectric strength M
A wiring 21 is connected to the 23 24 n-type semiconductor region 18 of the ISFETQh.

Next, the method for manufacturing the above-mentioned EEPROM will be briefly explained using FIGS. 2 to 8 (cross-sectional views of main parts shown for each manufacturing process).

First, a p-type semiconductor substrate 1 is prepared.

Next, the memory cell Qm, the low supply voltage withstand voltage MISFETQQ,
In each formation region of the high breakdown voltage MISFETQh, a p-type well region 2 is formed on the main surface of the p-type semiconductor substrate 1. Note that the p-channel MISFE of the p-type semiconductor substrate 1 is manufactured using almost the same manufacturing process as that of the p-type well region 2.
A mold well region is formed on the main surface of the T formation region.

Next, a field insulating film 3 is formed on the main surface of the inactive region of the p-type well region 2 (including the n-type well region), and a p-type channel stopper region 4 is formed on the main surface. The field insulating film 3 is formed of a silicon oxide film obtained by oxidizing the surface of the p-type well region 2, and has a thickness of, for example, 400 to 700[n].
The film is formed with a film thickness of about 1.0 m.

Next, as shown in Figure 2, a high dielectric strength MISFETQ
A gate insulating film (first gate insulating film) 6 is formed over the entire main surface of the active region of the P-type well region 2, including the formation region h. The gate insulating film 6 is formed to have a thick film thickness of, for example, about 30 [nm].

This gate insulating film 6 has a memory cell of 0 m and a low dielectric breakdown voltage MI.
It is also formed on the main surface of the p-type well region 2 in each formation region of the SFET.

Next, excluding the formation region of the high dielectric strength MISFETQh,
The gate insulating film 6 is removed in each of the formation regions of the memory cell 0m and the low dielectric breakdown voltage MISFET l. The gate insulating film 6 is removed by, for example, an isotropic etching (wet etching) technique using a low concentration HF aqueous solution. When removing the gate insulating film 6, high dielectric strength MIS
The gate insulating film 6 in the formation region of the FETQh is protected with a mask (for example, a photoresist film 30) (see FIG. 3).
.

Next, as shown in FIG. 3, a gate insulating film (second gate insulating film) 1 is formed in each of the formation regions of the memory cell 0m and the low dielectric breakdown voltage MISFET QQ from which the gate insulating film 6 has been removed. Since the gate insulating film 7 is mainly used as a tunnel silicon oxide film, the thickness of the gate insulating film 7 is, for example, 10 [nm1
By forming the gate insulating film 7 with a relatively thin film thickness, the high dielectric strength voltage M I S F E
The thickness of the gate insulating film 6 in the region where T Q b is formed is approximately 35 mm.
It can grow to about [nm].

Next, an information storage gate electrode 8 is formed on the gate insulating film 7 in the formation region of the memory cell 0m, and a gate electrode 8 is formed on the gate insulating film 6 in the formation region of the high breakdown voltage MISFETQh. In this step, the information storage gate electrode 8 is processed only in the gate width direction (channel width direction). Further, the gate electrode 8 is processed in the gate width direction and the gate length direction. Each of the information storage gate electrode 8 and the gate electrode 8 is processed by anisotropic etching.

Next, in the formation region of the drain region of the high breakdown voltage MISFETQh, an n-type impurity 5n, for example, P, is introduced into the main surface of the p-type well region 2 by ion implantation. This n-type impurity 5n is, for example, 1013 [atoms/
The impurity concentration is about cfn2] and is introduced by ion implantation.

Next, as shown in FIG.
Gate insulating film 7 is removed in the region where III is to be formed. This removal of the gate insulating film 7 is performed by etching the entire surface in order to reduce the number of masks in the 112'/Ii process. That is, the etching process is performed on the entire surface of the substrate including the formation regions of the low dielectric breakdown voltage MISFETQ, the memory cell 0m, and the high dielectric breakdown voltage MISFETQh. The gate insulating film 7 in the formation region of the memory cell 0m is protected by the information storage gate electrode 8, and the gate insulating film 6 in the formation region of the high dielectric breakdown voltage MISFETQh is protected by the gate electrode 8. The entire surface etching process is performed, for example, by an isotropic etching technique using an HF aqueous solution.

The thickness of the gate insulating film 7 in the formation region of this low dielectric breakdown voltage MISFET (1) is approximately 1/3 of that of the gate insulating film 6.
Since the gate insulating film 7 is formed with the following thin film thickness, the amount of etching required when removing the gate insulating film 7 is small. In other words, the amount of etching of the gate insulating film 7 is about 10 [nm], and the amount of etching of the surface of the field insulating film 3 is smaller. As a result, within the area shown by the dotted line in FIG.
In the formation region m, it is possible to reduce the overhang portion 3A that occurs on the surface of the end portion of the information storage gate electrode 8 of the field insulating film 3.

Next, in the formation region of the low breakdown voltage MISFET (Ill), a gate insulating film (third gate insulating film) 9 is formed on the main surface of the P-type well region 2. Along with this step,
In the formation region of the memory cell 0m, a gate insulating film (fourth gate insulating film) 1 is formed on the surface of the information storage gate electrode 8.
form 0. The gate insulating film 9 has a thickness of, for example, 17.5[
The gate insulating film 10 is formed to have a thickness of about 25 [nm], for example. Each of the gate insulating films 9 and 10 is formed of, for example, a silicon oxide film formed by oxidizing the respective silicon surfaces.

Next, as shown in FIG. 5, an information storage gate electrode 11 is placed on the gate insulating film 10 in the formation region of the memory cell 0m.
At the same time, a gate electrode 11 is formed on the gate insulating film 9 in the formation region of the low breakdown voltage MISFETQQ.

- In this step, the control gate electrode 11 has not yet been processed in the gate width direction and the gate length direction, and as a result is formed over the entire area of the memory cell array. The gate electrode 11 is processed in the gate width direction and the gate length direction. In addition, as shown in FIG. 5, high dielectric strength MISFETQ
In the formation region h, the n-type impurity 5n introduced in the previous step is slightly diffused, and the n-type semiconductor region 5 is formed.

Next, in the formation region of the memory cell 0m, the control gate electrode 11 is processed in the gate length direction.

Then, using this control gate electrode 11 as a mask, the information storage gate electrode 8 below it is processed in the gate length direction. This control gate electrode 11. Each of the information storage gate electrodes 8 is processed using an anisotropic etching technique, and is performed by so-called overlap cutting. Thereafter, a thermal oxidation process is performed to form an insulating film 12 covering each surface of the information storage gate electrode 8, the control gate electrode 11.degree. gate electrode 8.11, as shown in FIG. This insulating film 12 is the memory cell 0
It is used for the purpose of improving the information retention characteristics of m. Same 6th
Although not shown in the figure, at the end in the gate width direction of the information storage gate electrode 8 of the memory cell 0m, the overhang portion 3A is hardly formed on the surface of the field insulating film 3 as described above. Therefore, even if the control gate electrode 11 is deposited and processed by anisotropic etching, no gate electrode material remains in the overhang portion 3A (
(no etching residue).

Next, in the formation region of the source region of memory cell 0m, n-type impurities 13n, 1
Introduce each of 4n. The n-type impurity 13n is, for example, 1
As is used at an impurity concentration of about 0'' to 10''[atoms/an''] and introduced by ion implantation with an energy of about 60 [K e Vl.N-type impurity 1
4n is 1, for example, 10” to 101s [atoms/an
P is used at an impurity concentration of approximately 50 [KeV] and is introduced by ion implantation with an energy of approximately 50 [KeV].

Next, a P-type impurity 15p is introduced into the main surface of the p-type well region 2 in the formation region of the drain region of the memory cell 0m. The p-type impurity 15p is 1, for example 1013-10
BF2 with an impurity concentration of about 14 [atoms/cm2]
It is introduced by ion implantation with an energy of about 60 [K e V].

Next, as shown in FIG. 7, n-type impurities 16n are introduced into the main surface of the p-type well region 2 in the formation regions of the memory cell 0m, the low dielectric breakdown voltage MISFETQ, and the high dielectric breakdown voltage MISFETQh.

In the formation region of memory cell 0m, n-type impurity 16n
For example, As is used at an impurity concentration of about IQ" [atoms/am2] and is introduced by an ion implantation method with an energy of about 60 [KeV].Low dielectric breakdown voltage MISFE
In each formation region of TQQ and high dielectric breakdown voltage MI 5FETQh, the n-type impurity 16n is, for example, 10" [at
Using P with an impurity concentration of about 50
It is introduced by an ion implantation method with an energy of about [KeV].

Each of the introduced impurities is diffused by an annealing treatment performed thereafter to form a semiconductor region. In other words, the n-type impurity 13n is
, the n-type impurity 14n forms the n-type semiconductor region 14, the p-type impurity 15n forms the final-type semiconductor region 15, and the n-type impurity 16n forms the n-type semiconductor region 16.

Next, gate electrode 8 for information storage, control goo 1 to electrode 1
Sidewall spacers 17 are formed on each sidewall of L gate electrode 8.11. The sidewall spacer 17 is formed, for example, by depositing a silicon oxide film over the entire surface of the substrate by the CVD method, and then performing anisotropic etching such as RIE over the entire surface of the substrate by an amount corresponding to the thickness of the deposited film.

Next, memory cell 0m, low dielectric breakdown voltage MISFETQQ,
In each formation region of the high breakdown voltage MISFETQh, an n-type impurity 18n is introduced into the main surface portion of the P-type well region 2. The n-type impurity 18n is, for example, 1015 to 10"
As is used at an impurity concentration of about [:atoms/cm2] and introduced by ion implantation with an energy of about 60 [KeV]. This n-type impurity 18n is diffused by performing an annealing treatment, and is diffused in the d-type semiconductor region 18. form.

Next, the glabella insulating film 19, the connection hole 20, and the wiring 21 are formed in sequence, thereby completing the EEPROM of this embodiment shown in FIG. Although not shown, the wiring 2
An upper layer wiring and a passivation film are provided on the top of the semiconductor device 1.

In this way, in the EEFROM, different memory cells in the p-type well region 2, low dielectric breakdown voltage MISF
A gate insulating film 6 is formed on the main surface of the formation region of the ETQll and high dielectric breakdown voltage MISFETQh, and the gate insulating film 6 in the formation region of the memory cell Qm and low dielectric breakdown voltage MISFETQfl is removed. mold well area 2
A gate insulating film 7 having a thinner film thickness than the gate insulating film 6 is formed on the main surface of each forming region of the memory cell 0m and the low line edge pressure MISFETQQ.
An information storage gate electrode 8 is formed on the gate insulating film 7 in the formation region of the high dielectric breakdown voltage MISFETQh.
A gate electrode 8 is formed on the gate insulating film 6 in the formation region of the memory cell 0m, the low dielectric breakdown voltage MISFETQQ,
Etching is performed on the entire surface including the formation region of each high dielectric breakdown voltage MISFETQh, and the low dielectric breakdown voltage MISFETQh is etched.
The gate insulating film 7 in the TQk formation region is removed, and the gate insulating film 9 is formed on the main surface of the low dielectric breakdown voltage MISFETQQ formation region in this p-type well region 2, and information on the formation region of the memory cell 0m is removed. A gate insulating film 10 is formed on the storage gate electrode 8, a control gate electrode 11 is formed on the gate insulating film 10 in the region where the memory cell 0m is formed, and a gate insulator is formed in the region where the low breakdown voltage MISFET QII is formed. A step of forming a gate electrode 8 on the film 9 is provided.

With this configuration, the game insulating film 6 is formed on the main surface of the formation region of the low dielectric breakdown voltage MISFET QQ in the p-type well region 2.
A gate insulating film 7 having a thinner film thickness than that is formed, and an amount corresponding to the film thickness of this gate insulating film 7 (based on this film thickness),
Since the entire surface etching process was performed to remove the gate insulating film 7 in this formation region of the low dielectric breakdown voltage MI S FETQ, the etching process was performed to remove the gate insulating film 7 formed on the surface of the field insulating film 3, especially at the end of the information storage gate electrode 8. It is possible to reduce the size of the overhang caused by the etching process and reduce the etching residue remaining when the control gate electrode 11 is formed in the overhang. As a result, it is possible to prevent short termination between adjacent control gate electrodes 11 (between word lines) due to the etching residue, thereby improving the manufacturing yield of EEPROM.

In addition, by reducing the etching residue, it is possible to eliminate the side etching process for removing the etching residue, which particularly improves the processing dimensional accuracy of the control gate electrode 11 and the information storage gate electrode 8 of the memory cell 0m. can be improved.

Furthermore, by reducing the etching residue, it is possible to particularly increase the anisotropy of the etching process for processing the control gate electrode 11, so that the information storage gate electrode 8, the control gate electrode 11, and the source region can be improved. , the drain regions can be reliably and stably overlapped with each other, or the channel length dimension can be stably ensured, and the characteristics of the memory cell 0m can be stabilized or the high performance can be improved.

Further, the reduction of the etching residue can be achieved by
This can be done by simply changing the pattern of the mask 30 that removes the above, so the number of manufacturing steps for the EEPROM can be reduced by the amount corresponding to the manufacturing steps required to achieve the above effect.

In addition, since the memory cell 0m that adopts a flash structure has a process of forming a gate insulating film 7 with a very thin film thickness of about 10 [nm] as a tunnel silicon oxide film, this gate insulating film 7 is used as a low dielectric breakdown voltage MISFET. (By forming the overhang portion 3A in the formation region 1, it is possible to reduce the size of the overhang portion 3A described above without increasing the number of manufacturing steps.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, the present invention can be applied to an ultraviolet erasable read-only nonvolatile memory circuit (El"'ROM).

When the present invention is applied to an EPROM, the gate insulating film of the memory cell uses the same thick gate insulating film as the gate insulating film of the MISFET, which has a high dielectric strength. Only the MISFET forming region is etched.

The present invention also provides a FLOTOX type EEPROM having a thin tunnelable gate insulating film in a part of the gate insulating film.
It can also be applied to

Furthermore, the present invention provides the above-mentioned EEPROM and EPRO
The present invention can be applied to semiconductor integrated circuit devices such as microcomputers equipped with M.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device having a nonvolatile memory circuit, manufacturing yield can be improved.

In the semiconductor integrated circuit device, processing dimensional accuracy can be improved.

In the semiconductor integrated circuit device, the characteristics of the cable can be stabilized and the performance of the element can be improved.

In the semiconductor integrated circuit device, the number of manufacturing steps can be reduced.

[Brief explanation of drawings]

FIG. 1 shows E r' RO which is an embodiment of the present invention.
2 to 8 are cross-sectional views of main parts showing the structure of the EEPR shown in each manufacturing process.
It is a sectional view of the main part of OM. In the figure, 2... p-type well region, 6, 7, 9. 10...
・Gate insulating film, 8, 11... Gate electrode, 5, 1
3.14°15, 16.18...semiconductor region, Qm・
・・Memory cell, Q flood・・Low dielectric strength MISFET,
Qh...High dielectric strength MISFET.

Claims (1)

[Claims] 1. In a method for manufacturing a semiconductor integrated circuit device having an electrically erasable or ultraviolet erasable nonvolatile memory function, each of a first region, a second region, and a third region different from each other of a semiconductor substrate is forming a first gate insulating film on the main surface;
removing the gate insulating film, and forming a second gate insulating film thinner than the first gate insulating film on the main surface of the second region or the first region and the second region of the semiconductor substrate. forming an information storage gate electrode on the first gate insulating film in the first region or on the second gate insulating film in the first region; and forming an information storage gate electrode on the first gate insulating film in the third region. a step of etching the entire surface including the first region, the second region and the third region, and removing a second gate insulating film formed in the second region; forming a third gate insulating film on the main surface of the second region of the semiconductor substrate, and forming a fourth gate insulating film on the information storage gate electrode of the first region; A method for manufacturing a semiconductor integrated circuit device, comprising the steps of: forming a control gate electrode on a four-gate insulating film; and forming a gate electrode on a third gate insulating film in the second region. 2. A field effect transistor constituting a memory cell is formed on the main surface of the first region of the semiconductor substrate;
2. A field effect transistor with a low dielectric strength is formed on the main surface of the region, and a field effect transistor with a high dielectric strength is formed on the main surface of the third region. A method for manufacturing a semiconductor integrated circuit device. 3. At least a portion of the gate insulating film formed on the main surface of the first region of the semiconductor substrate is formed in the same process as a thin second gate insulating film formed on the main surface of the second region, and the electric field 3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the effect type transistor is a memory cell having an electrically erasable nonvolatile memory function.