JPH0366090A - Memory circuit - Google Patents

Abstract

PURPOSE:To prevent destruction of stored information of non-access cell at accessing by providing a means controlling in common a storage means of a memory cell connecting to a word line receiving a selection signal. CONSTITUTION:Write information is given to a ferroelectric capacitor 3 via a transistor (TR) 1-1 connecting to a word line W1 and a bit line B1 and write operation is implemented, then a clock pulse is given from an address decoder 4 to a drive line D1 from an address decoder 4 and applied also to a capacitor 3'. However, a bit line B2 is at the same high level as that of a readout state, a memory cell connecting to the word line W1 and the bit line B2 applies readout. Thus, when a low level is written in the capacitor 3', the its own polarization of the capacitor 3' is inverted by the readout operation and since the data of the same level as that stored so far is rewritten when the clock pulse is applied, the its own polarization restores and the destruction of a stored data is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a memory circuit equipped with a memory cell that stores information in a ferroelectric material, and particularly to a memory circuit that does not require a refresh operation.

(Prior Art) FIG. 3 is a diagram showing the structure of a memory cell of a conventional memory integrated circuit using a ferroelectric material.

In such a circuit configuration, the data write operation is
As shown in FIG. 4(a), after the potential of the bit line is set to a high potential level or a low potential level according to the data to be stored, the potential of the word line is raised to make field effect transistor 1 conductive, and node 2 is set to the data potential, and a pulse signal of clock φ is applied. This allows the capacitor to be made of, for example, lead zirconium titanate (PZT).
The direction of spontaneous polarization of the ferroelectric material 3 is set according to the data potential of the node 2, and data is written.

For example, in the case of high potential data, when the node 2 is at a high potential and the clock φ is at the "0" level, a large electric field is applied to the ferroelectric material 3 in the direction of the arrow 4, causing spontaneous polarization.

For low potential data, node 2 is at low potential level, clock φ
When is at a high potential level, ferroelectric material 3 produces spontaneous polarization in the direction of arrow 5. That is, the polarization direction of the arrow represents data, and since the polarization remains unchanged even when the power is turned off, nonvolatile data storage is possible.

To read the stored data, as shown in FIG. 4(b), the clock φ is set to a low potential, the bit line is placed in a floating state at a high potential, and the potential of the word line is raised to read out the memory cell to be accessed. transistor 1 is made conductive. This results in
Node 2 is at a high potential level, and ferroelectric 3 shows arrow 4.
An electric field is applied in the direction of .

Therefore, if the polarization direction is the same as arrow 4, the potential of the bit line will not change because no change will occur in the state. However, if the polarization state was in the direction of arrow 5, the polarization is reversed and becomes in the direction of arrow 4. At this time, the potentials of node 2 and the bit line decrease by an amount corresponding to the polarization inversion. In FIG. 4(b), the amount of inversion is indicated by 6. This drop in the potential of the bit line is amplified by the sense amplifier 7 connected to the bit line and output.

Thereafter, the clock φ-12 level is set to restore the polarization of the ferroelectric material 3 to perform rewriting. In this manner, the read operation is performed.

(Problems to be Solved by the Invention) Even with ferroelectric memory, it is desirable that it does not require periodic refresh operations like dynamic memory, and that data is not lost while the power is turned on. It is desirable that this is not the case.

However, in the case of the memory cell described above, there is a risk that data will be lost if it is not refreshed.

That is, in FIG. 3, it is assumed that after writing is performed with node 2 at a high potential level, the clock φ remains at a low potential level. In this state, the substrate node of the transistor is normally connected to Vss, so node 2, which was at a high potential level through the PN junction between the substrate and the source/drain, leaks and becomes a low potential level. It goes down to Therefore, when the clock φ for writing to another memory cell is input at this point, the electric field applied to the ferroelectric material is opposite to that when writing data at a high potential level, causing polarization reversal and data loss. A problem occurs. This is because when a pulse is applied to the clock φ, node 2 is cut off from the bit line and becomes a low potential level.

The present invention has been made in view of the above, and its purpose is to provide a statically operating non-volatile memory that prevents the destruction of stored information in non-accessed cells during access and eliminates the need for refresh operations. The purpose of this invention is to provide a flexible memory circuit.

[Structure of the invention]

(Means for Solving the Problem) In order to achieve the above object, a storage means for storing information as a polarization state of a ferroelectric substance is connected to a bit line via a transfer means whose conduction is controlled by a selection signal applied from a word line. In a memory circuit in which memory cells connected to a word line are arranged in a matrix, the present invention includes a control means for commonly controlling the storage means of the memory cells connected to the word line to which a selection signal is applied. It consists of

(Operation) In the above configuration, the present invention commonly controls the storage means of the respective memory cells connected to the same word line when the memory cell of this storage means is selected.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a diagram showing the configuration of a memory circuit according to an embodiment of the present invention.

In FIG. 1, the memory circuit includes a transfer transistor 1-1.1-2 whose gate is connected to a word line.
．． 2-1.2-2...... and a ferroelectric capacitor 3.3' whose one end is connected to the bit line via this transistor and the other end is connected to the drive line.・Memory cells consisting of are arranged in rows and columns. The read and write operations of each memory cell are similar to those shown in FIG.

Also, memory cells connected to the same word line are
They are connected to the same address decoder 4.5 and selectively driven. Furthermore, memory cells connected to the same word line have the other ends of their ferroelectric capacitors connected to the same drive line and are connected to the same address decoder as the word line. Control driven.

Next, the read and write operations of the entire memory circuit in such a configuration will be explained with reference to FIG.

Here, the memory cell to be accessed is the memory cell located at the intersection of bit line B and word line W+.

First, in a read operation, as shown in FIG. 2(b), the word line W1 is selected by the address decoder 4, and the transistors 1-1, 1-2 become conductive.

The sense amplifier 7 connected to the bit line B and the sense amplifier 7- connected to the bit line B2 both perform a read operation. However, sense amplifier 7'
A gate circuit (not shown) that transfers the output of 1 to an output i (not shown) is in a non-transfer state, and the sense amplifier 7' is in a non-selected state. Thereby, the data sense-amplified by the sense amplifier 7' via the bit line B2 is not read out to the outside.

On the other hand, since the sense amplifier 7 is in the selected state, the data sense-amplified by the sense amplifier 7 via the bit line B1 is read out from the sense amplifier 7.

Therefore, only the data held in the memory cell located at the intersection of word line WI and bit line B is read out.

Here, data at a high potential level is written to the node 2' of the ferroelectric material 3' connected to the drive line D1, and the spontaneous polarization state of the ferroelectric material 3' is as indicated by arrow 4 in FIG. Assume that the high potential level of node 2' drops to a low potential level due to leakage current from such a state.

In such a state, when the word line w1 is selected and becomes a read state, a current flows from the bit line B2, which is at a high potential level, to the node 2' through the transistor 1-2, which has become conductive, and the node 2'' becomes the high potential level. At this time, since the capacitance of node 2' is extremely small, even if current flows from bit line B2 to node 2'', the potential of bit line B2 is compared with the potential of bit line B2 by sense amplifier 7- during the read operation. The voltage will not drop below the comparison reference voltage.

Therefore, the potential of the bit line B2 is slightly lower than the original potential of the bit line B2 due to the charging of the node 2', but due to the read operation performed by the sense amplifier 7', the potential of the bit line B2 is reduced to the original high potential level of the bit line B2. recovers to.

Therefore, data at the high potential level before being lowered due to leakage current is rewritten to node 2'.

Therefore, in a read operation, when the potential of node 2' drops from a high potential level to a low potential level due to leakage current, even if a lock pulse is applied to the drive line D1 as shown in FIG. The spontaneous polarization state of the ferroelectric capacitor 3'' becomes the state before the read operation, and the destruction of the held data is prevented.

On the other hand, since no clock pulse is applied to memory cells connected to unselected word lines via the drive line D2, the spontaneous polarization state of the ferroelectric capacitor remains unchanged.

Next, in the write operation, as shown in FIG. 2(a), write information is applied from the sense amplifier 7 to the bit line B, and this write information is applied to the selected word m W +
A write operation is performed by applying the signal to the ferroelectric capacitor 3 via the transistor 1-1 connected to the ferroelectric capacitor 3.

At this time, as shown in FIG. 2(a), a clock pulse is applied from the address decoder 4 to the drive line.

Therefore, a clock pulse is also applied to the ferroelectric capacitor 3' of the memory cell connected to the word line w1.

However, no write information is applied to the bit line B2 connected to the memory cell of this ferroelectric capacitor 3', and the bit line B2 is in a floating state at the same high potential level as in the read state. Therefore, even if a clock pulse is applied from address decoder 4 via drive line DI, the memory cells connected to word line W and bit line B2 perform a read operation.

Therefore, if a low potential level has been written to the ferroelectric capacitor 3', the spontaneous polarization of the ferroelectric capacitor 3' is reversed by the read operation, but when a clock pulse is applied to the drive line D1, Since data at the same level as the previously held data is rewritten, the spontaneous polarization state returns to its original state. Therefore, even if a clock pulse is applied to the drive line, the held data is prevented from being destroyed.

On the other hand, in the memory cells connected to the unselected word line W2, the transistors 2-1 and 2-2 remain non-conductive, but the ferroelectric capacitors 3.3' of these memory cells No clock pulse is applied from the address decoder 5 via the drive line D2. Therefore, even if the potential at node 2.degree. 21 drops from a high potential level to a low potential level due to leakage, the spontaneous polarization of the ferroelectric capacitor does not change, and storage information is prevented from being inverted or destroyed.

〔Effect of the invention〕

As explained above, according to the present invention, the storage means of the respective memory cells connected to the same word line are commonly controlled when the memory cell of this storage means is selected. Destruction of information can be prevented. Thereby, it is possible to provide a memory circuit that stores information in a statically operated nonvolatile ferroelectric material that does not require a refresh operation.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a memory circuit according to the present invention, FIG. 2 is a timing diagram explaining the operation of the circuit in FIG. 1, FIG. 3 is a configuration diagram of a memory circuit according to the prior art, and FIG. 4 is a timing diagram illustrating the operation of the circuit of FIG. 3. FIG. 1-1.1-2.2-1.2-2...MOS) transistor, 3.3'...ferroelectric capacitor, 4.5...address decoder, 7.7'... Sense amplifier, w,, w2... word line, B,, B2... bit line, D,, D2... drive line.

Claims (1)

[Claims] A storage means for storing information as a polarization state of a ferroelectric substance,
In a memory circuit in which memory cells are arranged in a matrix, each memory cell is connected to a bit line via a transfer means whose conduction is controlled by a selection signal applied from a word line. A memory circuit comprising a control means for commonly controlling the storage means of the memory cells.