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JPH0363929U - - Google Patents

Info

Publication number
JPH0363929U
JPH0363929U JP1989124255U JP12425589U JPH0363929U JP H0363929 U JPH0363929 U JP H0363929U JP 1989124255 U JP1989124255 U JP 1989124255U JP 12425589 U JP12425589 U JP 12425589U JP H0363929 U JPH0363929 U JP H0363929U
Authority
JP
Japan
Prior art keywords
bump electrode
bonding pad
neck portion
head
conductive adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1989124255U
Other languages
Japanese (ja)
Other versions
JPH085550Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989124255U priority Critical patent/JPH085550Y2/en
Publication of JPH0363929U publication Critical patent/JPH0363929U/ja
Application granted granted Critical
Publication of JPH085550Y2 publication Critical patent/JPH085550Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/98—Methods for disconnecting semiconductor or solid-state bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11822—Applying permanent coating, e.g. in-situ coating by dipping, e.g. in a solder bath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13563—Only on parts of the surface of the core, i.e. partial coating
    • H01L2224/13565—Only outside the bonding interface of the bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図ないし第５図は本考案の一実施例を示す
ものである。第１図は半導体装置の縦断面図であ
る。第２図はバンプ電極にペースト状導電性接着
剤を転写する工程を示す縦断面図である。第３図
は適当なバンプ電極の形状を得るための説明に供
されるバンプ電極の縦断面図である。第４図はネ
ツク部と頭部との適当な寸法の範囲を示すグラフ
である。第５図ａは不良半導体チツプを取り外す
工程を示す縦断面図である。第５図ｂは導電性接
着剤層の残滓を示す平面図である。第６図ないし
第８図は従来例を示すものである。第６図は半導
体装置の縦断面図である。第７図はバンプ電極に
ペースト状導電性接着剤を転写する工程を示す縦
断面図である。第８図ａは不良半導体チツプを取
り外す工程を示す縦断面図である。第８図ｂは導
電性接着剤層の残滓を示す平面図である。 １……半導体チツプ、２……バンプ電極、２ａ
……ネツク部、２ｂ……頭部、３……導電性接着
剤層、４……薄膜回路基板、５……ボンデイング
パツドである。 1 to 5 show an embodiment of the present invention. FIG. 1 is a longitudinal sectional view of the semiconductor device. FIG. 2 is a longitudinal sectional view showing a process of transferring a paste conductive adhesive onto a bump electrode. FIG. 3 is a longitudinal sectional view of a bump electrode used for explanation of obtaining a suitable bump electrode shape. FIG. 4 is a graph showing the range of suitable dimensions for the neck portion and the head portion. FIG. 5a is a longitudinal sectional view showing the process of removing a defective semiconductor chip. FIG. 5b is a plan view showing the residue of the conductive adhesive layer. 6 to 8 show conventional examples. FIG. 6 is a longitudinal cross-sectional view of the semiconductor device. FIG. 7 is a longitudinal sectional view showing a process of transferring a paste conductive adhesive onto a bump electrode. FIG. 8a is a longitudinal sectional view showing the process of removing a defective semiconductor chip. FIG. 8b is a plan view showing the residue of the conductive adhesive layer. 1...Semiconductor chip, 2...Bump electrode, 2a
. . . network portion, 2b . . . head, 3 . . . conductive adhesive layer, 4 . . . thin film circuit board, 5 . . . bonding pad.

Claims (1)

【実用新案登録請求の範囲】 半導体チツプの内部配線に接続されたネツク部
とネツク部の先端に形成されたネツク部より径の
大きい頭部とを有するバンプ電極が半導体チツプ
に突設され、上記バンプ電極の頭部が、回路基板
上に形成された電極としてのボンデイングパツド
に当接され、バンプ電極の頭部とボンデイングパ
ツドとの当接部周囲が導電性接着剤層によつて被
覆されることにより、バンプ電極がボンデイング
パツドに固着されると共に、バンプ電極とボンデ
イングパツドとが電気的に接続されている半導体
装置において、 上記導電性接着剤層は、バンプ電極のネツク部
に達してバンプ電極の頭部全体を包みこんでいる
ことを特徴とする半導体装置。[Scope of Claim for Utility Model Registration] A bump electrode is provided protruding from a semiconductor chip, and has a neck portion connected to internal wiring of the semiconductor chip and a head portion formed at the tip of the neck portion and having a larger diameter than the neck portion. The head of the bump electrode is brought into contact with a bonding pad as an electrode formed on the circuit board, and the area around the contact area between the head of the bump electrode and the bonding pad is covered with a conductive adhesive layer. In a semiconductor device in which the bump electrode is fixed to the bonding pad and the bump electrode and the bonding pad are electrically connected, the conductive adhesive layer is attached to the neck portion of the bump electrode. A semiconductor device characterized in that the bump electrode reaches up and wraps around the entire head of the bump electrode.
JP1989124255U 1989-10-23 1989-10-23 Semiconductor device Expired - Lifetime JPH085550Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989124255U JPH085550Y2 (en) 1989-10-23 1989-10-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989124255U JPH085550Y2 (en) 1989-10-23 1989-10-23 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0363929U true JPH0363929U (en) 1991-06-21
JPH085550Y2 JPH085550Y2 (en) 1996-02-14

Family

ID=31672187

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989124255U Expired - Lifetime JPH085550Y2 (en) 1989-10-23 1989-10-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH085550Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2008136304A1 (en) * 2007-04-28 2010-07-29 木村　太 Golf putter practice device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63276237A (en) * 1987-05-08 1988-11-14 Citizen Watch Co Ltd Method for bonding integrated circuit to substrate
JPS6439043A (en) * 1987-08-05 1989-02-09 Nippon Denso Co Semiconductor integrated circuit device
JPH01232735A (en) * 1988-03-11 1989-09-18 Matsushita Electric Ind Co Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63276237A (en) * 1987-05-08 1988-11-14 Citizen Watch Co Ltd Method for bonding integrated circuit to substrate
JPS6439043A (en) * 1987-08-05 1989-02-09 Nippon Denso Co Semiconductor integrated circuit device
JPH01232735A (en) * 1988-03-11 1989-09-18 Matsushita Electric Ind Co Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2008136304A1 (en) * 2007-04-28 2010-07-29 木村　太 Golf putter practice device

Also Published As

Publication number Publication date
JPH085550Y2 (en) 1996-02-14

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term