JPH0363850A - Store system - Google Patents

Abstract

PURPOSE:To accelerate the processing of a store request on a data array by selecting readout data from the data array and store data in bit unit according to the output of a detection circuit which judges the hit of the readout data in an address array and the write position data of the store data to a main storage. CONSTITUTION:The address array 40 is indexed with an address shown by a signal line 102, and is compared with part of a request address shown by a signal line 101 at the detection circuit 60. When the output of the detection circuit 60 shows 1, the data array 50 performs the write of the store data on a signal line 201 according to a logic value on a signal line 301. Also, a data synthesis circuit 70 selects and outputs the readout data on the signal lines 201 and 501 according to the logic value on the signal line 301. Also, when the output of the detection circuit 60 shows 0, the data array 50 performs only the readout of the content of the store data, and the data synthesis circuit 70 selects and outputs the store data on the signal line 201. In such a way, it is possible to evade to make the processing of a following request await.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a storage method for an information processing device, and more particularly to a storage method for an information processing device that includes a data array that can be specified for writing in arbitrary bit units.

[Conventional technology]

In the storage method of conventional information processing devices, the first cycle determines the cash bit and reads the contents of the data array, and the second cycle combines the read data from the data array with the stored data. A method has been used in which synthetic data is written into a data array.

[Problem to be solved by the invention]

In the conventional store method described above, the data array is read in the first cycle for one store request, and the synthesized data is written to the data array in the second cycle, so it takes two cycles. This method has the disadvantage that the data array must be occupied for a while, and subsequent requests must be processed.

[Means to solve the problem]

The storage method of the present invention includes: a data array that can be specified for writing in arbitrary bit units and stores a copy of main memory data; an address array that associates the contents of the data array with the contents of the main memory; Selecting read data and store data from the data array in bit units according to a detection circuit that determines bits of read data, write position data indicating a write position of store data to main memory, and the output of the detection circuit. and a data synthesis circuit that outputs the data.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a store method according to the present invention. 10.20.30 in Figure 1
are registers, 40 is an address array, 50 is a data array, 60 is a detection circuit, and 70 is a data synthesis circuit.

The address register 10 receives and holds the address of a store request, and the address array 40 manages correspondence with the address register 10 by storing a part of the requested address indicated by the signal line 101. Detection circuit 60
compares the contents of the address array 40 and the request address, and outputs a logic "1" when the two match. Note that a cash bit is generated when the logical value on the signal line 601 is "1". The data register 20 is
The data array 50 holds the data of the store request, is indexed at the same time as the address value of the address array 40 is determined by the address register 10, and read data is sent out on the signal line 501.

The mask register 30 holds mask data indicating the position where store data is written to main memory (not shown).The data synthesis circuit 70 connects the signal line 6 from the detection circuit 60
When the output on the signal line 601 is logic 1 and the output from the mask register 30 on the signal line 301 is logic 0, the read data on the signal line 501 is selected bit by bit, and the logic on the signal line 601 is selected. When the value is "O" or when the logical value on the signal line 301 is "1", the store data on the signal line 201 is selected bit by bit and output on the signal line 701. The logical value on the signal line 601 is “
1'', the logical value on the signal line 301 writes the store data on the signal line 201 corresponding to the bit of “1”.

Next, the operation of the embodiment having the above configuration will be explained. Here, as the operation of this embodiment, a store method for 8-byte store data will be described.

Now, assuming that the writing position to the main memory is byte 0°1.2, the mask register 30 has a logical value “1110000”.
Next, the address array 40 is indexed by the address indicated by the signal line 102, and the detection circuit 60 compares it with a portion of the requested address indicated by the signal line 101.

The logic value on the signal line 601 which is the output of the detection circuit 60 is “
1”, the data array 50 writes the store data on the signal line 201 in bytes 0, 1.2 according to the logical value “11100000” on the signal line 301, and in bytes 3 to 7, the data array 50 writes the store data on the signal line 201 in bytes 0 and 1.2. The contents of the array are simultaneously read and the read data is sent out on the signal line 501.
Logical value “1110.0000” on 01 G: Therefore, in byte 0.1.2, store data on signal line 201 is selected, and in bytes 3 to 7, read data on signal line 501 is selected and output. .

Further, when the output of the detection circuit 60 is logic "O", the data array 50 only reads the contents of the data array 50 in all bytes and sends the read data onto the signal line 501. The data synthesis circuit 70 includes the detection circuit 6
Since the logical value on the signal line 601, which is an output of 0, is "0", the store data on the signal line 201 is selected and output in all bytes.

〔Effect of the invention〕

As explained above, the present invention uses a store method that has a data array that can be specified for writing bit by bit, so that it is possible to read the data array and write store data in the same cycle. This has the effect of speeding up the processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a store method according to the present invention. DESCRIPTION OF SYMBOLS 10... Address register, 20... Data register, 30... Mask register, 40... Address array, 50... Data array, 60... Detection circuit,
70...Data synthesis circuit.

Claims (1)

[Claims] A data array that can be specified for writing in arbitrary bit units and stores a copy of main memory data, an address array that associates the contents of the data array with the contents of the main memory, and a bit of read data from the address array is determined. a data synthesis circuit that selects and outputs read data and store data from the data array bit by bit according to a detection circuit, write position data indicating a write position of store data to main memory, and an output of the detection circuit; A store method characterized by comprising: